NXP Semiconductors MPC5644A Reference Manual page 600

Error Correction Status Module (ECSM)
Register address: ECSM Base + 0x0060 (0xFFF4_0060)
0 1
R
W
Reset — —
16 17
R
W
Reset — —
= Unimplemented
Name
0–31 RAM ECC Address Register
REAR[31:0] This 32-bit register contains the faulting access address of the last, properly-enabled RAM ECC
event.
18.4.4.9 RAM ECC Syndrome Register (ECSM_PRESR)
The ECSM_PRESR is an 8-bit register for capturing the error syndrome of the last, properly-enabled ECC
event in the RAM memory. Depending on the state of the ECC Configuration Register, an ECC event in
the RAM causes the address, attributes and data associated with the access to be loaded into the
ECSM_REAR, ECSM_PRESR, ECSM_REMR, ECSM_REAT and ECSM_REDR registers, and the
appropriate flag (RNCE) in the ECC Status Register to be asserted.
The ECSM_PRESR can only be read from the IPS programming model; any attempted write is ignored.
Register address: ECSM Base + 0x0065 (0xFFF4_0065)
0
R
W
Reset —
Figure 18-12. RAM ECC Syndrome Register (ECSM_PRESR)
600
2 3 4 5 6
— — — — —
18 19 20 21 22
— — — — —
Figure 18-11. RAM ECC Address Register (ECSM_REAR)
Table 18-13. ECSM_REAR field description
1 2
— —
= Unimplemented
MPC5644A Microcontroller Reference Manual, Rev. 6
7 8 9 10
REAR[31:16]
— — — —
23 24 25 26
REAR[15:0]
— — — —
Description
3 4 5
PRESR[7:0]
— — —
11 12 13 14 15
— — — — —
27 28 29 30 31
— — — — —
6 7
— —
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