NXP Semiconductors MPC5644A Manuals

Manuals and User Guides for NXP Semiconductors MPC5644A. We have 1 NXP Semiconductors MPC5644A manual available for free PDF download: Reference Manual

NXP Semiconductors MPC5644A Reference Manual (1735 pages)

microcontroller

Brand: NXP Semiconductors | Category: Controller | Size: 17 MB

Table of Contents
3
The MPC5644A Microcontroller Family
27
MPC5644A and MPC5642A Device Comparison
28
Device Block Diagram
30
Feature Summary
32
Chapter 1

33
- Feature Details
  33
- Crossbar Switch (XBAR)
  34
Chapter 15 Interrupt Controller

35
Chapter 13

36
Memory Protection Unit (MPU)

36
- Fmpll
  37
Chapter 12 Flash Memory

38
- Emios
  40
- Reaction Module
  42
  - Dspi
    44
  - Esci
    45
  - Flexcan
    46
Chapter 33 Flexray

47
Chapter 19 Software Watchdog Timer (SWT)

48
Chapter 18 Error Correction Status Module (ECSM)

49
Chapter 35 Power Management Controller (PMC)

50
Chapter 38 Development Trigger Semaphore (DTS)

51
- Introduction
  53
Chapter 3

57
Chapter 2

58
- Signal Properties
  58
- Signal Details
  85
Chapter 4

93
- Reset Sources
  93
- Reset Vector
  94
  - FMPLL Lock Gating Signal
    95
  - Power-On Reset (POR)
    98
  - Loss of Clock
    99
  - JTAG Reset
    100
  - Reset Configuration
    101
  - Reset Configuration Timing
    103
  - Reset Weak Pull Up/Down Configuration
    104
  - Overview
    105
Chapter 5 Clock Architecture

106
- Block Diagram
  107
- FMPLL Modes of Operation
  109
- Introduction
  117
- Configuring Hardware Features
  118
Chapter 6

119
- Frequency-Modulated PLL
  119
- Flash Bus Interface Unit
  120
- Cache
  121
- Memory Management Unit (MMU)
  123
- Application Software
  124
  - Signal Processing Extension
    125
  - Hardware Single Precision Floating Point
    126
- Peripherals and General Application Guidelines
  127
- Performance Optimization Checklist
  128
- Overview
  131
- Microarchitecture Summary
  132
Chapter 7

134
- Instruction Unit Features
  134
- Integer Unit Features
  135
- E200Z4 System Bus Features
  136
  - Introduction
    137
  - Modes of Operation
    138
  - External Signal Description
    139
  - Register Descriptions
    146
  - Functional Description
    172
Chapter 8 Edma Basic Data Flow

173
- Initialization / Application Information
  176
  - DMA Programming Errors
    178
  - DMA Request Assignments
    179
  - DMA Arbitration Mode Considerations
    182
  - DMA Transfer
    183
  - TCD Status
    186
  - Channel Linking
    188
  - Dynamic Programming
    189
    
    Introduction
    193
    
    Features
    194
- XBAR Registers
  195
Chapter 9

196
- XBAR Register Descriptions
  196
- Coherency
  201
- Function
  202
- Priority Assignment
  203
Chapter 10

205
- PBRIDGE Features
  205
- PBRIDGE Signal Description
  206
  - Register Descriptions
    208
  - Introduction
    213
  - External Signal Description
    214
Chapter 11

215
- Access Timing
  215
  - Initialization and Application Information
    216
  - Introduction
    217
  - Block Diagram
    218
  - Features
    219
  - Modes of Operation
    220
Chapter 23

221
- Module Memory Map
  221
  - Register Descriptions
    223
  - Functional Description
    245
- Utest Mode
  246
- Flash Programming
  249
- Flash Erase
  252
- Flash Shadow Block
  255
- Flash Reset
  256
  - Introduction
    257
  - Modes of Operation
    258
  - Register Descriptions
    260
  - Functional Description
    271
  - Initialization Information
    272
  - Information Specific to this Device
    275
  - Overview
    276
  - Features
    278
  - External Signal Description
    281
- Detailed Signal Descriptions
  282
- Signal Output Buffer Enable Logic by Mode
  284
  - Register Descriptions
    285
  - Functional Description
    295
- External Bus Operations
  300
- Initialization/Application Information
  333
- Running with Asynchronous Memories
  334
- Connecting an Mcu to Multiple Memories
  336
- EBI Operation with Reduced Pinout Mcus
  337
- Summary of Differences from Mpc5Xx
  338
  - Information Specific to this Device
    341
  - Overview
    342
  - Features
    345
  - External Signal Description
    347
  - Register Descriptions
    348
  - Functional Description
    354
- Priority Management
  368
- Details on Handshaking with Processor
  370
- Initialization and Application Information
  372
- ISR, RTOS, and Task Hierarchy
  374
- Order of Execution
  375
- Priority Ceiling Protocol
  376
- Deadlines
  377
- Lowering Priority Within an ISR
  378
- Examining LIFO Contents
  379
  - Overview
    381
  - Modes of Operation
    382
  - Signal Description
    383
  - Memory Map and Register Descriptions
    384
Chapter 16

387
Chapter 17

576
- Lock Detection
  576
- Frequency Modulation
  579
  - Overview
    583
  - Register Descriptions
    584
- Miscellaneous Wakeup Control Register (ECSM_MWCR)
  585
- Miscellaneous User-Defined Control Register (ECSM_MUDCR)
  586
- ECC Registers
  587
  - Information Specific to this Device
    607
  - Register Descriptions
    608
  - Functional Description
    612
  - Introduction
    613
- Memory Map
  614
  - Functional Description
    619
  - Overview
    621
Chapter 21

622
- Internal Boot Mode
  622
- BAM Program Operation
  623
- Reset Configuration Half Word (RCHW)
  626
- Internal Boot Mode
  628
- Serial Boot Mode
  630
- Booting from the External Bus Interface (EBI)
  637
- Device-Specific Features
  639
  - Features
    640
  - Modes of Operation
    641
- External Signals Description
  642
Chapter 22

649
- Global Registers
  649
- Channel Registers
  652
- Functional Description
  660
- IP Bus Interface Unit (BIU)
  684
- Global Clock Prescaler Submodule (GCP)
  686
  - Introduction
    689
  - Block Diagram
    691
  - Signal Description
    695
  - Reacm_Rchn — REACM Channel (N) Output Pin A, B and C
    696
- REACM Module Configuration Register (REACM_MCR)
  697
- REACM Timer Configuration Register (REACM_TCR)
  699
- REACM Threshold Router Register (REACM_THRR)
  700
- REACM ADC Sensor Input Register (REACM_SINR)
  701
- REACM Global Error Flag Register (REACM_GEFR)
  702
- REACM Channel N Configuration Register (Reacm_Chcrn)
  703
- REACM Channel N Status Register (Reacm_Chsrn)
  705
- REACM Channel N Router Register (Reacm_Chrrn)
  708
- REACM Shared Timer Bank Registers (REACM_STBK)
  710
- REACM Threshold Bank Register (REACM_THBK)
  711
- REACM ADC Result Maximum Limit Check Register (REACM_ADCMAX)
  712
- REACM Modulation Minimum Pulse Width Register (REACM_MINPWD)
  713
- REACM Modulation Control Word Bank Registers (REACM_MWBK)
  714
- Functional Description
  717
- Modulation Control Words Bank
  719
- Shared Timer Bank
  720
- Hold-Off Timer Bank
  721
- Threshold Bank and Comparator
  722
- ADC Interface
  723
- Prescalers
  725
- Modulation Modes
  727
  - Limitations on the Modulation Process
    728
- Monitored Modulation
  731
- DMA Support
  734
- Reset Overview
  735
  - Interrupt Sources
    736
  - Advancing Modulation Phase on a Threshold Level
    742
  - Controlling the Loop Function
    743
  - Banked Mode
    744
  - Information Specific to this Device
    745
- Overview
  746
  - Features
    752
  - Modes of Operation
    756
  - External Signal Description
    758
- Memory Map/Register Definition
  760
Chapter 24

767
- System Configuration Registers
  767
- Time Base Registers
  781
- Engine Related Registers
  790
- Channel Registers Layout
  792
- Channel Configuration and Control Registers
  801
- Functional Description
  810
  - Host Interface
    823
  - Scheduler
    829
  - Parameter Sharing and Coherency
    836
  - Enhanced Channels
    840
  - Time Bases
    885
  - EAC – Etpu Angle Counter
    893
  - Microengine
    912
  - Microinstruction Set
    929
  - Test and Development Support
    962
- Initialization/Application Information
  969
  - Reset Options
    970
  - Programming Hints and Caveats
    971
  - Estimating Worst-Case Latency
    972
  - Endianness
    988
  - Initialization Code Example
    992
  - Predefined Channel Mode Summary
    995
  - MISC Algorithm
    999
  - Information Specific to this Device
    1001
Chapter 25

1002
- Availability of Analog Inputs
  1002
- Block Diagram
  1003
  - Features
    1004
  - Modes of Operation
    1006
- Debug Mode
  1007
- Stop Mode
  1008
- External Signal Description
  1009
- Detailed Signal Descriptions
  1011
- Memory Map/Register Definition
  1015
- EQADC Register Descriptions
  1019
- On-Chip ADC Registers
  1057
- Functional Description
  1071
- Data Flow in EQADC
  1072
- Command/Result Queues
  1089
- EQADC Command Fifos
  1090
- EQADC Result Fifos
  1118
- On-Chip ADC Configuration and Control
  1122
- Internal/External Multiplexing
  1134
- EQADC Synchronous Serial Interface (SSI) Sub-Block
  1143
- EQADC Parallel Side Interface (PSI) Sub-Block
  1148
- Analog Sub-Block
  1151
- Initialization/Application Information
  1154
  - EQADC/DMAC Interface
    1159
  - Sending Immediate Command Setup Example
    1160
  - Modifying Queues
    1161
  - Cqueue and Rqueues Usage
    1162
  - ADC Result Calibration
    1164
- Information Specific to this Device
  1171
  - Features
    1173
  - Modes of Operation
    1174
- External Signal Description
  1175
Chapter 26

1176
- Integrator Halt Signal
  1176
- Decimation Filter Register Descriptions
  1178
- Decimation Filter Memory Map for Parallel Side Interface
  1199
- PSI Register Description
  1200
- Functional Description
  1202
  - Output Buffer Description
    1204
  - Bypass Configuration Description
    1205
  - IIR and FIR Filter
    1206
  - Filter Prefill Control Description
    1209
  - Timestamp Data Transmission
    1210
  - Soft-Reset Command Description
    1211
  - Interrupts Requests Description
    1212
  - DMA Requests Description
    1213
  - Freeze Mode Description
    1214
  - Integrator
    1215
  - Cascade Mode Description
    1218
- Initialization Information
  1224
- Filter Example Simulation
  1225
  - Input Data Calculation
    1226
  - Filter Results
    1227
  - Overview
    1229
Chapter 27 Temperature Formula

1230
- Registers
  1232
- Overview
  1235
- Overview
  1237
Chapter 28

1238
Chapter 29

1238
- Calculating a CRC Checksum
  1238
  - Configuring the Context
    1239
  - Initializing the Context Seed Value
    1240
  - Reading the Checksum
    1241
  - CRC Configuration Register (CRC_CFG)
    1242
  - CRC Input Register (CRC_INP)
    1243
  - CRC Current Status Register (CRC_CSTAT)
    1244
  - CRC Output Register (CRC_OUTP)
    1245
- Use Cases and Limitations
  1246
- Introduction
  1251
Chapter 36 Features

1252
- DSPI Configurations
  1253
Chapter 30

1254
- SPI Configuration
  1254
- CSI Configuration
  1255
- Modes of Operation
  1256
- External Signal Description
  1257
Chapter 31 Memory Map and Register Definition

1258
- Register Descriptions
  1260
- Functional Description
  1290
  - Start and Stop of DSPI Transfers
    1291
  - Deserial Serial Interface (DSI) Configuration
    1294
  - Combined Serial Interface (CSI) Configuration
    1301
  - DSPI Baud Rate and Clock Delay Generation
    1302
  - Transfer Formats
    1304
  - Continuous Serial Communications Clock
    1313
  - Timed Serial Bus (TSB)
    1315
  - Parity Generation and Check
    1317
  - Interrupts/Dma Requests
    1318
  - Buffered SPI Operation
    1320
  - Continuous Peripheral Chip Select
    1321
  - Modified SPI Transfer Format
    1322
  - DSPI Connections to Etpu_A, Emios and SIU
    1323
  - Power Saving Features
    1330
  - Initialization/Application Information
    1331
  - Switching Master and Slave Mode
    1332
  - Delay Settings
    1333
  - Calculation of FIFO Pointer Addresses
    1334
    
    Introduction
    1337
    
    Overview
    1338
    
    Features
    1339
    
    Modes of Operation
    1340
- Memory Map and Register Definition
  1341
  - Register Descriptions
    1342
  - Functional Description
    1356
  - Baud Rate and Clock Generation
    1359
  - Baud Rate Tolerance
    1361
  - SCI Mode
    1363
  - LIN Mode
    1377
    
    Interrupts
    1386
    
    Application Information
    1387
    
    Information Specific to this Device
    1389
    
    Overview
    1391
    
    Modes of Operation
    1392
    
    External Signal Description
    1393
    
    Signal Descriptions
    1394
  - Message Buffer Architecture
    1396
  - Message Buffer Structure
    1398
  - Rx FIFO Structure
    1401
    
    Register Descriptions
    1403
    
    Functional Description
    1421
  - Transmit Process
    1422
  - Receive Process
    1423
  - Matching Process
    1424
  - Data Coherence
    1426
  - Rx FIFO
    1428
  - CAN Protocol Related Features
    1430
    
    Modes of Operation Details
    1434
    
    Interrupts
    1436
  - Bus Interface
    1437
  - Flexcan Addressing and RAM Size Configurations
    1438
  - Introduction
    1441
  - Color Coding
    1442
    
    Features
    1444
    
    Modes of Operation
    1445
    
    External Signal Description
    1446
- Controller Host Interface Clocking
  1447
  - Oscillator Clocking
    1448
    
    Register Descriptions
    1454
    
    Functional Description
    1531
  - Message Buffer Types
    1533
  - Flexray Memory Area Layout
    1538
  - Physical Message Buffer Description
    1541
  - Individual Message Buffer Functional Description
    1551
  - Individual Message Buffer Search
    1578
  - Individual Message Buffer Reconfiguration
    1580
  - Receive Fifos
    1581
  - Channel Device Modes
    1587
  - External Clock Synchronization
    1589
  - Sync Frame ID and Sync Frame Deviation Tables
    1590
  - MTS Generation
    1593
  - Key Slot Transmission
    1594
  - Sync Frame Filtering
    1595
  - Strobe Signal Support
    1596
  - Timer Support
    1597
  - Slot Status Monitoring
    1598
  - System Bus Access
    1601
  - Interrupt Support
    1602
  - Lower Bit Rate Support
    1607
  - CHI Lookup-Table Memory (CHI LRAM)
    1608
  - Memory Content Error Detection
    1609
  - Memory Error Injection
    1614
- Application Information
  1616
  - Initialization Sequence
    1617
  - Shut down Sequence
    1618
  - Number of Usable Message Buffers
    1619
  - Protocol Control Command Execution
    1620
  - Message Buffer Search on Simple Message Buffer Configuration
    1621
    
    Information Specific to this Device
    1625
    
    Overview
    1626
- Signal Description
  1627
  - Functional Description
    1631
  - Interrupts
    1632
- Initialization and Application Information
  1633
- Introduction
  1635
  - Block Diagram
    1636
  - External Signal Description
    1637
  - Memory Map/Register Definition
    1638
  - Module Configuration Register (MCR)
    1639
  - Trimming Register (TRIMR)
    1641
  - Status Register (SR)
    1644
  - Functional Description
    1647
  - V Internal Voltage Regulator
    1648
  - V Lvi
    1650
  - V Voltage Regulator Controller
    1651
  - Soft-Start (for 1.2 V and 3.3 V Regulators)
    1655
- Electrical Characteristics
  1656
  - Information Specific to this Device
    1657
  - Introduction
    1658
  - Modes of Operation
    1659
  - External Signal Description
    1660
- Register Definition
  1661
  - Functional Description
    1664
  - JTAGC Block Instructions
    1666
  - Boundary Scan
    1668
    
    Initialization/Application Information
    1669
    
    Information Specific to this Device
    1671
  - Parameter Values
    1672
    
    Introduction
    1673
    
    Overview
    1674
    
    Modes of Operation
    1675
    
    External Signal Description
    1676
- Register Definition
  1677
  - Register Descriptions
    1678
  - Functional Description
    1682
  - Ieee 1149.1-2001 (Jtag) Tap
    1685
  - Nexus JTAG Port Sharing
    1690
  - Nexus Reset Control
    1691
  - Introduction
    1693
- DTS Device Connections
  1694
  - DTS Register Access
    1695
- Memory Map
  1696
  - DTS Startup Register (DTS_STARTUP)
    1697
  - DTS Semaphore Register (DTS_SEMAPHORE)
    1698
- Example Application
  1699

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NXP Semiconductors MPC5644A Manuals

NXP Semiconductors MPC5644A Reference Manual (1735 pages)

Table of Contents

Chapter 1

Chapter 15 Interrupt Controller

Chapter 13

Memory Protection Unit (MPU)

Chapter 12 Flash Memory

Chapter 33 Flexray

Chapter 19 Software Watchdog Timer (SWT)

Chapter 18 Error Correction Status Module (ECSM)

Chapter 35 Power Management Controller (PMC)

Chapter 38 Development Trigger Semaphore (DTS)

Chapter 3

Chapter 2

Chapter 4

Chapter 5 Clock Architecture

Chapter 6

Chapter 7

Chapter 8 Edma Basic Data Flow

Chapter 9

Chapter 10

Chapter 11

Chapter 23

Chapter 16

Chapter 17

Chapter 21

Chapter 22

Chapter 24

Chapter 25

Chapter 26

Chapter 27 Temperature Formula

Chapter 28

Chapter 29

Chapter 36 Features

Chapter 30

Chapter 31 Memory Map and Register Definition

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