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Resets
4.5.6
JTAG reset
A system reset occurs when JTAG is enabled and either the EXTEST, CLAMP, or HIGHZ instructions are
executed by the JTAG controller. The internal reset signal is asserted. The state of the RSTOUT pin is
determined by the JTAG instruction. The value on the WKPCFG pin is applied at the assertion of the
internal reset signal, as is the PLLREF value. After the JTAG reset request is negated, the reset controller
waits for a predetermined number of clock cycles (refer to
finishes the WKPCFG and BOOTCFG[0:1] pins are sampled, and the associated bits/fields are updated in
the SIU_RSR. The reset status bits in the SIU_RSR are unaffected. Refer to
(JTAGC),
for more information.
4.5.7
Software system reset
A Software System Reset is caused by a write to field SIU_SRCR[SSR]; see
Control Register (SIU_SRCR).
The internal reset signal and RSTOUT pin are asserted. The value on the WKPCFG pin is applied at the
assertion of the internal reset signal (assertion of RSTOUT), as is the PLLREF value. SIU_SRCR[SSR] is
automatically cleared and the reset controller waits for a predetermined number of clock cycles (refer to
Section 4.3.2,
RSTOUT"). Once the clock count finishes the WKPCFG and BOOTCFG[0:1] pins are
sampled. The reset controller then waits four clock cycles before negating RSTOUT, and the associated
bits/fields are updated in the SIU_RSR. In addition, SIU_RSR[SSRS] is set, and all other reset status bits
in the SIU_RSR are cleared.
4.5.8
Software external reset
A write of '1' to field SIU_SRCR[SER] causes the external RSTOUT pin to be asserted for a
predetermined number of clock cycles (refer to
automatically clears after the clock counting expires. A Software External Reset does not cause a reset of
the MCU, the BAM program is not executed, the PLLREF, BOOTCFG, and WKPCFG pins are not
sampled. Field SIU_RSR[SERF] is set, but no other status bits are affected. SIU_RSR[SERF] is not
automatically cleared and remains set until cleared by software or another reset besides the Software
External Reset occurs.
For a Software External Reset, the e200z4 core will continue to execute instructions, timers that are
enabled will continue to operate, and interrupt requests will continue to be processed. The application must
ensure that devices connected to RSTOUT are not accessed during a Software External Reset, and it must
determine how to manage MCU resources when using the Software External Reset.
4.6
Reset registers in the SIU
The System Integration Unit (SIU) on this device includes two registers, SIU_RSR and SIU_SRCR, that
affect the reset behavior of this device. See
these registers.
100
A write of '1' to SIU_SRCR[SSR] causes an internal reset of the MCU.
Section 4.3.2,
Chapter 16, System Integration Unit (SIU),
MPC5644A Microcontroller Reference Manual, Rev. 6
Section 4.3.2,
RSTOUT). Once the clock count
Chapter 36, JTAG Controller
Section 16.6.5, System Reset
RSTOUT"). SIU_SRCR[SER]
for descriptions of
Freescale Semiconductor
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