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Field
29
Loss-of-clock flag
LOCF
This bit provides the interrupt request flag for the loss-of-clock. To clear the flag, software must write a 1
to the bit. Writing 0 has no effect. This flag bit is sticky in the sense that if clocks return to normal, the bit
will remain set until cleared by either writing 1 or asserting reset. The LOCF flag is not asserted while the
FMPLL is in bypass mode. See
modes and conditions can this flag be asserted.
0 No loss of clock detected. Interrupt service not requested.
1 Loss of clock detected. Interrupt service requested.
30–31
Reserved, should be cleared.
17.4.2.3
Enhanced Synthesizer Control Register 1 (ESYNCR1)
Offset 0x0008
0
1
R
CLKCFG
W
Reset
0
0
16
17
R
0
0
W
Reset
0
0
1
Reset value determined by the PLLREF pin.
Figure 17-4. Enhanced Synthesizer Control Register 1 (ESYNCR1)
Freescale Semiconductor
Table 17-7. SYNSR field descriptions (continued)
Section 17.5.4, Loss-of-clock
2
3
4
5
6
0
0
0
1
1
–
0
0
0
18
19
20
21
22
0
0
0
0
0
0
0
0
0
0
MPC5644A Microcontroller Reference Manual, Rev. 6
Frequency-modulated phase locked loop (FMPLL)
Description
detection, for information on which operating
7
8
9
10
11
0
0
0
0
0
0
0
0
0
0
23
24
25
26
27
0
0
0
0
0
1
0
Access: User read/write
12
13
14
15
EPREDIV
1
1
1
1
28
29
30
31
EMFD
0
0
0
0
569
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