Table of Contents
Advertisement
24.4.2
System configuration registers
24.4.2.1
ETPU_MCR – eTPU Module Configuration Register
This register is global to both eTPU engines, and resides in the Shared BIU. ETPU_MCR gathers global
configuration and status in the eTPU system, including Global Exception. It is also used for configuring
the SCM (Shared Code Memory) operation and test.
Offset: eTPU_BASE + 0x0000
0
1
R
0
W GEC
Reset
0
0
16
17
R
0
0
W
Reset
0
0
= Unimplemented or Reserved
Field
0
GEC—Global Exception Clear
This write-only bit negates Global Exception request and clears Global Exception status bits MGE1,
MGE2, ILF1, ILF2 and SCMMISF.
1: Negate Global Exception, clear status bits MGE1, MGE2, ILF1, ILF2 and SCMMISF
0: Keep Global Exception request and status bits MGE1, MGE2, ILF1, ILF2 and SCMMISF as is.
GEC works the same way in Module Disable Mode.
Freescale Semiconductor
2
3
4
5
6
MGE
MGE
ILF1 ILF2
1
2
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
0
0
Figure 24-3. ETPU_MCR Register
Table 24-5. ETPU_MCR field description
MPC5644A Microcontroller Reference Manual, Rev. 6
Enhanced Time Processing Unit (eTPU2)
7
8
9
10
11
0
0
0
0
0
0
23
24
25
26
27
0
0
VIS
0
0
0
0
0
0
0
Description
Access: User read/write
12
13
14
15
SCMSIZE
SCMSIZE
28
29
30
31
0
0
0
0
0
0
0
767
Advertisement
Table of Contents
