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The arbitration phase is where bus ownership is requested and granted. This phase is not needed in Single
Master Mode because the EBI is the permanent bus owner in this mode.
The address transfer phase specifies the address for the transaction and the transfer attributes that describe
the transaction. The signals related to the address transfer phase are TS, ADDR (or DATA if Address/Data
multiplexing is used), CS[0:3], RD_WR, and BDIP. The address and its related signals (with the exception
of TS, BDIP) are driven on the bus with the assertion of the TS signal, and kept valid until the bus master
receives TA asserted (the EBI holds them one cycle beyond TA for writes and external TA accesses). Note
that for writes with internal TA, RD_WR is not held one cycle past TA.
The data transfer phase performs the transfer of data, from master to slave (in write cycles) or from slave
to master (on read cycles), if any is to be transferred. The data phase may transfer a single beat of data (1-4
bytes) for non-burst operations or a 2-beat (special DBM=1 case only), 4-beat, 8-beat, or 16-beat burst of
data (2 or 4 bytes per beat depending on port Size) when burst is enabled. On a write cycle, the master must
not drive write data until after the address transfer phase is complete. This is to avoid electrical contentions
when switching between drivers. The master must start driving write data one cycle after the address
transfer cycle. The master can stop driving the data bus as soon as it samples the TA line asserted on the
rising edge of CLKOUT. To facilitate asynchronous write support, the EBI keeps driving valid write data
on the data bus until 1 clock after the rising edge where RD_WR and WE are negated (for chip-select
accesses only). See
Figure 14-14
data bus contents as valid on the rising edge of the CLKOUT in which the TA signal is sampled asserted.
See
Figure 14-10
for an example of read timing.
The termination phase is where the cycle is terminated by the assertion of either TA (normal termination)
or TEA (termination with error). Termination is discussed in detail in
protocol.
In the timing diagrams in this document, asynchronous relationships
between signals that switch in the same CLKOUT cycle are not guaranteed.
For example, in
CLKOUT cycle. There is no guarantee that DATA will be stable before WE
assertion. External devices should not be latching write DATA on WE
assertion, but instead must use a signal edge that takes place in a later
CLKOUT cycle, such as WE negation.
14.5.2.4
Single beat transfer
The flow and timing diagrams in this section assume that the EBI is configured in Single Master Mode.
Therefore, arbitration is not needed and is not shown in these diagrams.
14.5.2.4.1
Single beat read flow
The handshakes for a single beat read cycle are illustrated in the following flow and timing diagrams.
Freescale Semiconductor
for an example of write timing. On a read cycle, the master accepts the
NOTE
Figure
14-14, WE and write DATA change during the same
MPC5644A Microcontroller Reference Manual, Rev. 6
External Bus Interface (EBI)
Section 14.5.2.8, Termination signals
301
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