NXP Semiconductors PCA9665 Product Data Sheet
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NXP Semiconductors PCA9665 Product Data Sheet

Fm+ parallel bus to i2c-bus controller
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1. General description

2. Features

PCA9665
Fm+ parallel bus to I
Rev. 02 — 7 December 2006
The PCA9665 serves as an interface between most standard parallel-bus
microcontrollers/microprocessors and the serial I
system to communicate bidirectionally with the I
master or a slave and can be a transmitter or receiver. Communication with the I
carried out on a Byte or Buffered mode using interrupt or polled handshake. The
PCA9665 controls all the I
no external timing element required.
The PCA9665 has the same footprint as the PCA9564 with additional features:
•
1 MHz transmission speeds
•
Up to 25 mA drive capability on SCL/SDA
•
68-byte buffer
•
2
I
C-bus General Call
•
Software reset on the parallel bus
I
2
Parallel-bus to I
C-bus protocol converter and interface
I
Both master and slave functions
I
Multi-master capability
I
Internal oscillator trimmed to 15 % accuracy reduces external components
I
1 Mbit/s and up to 25 mA SCL/SDA I
I
2
I
C-bus General Call capability
I
Software reset on parallel bus
I
68-byte data buffer
I
Operating supply voltage: 2.3 V to 3.6 V
I
5 V tolerant I/Os
I
Standard-mode and Fast-mode I
I
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
I
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I
Packages offered: DIP20, SO20, TSSOP20, HVQFN20
2
C-bus controller
2
C-bus specific sequences, protocol, arbitration and timing with
(Fast-mode Plus (Fm+)) capability
OL
2
C-bus capable and compatible with SMBus
Product data sheet
2
C-bus and allows the parallel bus
2
C-bus. The PCA9665 can operate as a
2
C-bus is

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Summary of Contents for NXP Semiconductors PCA9665

  • Page 1: General Description

    Byte or Buffered mode using interrupt or polled handshake. The PCA9665 controls all the I no external timing element required. The PCA9665 has the same footprint as the PCA9564 with additional features: • 1 MHz transmission speeds •...

  • Page 2: Product Data Sheet

    NXP Semiconductors 3. Applications Add I Add additional I Converts 8 bits of parallel data to serial data stream to prevent having to run a large number of traces across the entire printed-circuit board 4. Ordering information Table 1. Ordering information...

  • Page 3: Product Data Sheet

    FILTER SDA CONTROL AA ENSIO STA STO SI FILTER SCL CONTROL ENSIO STA STO SI CLOCK SELECTOR OSCILLATOR Fig 1. Block diagram of PCA9665 PCA9665_2 Product data sheet data BUS BUFFER 68-BYTE I2CDAT – data register – read/write BUFFER –...

  • Page 4: Product Data Sheet

    NXP Semiconductors 6. Pinning information 6.1 Pinning i.c. Fig 2. Pin configuration of SO20 Fig 4. Pin configuration of DIP20 PCA9665_2 Product data sheet RESET PCA9665D 002aab020 RESET PCA9665N i.c. 002aab019 Rev. 02 — 7 December 2006 PCA9665 Fm+ parallel bus to I...

  • Page 5: Pca9665_2

    NXP Semiconductors 6.2 Pin description Table 2. Symbol Pin i.c. RESET HVQFN package die supply ground is connected to both the V pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the PCB in the thermal pad region.

  • Page 6: Product Data Sheet

    7.2 Internal oscillator The PCA9665 contains an internal 28.5 MHz oscillator which is used for all I The oscillator requires up to 550 s to start-up after ENSIO bit is set to ‘1’.

  • Page 7: Product Data Sheet

    NXP Semiconductors Table 4. Register name I2CCOUNT I2CADR I2CSCLL I2CSCLH I2CTO I2CPRESET I2CMODE Fig 6. Register mapping flowchart PCA9665_2 Product data sheet Indirect register selection by setting A1 = 1 and A0 = 0 Register function byte count own address...

  • Page 8: Product Data Sheet

    SD7 bit position and the Read/Write bit in the SD0 bit position. The CPU can read from and write to this 8-bit register while the PCA9665 is not in the process of shifting a byte. This occurs when PCA9665 is in a defined state and the serial interrupt flag is set.

  • Page 9: Product Data Sheet

    NXP Semiconductors In Byte mode, the CPU can read or write a single byte at a time. In Buffered mode, the CPU can read or write up to 68 bytes at a time. See more detail. Remark: The I2CDAT register will capture the serial address as data when addressed via the serial bus.

  • Page 10: Reset

    HIGH level. In state C8h, the AA flag can be set again for future address recognition. When the PCA9665 is in the not addressed slave mode, its own slave address is ignored. Consequently, no acknowledge is returned, and a serial interrupt is not requested.

  • Page 11: The Indirect Data Field Access Register, Indirect (A1 = 1, A0 = 0)

    If the STA and STO bits are both set, then a STOP condition is transmitted on the C-bus, if the PCA9665 is in a master mode. the bus controller then transmits a START condition after the minimum buffer time (t STO = 0 : When the STO bit is reset, no STOP condition will be generated.

  • Page 12: Indirect Registers

    Last Byte control bit. Master/Slave Buffered Receiver mode only. LB = 1: PCA9665 does not acknowledge the last received byte. LB = 0: PCA9665 acknowledges the last received byte. A future bus transaction must complete the read sequence by not acknowledging the last byte.

  • Page 13: The Clock Rate Registers, I2Cscll And I2Csclh (Indirect Addresses 02H And 03H)

    7.3.2.3 The Clock Rate registers, I2CSCLL and I2CSCLH (indirect addresses 02h and 03h) I2CSCLL and I2CSCLH are 8-bit read/write registers. They define the data rate for the PCA9665 when used as a bus master. The actual frequency is determined by t where SCL is HIGH), t...

  • Page 14: The Time-Out Register, I2Cto (Indirect Address 04H)

    I2CPRESET is an 8-bit write-only register. Programming the I2CPRESET register allows the user to reset the PCA9665 under software control. The software reset is achieved by writing two consecutive bytes to this register. The first byte must be A5h while the second byte must be 5Ah.

  • Page 15: The I C-Bus Mode Register, I2Cmode (Indirect Address 06H)

    NXP Semiconductors 7.3.2.6 The I C-bus mode register, I2CMODE (indirect address 06h) I2CMODE is an 8-bit read/write register. It contains the control bits that select the correct timing parameters when the device is used in master mode (AC[1:0]). Timing parameters involved with AC[1:0] are t Table 23.

  • Page 16: Pca9665 Modes

    I2CSTA register is updated. This allows the microcontroller to request a sequence, up to 68 bytes in a single transmission and lets the PCA9665 perform it without having to access the Status Register and the Control Register each time a single command is performed.

  • Page 17: Byte Mode

    Symbol Value ENSIO must be set to logic 1 to enable the PCA9665. If the AA bit is reset, the PCA9665 will not acknowledge its own slave address in the event of another device becoming master of the bus. (In other words, if AA is reset, PCA9665 cannot enter a slave mode.) STA, STO, and SI must be reset.
  • Page 18 AA = 1) • D8h if the PCA9665 lost the arbitration and is addressed as a slave receiver during a General Call sequence (slave mode enabled with AA = 1 and General Call address enabled with GC = 1 in I2CADR register)
  • Page 19 NXP Semiconductors successful transmission to a Slave Receiver next transfer started with a repeated START condition Not Acknowledge received after the slave address Not Acknowledge received after a data byte arbitration lost in slave address or data byte arbitration lost and addressed as slave...
  • Page 20 I2CDAT action no I2CDAT action 1 Rev. 02 — 7 December 2006 PCA9665 Fm+ parallel bus to I Next action taken by the PCA9665 AA MODE SLA+W will be transmitted; ACK/NACK will be received SLA+W will be transmitted; ACK/NACK will be received SLA+R will be transmitted;...
  • Page 21 No I2CDAT action Rev. 02 — 7 December 2006 PCA9665 Fm+ parallel bus to I Next action taken by the PCA9665 AA MODE Data byte will be transmitted; ACK/NACK will be received Repeated START will be transmitted; STOP condition will be transmitted;...

  • Page 22: Master Receiver Byte Mode

    AA = 1) • D8h if the PCA9665 lost the arbitration and is addressed as a slave receiver during a General Call sequence (slave mode enabled with AA = 1 and General Call address enabled with GC = 1 in I2CADR register).
  • Page 23 NXP Semiconductors successful reception from a Slave Transmitter next transfer started with a repeated START condition Not Acknowledge received after the slave address arbitration lost in slave address or Acknowledge bit arbitration lost and addressed as slave from master to slave...
  • Page 24 Rev. 02 — 7 December 2006 PCA9665 Fm+ parallel bus to I C-bus controller Next action taken by the PCA9665 AA MODE SLA+R will be transmitted; ACK/NACK bit will be received SLA+R will be transmitted; ACK/NACK bit will be received SLA+W will be transmitted;...

  • Page 25: Slave Receiver Byte Mode

    Value The upper 7 bits are the I by a master. GC is the control bit that allows the PCA9665 to respond or not to the General Call address (00h). When programmed to logic 1, the PCA9665 will acknowledge the General Call address.
  • Page 26 NXP Semiconductors reception of own slave address and one or more data bytes; all are Acknowledged. last data byte received is Not Acknowledged arbitration lost as MST and addressed as slave reception of the General Call address and one or more...
  • Page 27 NXP Semiconductors Table 31. Slave Receiver Byte mode (MODE = 0) Status Status of the code C-bus and the (I2CSTA) PCA9665 Own SLA+W has been received; ACK has been returned Arbitration lost in SLA+R/W as master; Own SLA+W has been...
  • Page 28 NXP Semiconductors Table 31. Slave Receiver Byte mode (MODE = 0) Status Status of the code C-bus and the (I2CSTA) PCA9665 Previously addressed with General Call; Data has been received; ACK has been returned Previously addressed with General Call; Data has been received;...

  • Page 29: Slave Transmitter Byte Mode

    (2) Defined state when a single byte is transmitted and an ACK is received. (3) Defined state when a single byte is transmitted and a NACK is received. (4) Defined state when a single byte is transmitted and the PCA9665 goes to the non-addressed mode (AA = 0) and an ACK is received.
  • Page 30 I2CDAT action Rev. 02 — 7 December 2006 PCA9665 Fm+ parallel bus to I Next action taken by PCA9665 Last data byte will be transmitted and ACK/NACK bit will be received Data byte will be transmitted; ACK/NACK will be received...

  • Page 31: Buffered Mode

    Symbol Value ENSIO must be set to logic 1 to enable the PCA9665. If the AA bit is reset, the PCA9665 will not acknowledge its own slave address in the event of another device becoming master of the bus (in other words, if AA is reset, the PCA9665 cannot enter a slave mode).
  • Page 32 AA = 1). • D8h if the PCA9665 lost the arbitration and is addressed as a slave receiver during a General Call sequence (slave mode enabled with AA = 1 and General Call address enabled with GC = 1 in I2CADR register).
  • Page 33 NXP Semiconductors successful transmission to a Slave Receiver next transfer started with a repeated START condition Not Acknowledge received after the slave address Not Acknowledge received after a data byte arbitration lost in slave address or data byte arbitration lost and addressed as slave...
  • Page 34 ACK has been received for each of them or until a NACK bit is received. SLA+R will be transmitted. PCA9665 will be switched to Master Receiver Buffered mode. Up to BC[6:0] data bytes will be transmitted (until...
  • Page 35 STO flag will be reset. STOP condition followed by a START condition will be transmitted. STO flag will be reset. C-bus will be released; PCA9665 will enter the not addressed slave mode. C-bus will be released; PCA9665 will enter the slave mode.

  • Page 36: Master Receiver Buffered Mode

    1 if the last received byte needs to be not acknowledged (read operation ends so the PCA9665 can issue a STOP or Re-START condition). A write to I2CCON resets the SI bit, clears the Interrupt (INT goes HIGH) and allows the serial transfer to continue.
  • Page 37 NXP Semiconductors successful reception from a Slave Transmitter next transfer started with a repeated START condition Not Acknowledge received after the slave address arbitration lost in slave address or Acknowledge bit arbitration lost and addressed as slave from master to slave...
  • Page 38 Total number of bytes to be transmitted (= SLA+W + number of data bytes) Next action taken by the PCA9665 SLA+R will be transmitted. If ACK bit received, BC[6:0] data bytes will be received, ACK bit will be returned for all of them.
  • Page 39 Total number of bytes to be received Total number of bytes to be received Next action taken by the PCA9665 BC[6:0] data bytes will be received, ACK bit will be returned for all of them BC[6:0] data bytes will be received, ACK bit...

  • Page 40: Slave Receiver Buffered Mode

    Value The upper 7 bits are the I by a master. GC is the control bit that allows the PCA9665 to respond or not to the General Call address (00h). When programmed to logic 1, the PCA9665 will acknowledge the General Call address.
  • Page 41 NXP Semiconductors If the LB bit is reset (logic 0), the PCA9665 will return an acknowledge for all the bytes that will be received. The maximum number of bytes that are received in a single sequence is defined by BC[6:0] in I2CCOUNT register as shown in If the LB bit is set (logic 1) during a transfer, the PCA9665 will return a not acknowledge (logic 1) on SDA after receiving the last byte.
  • Page 42 Total number of bytes to be received Next action taken by the PCA9665 Up to BC[6:0] data bytes will be received, ACK bit will be returned for all of them. Up to BC[6:0] data bytes will be received, ACK bit...
  • Page 43 Total number of bytes to be received Next action taken by the PCA9665 Up to BC[6:0] data bytes will be received, ACK bit will be returned for all of them. Up to BC[6:0] data bytes will be received, ACK bit...
  • Page 44 To I2CCON LB BC[6:0] STA STO SI AA MODE Next action taken by the PCA9665 Switched to not addressed slave mode; No recognition of own slave address; General Call address will be recognized if GC = 1 Switched to not addressed slave mode;...

  • Page 45: Slave Transmitter Buffered Mode

    I2CCOUNT register. (4) Defined state after the last byte has been transmitted and the PCA9665 goes to the non-addressed mode (AA = 0) and an ACK is received. The number of bytes that are transmitted is equal to the value in I2CCOUNT register.
  • Page 46 Total number of data bytes to be transmitted Total number of data bytes to be transmitted Next action taken by the PCA9665 Up to BC[6:0] bytes will be transmitted. PCA9665 switches to the not addressed mode after BC[6:0] bytes have been transmitted.
  • Page 47 To I2CCON LB BC[6:0] STA STO SI AA MODE Next action taken by the PCA9665 Switched to not addressed slave mode; No recognition of own slave address; General Call address recognized if GC = 1. Switched to slave mode; Own slave address will be recognized;...

  • Page 48: Buffered Mode Examples

    2. Load the data bytes in I2CDAT buffer. The different bytes to be sent will be stored in the PCA9665 buffer. There is no protection against writing over a buffer’s boundary. If more than 68 bytes are written to the buffer, the data at address 00h will be overwritten.

  • Page 49: Buffered Slave Transmitter Mode

    3. Load the data bytes in I2CDAT buffer. The different bytes to be sent will be stored in the PCA9665 buffer. There is no protection against writing over a buffer’s boundary. If more than 68 bytes are written to the buffer, the data at address 00h will be overwritten.

  • Page 50: Buffered Slave Receiver Mode

    I2CCON register to send the data to the I when sequence has been executed) can be performed as long as the master acknowledges the bytes sent by the PCA9665 and AA = 1. Slave Transmitter Buffered mode ends when the I PCA9665 goes to Non-addressed Slave mode.

  • Page 51: I2Ccount Register

    NXP Semiconductors – the SCL line is held LOW by the PCA9665 after the 2 bytes have been sent – the PCA9665 sends an Interrupt, sets SI = 1 and updates I2CSTA register – I2CSTA reads 28h 5. Program I2CCOUNT = 40h (64 bytes to read and Last byte acknowledged).
  • Page 52 Slave Receiver Buffered mode (regular slave mode and General Call response After Slave Address + W and ACK bit returned for slave address (both in regular mode and when PCA9665 loses arbitration and is addressed as slave) After receiving ‘n’ bytes, ACK bit returned for the ‘n’ bytes After receiving ‘n’...

  • Page 53: Acknowledge Management

    Buffered modes Data acknowledge/not acknowledge management can be controlled on a byte basis (Byte mode) or on a sequence basis (Buffered mode). The PCA9665 can be programmed to respond (ACK) or not (NACK) to two different I is performed based on the different control bits (AA, GC, LB and MODE) and the different modes.
  • Page 54 NXP Semiconductors Table 44. Unbuffered Mode (MODE = 0) Control bits AA = 0 Master Transmitter mode • address/data are transmitted on a byte basis Slave Transmitter mode • NACK returned after own slave address received • switch to not addressed slave mode any time...
  • Page 55 NXP Semiconductors Table 45. Buffered Mode (MODE = 1) Control bits AA = 0 Master Transmitter mode • address/data are transmitted on a multiple byte basis = BC[6:0] value Slave Transmitter mode • NACK returned after own slave address received •...
  • Page 56 NXP Semiconductors Table 45. Buffered Mode (MODE = 1) Control bits AA = 1 Master Transmitter mode • address/data are transmitted on a multiple byte basis = BC[6:0] value Slave Transmitter mode • ACK returned after own slave address received •...

  • Page 57: Miscellaneous States

    STOP condition 8.8.1 I2CSTA = F8h This status code indicates that the PCA9665 is in an idle state and that no relevant information is available because the serial interrupt flag, SI, is not yet set. This occurs on a STOP condition or during a hardware or software reset event and when the PCA9665 is not involved in a serial transfer.

  • Page 58: I2Csta = 78H

    This status code indicates that the SCL line is stuck LOW. 8.9 Some special cases The PCA9665 has facilities to handle the following special cases that may occur during a serial transfer. 8.9.1 Simultaneous repeated START conditions from two masters A repeated START condition may be generated in the Master Transmitter or Master Receiver modes.

  • Page 59: I 2 C-Bus Obstructed By A Low Level On Scl Or Sda

    PCA9665, state 08h is entered and the serial transfer continues. If the SDA line is not released by the slave pulling it LOW, then the PCA9665 concludes that there is a bus error, loads 70h in I2CSTA, generates an interrupt signal, and releases the SCL and SDA lines.

  • Page 60: Bus Error

    The PCA9665 only reacts to a bus error when it is involved in a serial transfer either as a master or an addressed slave. When a bus error is detected, PCA9665 releases the SDA and SCL lines, sets the interrupt flag, and loads the status register with 00h.

  • Page 61: Reset

    NXP Semiconductors 8.11 Reset Reset of the PCA9665 to its default state can be performed in 2 different ways: • By holding the RESET pin LOW for a minimum of t • By using the Parallel Software Reset sequence as described in...
  • Page 62 Fig 21. Bus timing diagram; Unbuffered Slave Transmitter mode 7-bit address R/W = 0 START condition from slave PCA9665 Slave PCA9665 is written to by external master transmitter. (1) As defined in I2CADR register. Fig 22. Bus timing diagram; Unbuffered Slave Receiver mode PCA9665_2 Product data sheet interrupt...

  • Page 63: I C-Bus Timing Diagrams, Buffered Mode

    Master PCA9665 writes data to slave transmitter. (1) 7-bit address + R/W = 0 byte and number of bytes sent = value programmed in I2CCOUNT register (BC[6:0] Fig 23. Bus timing diagram; Buffered Master Transmitter mode...
  • Page 64 START condition from slave PCA9665 Slave PCA9665 is written to by external master transmitter. (1) As defined in I2CADR register. (2) Number of bytes received = value programmed in I2CCOUNT register (BC[6:0] Fig 26. Bus timing diagram; Buffered Slave Receiver mode...

  • Page 65: Characteristics Of The I C-Bus

    NXP Semiconductors 9. Characteristics of the I The I C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device.

  • Page 66: Acknowledge

    NXP Semiconductors MASTER TRANSMITTER/ RECEIVER Fig 30. System configuration 9.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit.

  • Page 67: Application Design-In Information

    I not have an integrated I C-bus port. The PCA9665 can also be used to add more I devices, provide a higher frequency, lower voltage migration path for the PCF8584 and convert 8 bits of parallel data to a serial bus to avoid running multiple traces across the printed-circuit board.

  • Page 68: Add Additional I C-Bus Ports

    NXP Semiconductors Fig 33. Adding I 10.3 Add additional I The PCA9665 can be used to convert 8-bit parallel data into additional multiple master capable I microprocessor, custom ASIC, DSP, etc., already have an I more additional I components that cannot be located on the same bus (e.g., 100 kHz and 400 kHz slaves on different buses so that each bus can operate at its maximum potential).

  • Page 69: Limiting Values

    NXP Semiconductors 11. Limiting values Table 47. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter supply voltage input voltage input current output current total power dissipation P/out power dissipation per output storage temperature ambient temperature 5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present.

  • Page 70: Static Characteristics

    NXP Semiconductors 12. Static characteristics Table 48. Static characteristics = 2.3 V to 3.6 V; T = 40 C to +85 C; unless otherwise specified. Symbol Parameter Supply supply voltage supply current power-on reset voltage Inputs WR, RD, A0, A1, CE, RESET...

  • Page 71: Dynamic Characteristics

    NXP Semiconductors 13. Dynamic characteristics Table 49. Dynamic characteristics (3.3 volt) = 3.3 V 0.3 V; T = 40 C to +85 C; unless otherwise specified. (See Symbol Parameter Initialization timing power-on initialization time init(po) Serial interface initialization timing serial interface initialization time...
  • Page 72 NXP Semiconductors Table 50. Dynamic characteristics (2.5 volt) = 2.5 V 0.2 V; T = 40 C to +85 C; unless otherwise specified. (See Symbol Parameter Initialization timing power-on initialization time init(po) Serial interface initialization timing serial interface initialization time...
  • Page 73 NXP Semiconductors START RESET 50 % rec(rst) Fig 36. Reset timing D7 to D0 Fig 37. Interrupt timing PCA9665_2 Product data sheet 30 % as(int) Rev. 02 — 7 December 2006 PCA9665 Fm+ parallel bus to I C-bus controller ACK or read cycle...
  • Page 74 NXP Semiconductors A0 to A1 D0 to D7 (read) Fig 38. Bus timing (read cycle) A0 to A1 D0 to D7 (write) Fig 39. Parallel bus timing (write cycle) PCA9665_2 Product data sheet su(A) h(A) su(CE_N) w(RDL) d(DV) float not valid...
  • Page 75 NXP Semiconductors Fig 40. Data timing PCA9665_2 Product data sheet RD, CE input d(QLZ) Dn output LOW-to-float float-to-LOW d(QHZ) Dn output HIGH-to-float float-to-HIGH outputs enabled = 1.5 V + 0.3 V 0.3 V and V are typical output voltage drops that occur with the output load.
  • Page 76 NXP Semiconductors Table 51. C-bus frequency and timing specifications All the timing limits are valid within the operating supply voltage and ambient temperature range; V 3.3 V 0.3 V; T = 40 C to +85 C; and refer to V...
  • Page 77 NXP Semiconductors HD;STA Fig 41. Definition of timing on the I START protocol condition SU;STA HD;STA Rise and fall times refer to V Fig 42. I C-bus timing diagram PCA9665_2 Product data sheet SU;DAT SU;STA HIGH HD;DAT C-bus bit 7...

  • Page 78: Test Information

    NXP Semiconductors 14. Test information Fig 43. Test circuitry for switching times Table 52. Test d(DV) d(QZ) Fig 44. Test circuitry for open-drain switching times Table 53. Test d(DV) d(QZ) as(int) das(int) PCA9665_2 Product data sheet PULSE GENERATOR Test data are given in Table = load resistance.

  • Page 79: Package Outline

    NXP Semiconductors 15. Package outline DIP20: plastic dual in-line package; 20 leads (300 mil) pin 1 index DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT max. min. max. 0.51 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
  • Page 80 NXP Semiconductors SO20: plastic small outline package; 20 leads; body width 7.5 mm pin 1 index DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT max. 2.45 2.65 0.25 2.25 0.012 0.096 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
  • Page 81 NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm pin 1 index DIMENSIONS (mm are the original dimensions) UNIT max. 0.15 0.95 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
  • Page 82 NXP Semiconductors HVQFN20: plastic thermal enhanced very thin quad flat package; no leads; 20 terminals; body 5 x 5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) UNIT max. 0.05 0.38 0.00...

  • Page 83: Handling Information

    NXP Semiconductors 16. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe you must take normal precautions appropriate to handling integrated circuits. 17. Soldering 17.1 Introduction There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch...
  • Page 84 NXP Semiconductors packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 54 Table 54. Package thickness (mm) < 2.5 Table 55. Package thickness (mm) <...

  • Page 85: Wave Soldering

    NXP Semiconductors 17.3.2 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
  • Page 86 NXP Semiconductors Table 56. Suitability of IC packages for wave, reflow and dipping soldering methods Mounting Package Surface mount BGA, HTSSON..T LFBGA, SQFP, SSOP..T VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC...

  • Page 87: Abbreviations

    NXP Semiconductors 18. Abbreviations Table 57. Acronym ASIC C-bus SMBus 19. Revision history Table 58. Revision history Document ID Release date PCA9665_2 20061207 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors.
  • Page 88 NXP Semiconductors Table 58. Revision history …continued Document ID Release date • Modifications: Table 49, sub-section “Bus timing”: (continued) – changed Min value for t – changed Min value for t – changed Min value for t – changed Min value for t –...

  • Page 89: Legal Information

    For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

  • Page 90: Table Of Contents

    (indirect address 06h) ....15 PCA9665 modes......16 Configuration modes.
  • Page 91 NXP Semiconductors Static characteristics....70 Dynamic characteristics ....71 Test information .

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