NXP Semiconductors MPC5644A Reference Manual page 158

Enhanced Direct Memory Access Controller (eDMA)
Offset: EDMA_BASE + 0X001C
R
W
Reset
Figure 8-12. eDMA Clear Interrupt Request (EDMA_CIRQR)
Field
NOP No operation
0 Normal operation
1 No operation, ignore bits 1–7.
CINT[0:6]
Clear Interrupt Request
0–32 (64 for eDMA) Clear corresponding bit in EDMA_IRQRH or EDMA_IRQRL.
64–127
8.3.2.10 eDMA Clear Error Register (EDMA_CER)
The EDMA_CER provides a memory-mapped mechanism to clear a given bit in the EDMA_ERH or
EDMA_ERL to disable the error condition flag for a given channel. The given value on a register write
causes the corresponding bit in the EDMA_ERH or EDMA_ERL to be cleared. Setting bit 1 (CERR[0])
provides a global clear function, forcing the entire contents of the EDMA_ERH or EDMA_ERL to be
zeroed, clearing all channel error indicators. Reads of this register return all zeroes.
If bit 0 is set, the CERR command is ignored. This allows multiple byte registers to be written as a 32-bit
word. Reads of this register return all zeroes.
Offset: EDMA_BASE + 0x001D
R
W
Reset
Field
NOP No operation
0 Normal operation
1 No operation, ignore bits 1–7.
CERR[0:6] Clear Error Indicator
0–32 (64 for eDMA) Clear corresponding bit in EDMA_ERH or EDMA_ERL.
64–127
158
0 1 2
NOP
0 0 0
Table 8-11. EDMA_CIRQR field descriptions
Clear all bits in EDMA_IRQRH or EDMA_IRQRL.
0 1 2
NOP
0 0 0
Figure 8-13. eDMA Clear Error Register (EDMA_CER)
Table 8-12. EDMA_CER field descriptions
Clear all bits in EDMA_ERH or EDMA_ERL.
MPC5644A Microcontroller Reference Manual, Rev. 6
Access: User write-only
3 4 5
CINT[0:6]
0 0 0
Description
Access: User write-only
3 4 5
CERR[0:6]
0 0 0
Description
6 7
0 0
6 7
0 0
Freescale Semiconductor