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Enhanced Time Processing Unit (eTPU2)
24.4.2.5
ETPU_ECR – eTPU Engine Configuration Register
Each engine has its own ETPU_ECR. ETPU_ECR holds configuration and status fields that are
programmed independently in each engine.
Offset: eTPU_A: eTPU_Base + 0x014; eTPU_B: eTPU_Base + 0x018
0
1
R FEN
MDIS
D
W
1
Reset
0
0/1
16
17
R
CDFC
W
Reset
0
0
= Unimplemented or Reserved
1
The MDIS reset value is MCU-dependent. Please consult the Reference Manual of the specific MCU.
2
Engine may go to Debug state (halted) soon after reset, depending on the NDEDI configuration.
Field
0
FEND—Force End
FEND assertion terminates any current running thread as if an END instruction have been executed (see
Section 24.5.9.4.1, Ending current thread –
1: Ends any ongoing thread.
0: Normal operation.
This bit is self-negating when the thread ends. Writing FEND = 1 is ignored and FEND stays 0 when the
microengine is in TST, halted, stopped, or idle (no thread executing).
Note: Only on rare occasions (e.g., during a long stall, see
can be read as 1, because it negates as soon as the end begins execution.
776
2
3
4
5
6
0
STF
0
0
0
0
0
0
0
0
18
19
20
21
22
0
ERBA
0
0
0
0
0
Figure 451. ETPU_ECR Register
Table 24-9. ETPU_ECR field description
END).
MPC5644A Microcontroller Reference Manual, Rev. 6
7
8
9
10
11
0
HLTF
0
0
0
2
0
0(1
)
0
0
0
23
24
25
26
27
SPP
0
0
DIS
0
0
0
0
0
Description
Section 24.5.10.2.10, Microengine
Access: User read/write
12
13
14
15
FCS
FPSCK
S
0
0
0
0
28
29
30
31
ETB
0
0
0
0
stall) FEND
Freescale Semiconductor
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