Table of Contents
Advertisement
System Timer Module (STM)
Address offset
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
0x0028
0x002C
0x0030
0x0034
0x0038
0x003C
0x0040
0x0044
0x0048
0x004C – 0x3FFF Reserved
19.4.2
Register descriptions
The following sections detail the individual registers within the STM programming model.
608
Table 19-1. STM memory map
Register description
STM Control Register(STM_CR)
STM Count Register(STM_CNT)
Reserved
Reserved
STM Channel 0 Control Register(STM_CCR0)
STM Channel 0 Interrupt Register(STM_CIR0)
STM Channel 0 Compare Register(STM_CMP0)
Reserved
STM Channel 1 Control Register(STM_CCR1)
STM Channel 1 Interrupt Register(STM_CIR1)
STM Channel 1 Compare Register(STM_CMP1)
Reserved
STM Channel 2 Control Register(STM_CCR2)
STM Channel 2 Interrupt Register(STM_CIR2)
STM Channel 2 Compare Register(STM_CMP2)
Reserved
STM Channel 3 Control Register(STM_CCR3)
STM Channel 3 Interrupt Register(STM_CIR3)
STM Channel 3 Compare Register(STM_CMP3)
MPC5644A Microcontroller Reference Manual, Rev. 6
Size (bits) Access
Location
32
R/W
on page
19-609
32
R/W
on page
19-609
—
—
—
—
—
—
32
R/W
on page
19-610
32
R/W
on page
19-610
32
R/W
on page
19-611
—
—
—
32
R/W
on page
19-610
32
R/W
on page
19-610
32
R/W
on page
19-611
—
—
—
32
R/W
on page
19-610
32
R/W
on page
19-610
32
R/W
on page
19-611
—
—
—
32
R/W
on page
19-610
32
R/W
on page
19-610
32
R/W
on page
19-611
—
—
—
Freescale Semiconductor
Advertisement
Table of Contents
