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non-correctable error is not reported by the master. Examples include speculative instruction fetches
which are discarded due to a change-of-flow operation, and buffered operand writes. The ECC reporting
logic in the ECSM provides an optional error interrupt mechanism to signal all non-correctable memory
errors. In addition to the interrupt generation, the ECSM captures specific information (memory address,
attributes and data, bus master number, etc.) which can be useful for subsequent failure analysis.
Register address: ECSM Base + 0x0043 (0xFFF4_0043)
0
R
0
W
Reset
0
Name
2
Enable RAM 1-bit Reporting
ER1BR
0 = Reporting of single-bit platform RAM corrections is disabled.
1 = Reporting of single-bit platform RAM corrections is enabled.
The occurrence of a single-bit RAM correction generates an ECSM ECC interrupt request as signalled
by the assertion of ECSM_ESR[R1BC]. The address, attributes and data are also captured in the
ECSM_REAR, ECSM_PRESR, ECSM_REMR, ECSM_REAT and ECSM_REDR registers.
3
Enable Flash 1-bit Reporting
EF1BR
0 = Reporting of single-bit platform flash corrections is disabled.
1 = Reporting of single-bit platform flash corrections is enabled.
The occurrence of a single-bit flash correction generates an ECSM ECC interrupt request as signalled
by the assertion of ECSM_ESR[F1BC]. The address, attributes and data are also captured in the
ECSM_FEAR, ECSM_FEMR, ECSM_FEAT and ECSM_FEDR registers.
6
Enable RAM Non-Correctable Reporting
ERNCR
0 = Reporting of non-correctable platform RAM errors is disabled.
1 = Reporting of non-correctable platform RAM errors is enabled.
The occurrence of a non-correctable multi-bit RAM error generates an ECSM ECC interrupt request as
signalled by the assertion of ECSM_ESR[RNCE]. The faulting address, attributes and data are also
captured in the ECSM_REAR, ECSM_PRESR, ECSM_REMR, ECSM_REAT and ECSM_REDR
registers.
7
Enable Flash Non-Correctable Reporting
EFNCR
0 = Reporting of non-correctable platform flash errors is disabled.
1 = Reporting of non-correctable platform flash errors is enabled.
The occurrence of a non-correctable multi-bit flash error generates an ECSM ECC interrupt request as
signalled by the assertion of ECSM_ESR[FNCE]. The faulting address, attributes and data are also
captured in the ECSM_FEAR, ECSM_FEMR, ECSM_FEAT and ECSM_FEDR registers.
Freescale Semiconductor
1
2
0
ER1BR
0
0
= Unimplemented
Figure 18-4. ECC Configuration Register (ECSM_ECR)
Table 18-6. ECSM_ECR field description
MPC5644A Microcontroller Reference Manual, Rev. 6
3
4
5
0
0
EF1BR
0
0
0
Description
Error Correction Status Module (ECSM)
6
7
ERNCR
EFNCR
0
0
589
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