NXP Semiconductors MPC5644A Reference Manual page 654

Configurable Enhanced Modular IO Subsystem (eMIOS200)
Table 22-7. EMIOS_CADR[n], EMIOS_CBDR[n], and EMIOS_ALTA[n] values assignment (continued)
1
SAIC
1
SAOC
IPWM
IPM
DAOC
1
MCB
OPWFMB
OPWMB
1
In this mode, the register EMIOS_CBDR[n] is not used but B2 can be accessed.
22.4.3.3 eMIOS200 Channel Counter Register (EMIOS_CCNTR[n])
Offset: UC[n] base address + 0x0008
0 1
R 0 0
W
Reset 0 0
16 17 18
R
W
Reset 0 0
1
In GPIO mode or freeze action, this register is writable.
Figure 22-8. eMIOS200 Channel Counter Register (EMIOS_CCNTR[n])
The EMIOS_CCNTR[n] contains the value of the internal counter for eMIOS channel n. When GPIO
mode is selected or the channel is frozen the EMIOS_CCNTR[n] is read/write. For all other modes, the
EMIOS_CCNTR[n] is a read-only register. When entering some operation modes, this register is
automatically cleared (refer to
Depending on its configuration, a channel may have an internal counter or not. If at least one mode that
requires the counter is implemented, the counter is present, otherwise it is not.
654
— A2
A2 A1
— A2
— A2
A2 A1
A2 A1
A2 A1
A2 A1
2 3 4 5 6
0 0 0 0 0
0 0 0 0 0
19 20 21 22
0 0 0 0 0
Section 22.5.1.1, Channel modes of
MPC5644A Microcontroller Reference Manual, Rev. 6
B2 B2
B2 B2
— B1
— B1
B2 B1
B2 B2
B2 B1
B2 B1
7 8 9 10 11
0 C[0:23]
0 0 0 0 0
23 24 25 26 27
C[0:23]
0 0 0 0 0
operation, for details).
— —
— —
— —
— —
— —
— —
— —
— —
Access: User read/write
12 13 14 15
0 0 0 0
28 29 30 31
0 0 0 0
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