Dma Request Assignments - NXP Semiconductors MPC5644A Reference Manual

group-priority error and channel-priority error, or EDMA_ESR[GPE] and EDMA_ESR[CPE],
respectively.
For all error types other than group- or channel-priority errors, the channel number causing the error is
recorded in the EDMA_ESR. If the error source is not removed before the next activation of the problem
channel, the error is detected and recorded again.
Channel-priority errors are identified within a group after that group has been selected as the active group.
For example, all of the channel priorities in group 1 are unique, but some of the channel priorities in group
0 are the same:
1. The DMA is configured for fixed-group and fixed-channel arbitration modes.
2. Group 1 is the highest priority and all channels are unique in that group.
3. Group 0 is the next highest priority and has two channels with the same priority level.
4. If group 1 has any service requests, those requests are executed.
5. After all of group 1 requests have completed, group 0 becomes the next active group.
6. If group 0 has a service request, then an undefined channel in group 0 is selected and a
channel-priority error will occur.
7. This repeats until the all of group 0 requests have been removed or a higher priority group 1 request
comes in.
In this sequence, for item 2, the DMA acknowledge lines assert only if the selected channel is requesting
service via the DMA peripheral request signal. If interrupts are enabled for all channels, the user receives
an error interrupt, but the channel number for the EDMA_ER and the error interrupt request line are
undetermined because they reflect the undefined channel. A group-priority error is global and any request
in any group causes a group-priority error.
If priority levels are not unique, the highest (channel/group) priority that has an active request is selected,
but the lowest numbered (channel/group) with that priority is selected by arbitration and executed by the
DMA engine. The hardware service request handshake signals, error interrupts, and error reporting are
associated with the selected channel.
8.5.3

DMA request assignments

The assignments between the DMA requests from the modules to the channels of the eDMA are shown in
Table 8-22. The source column is written in C language syntax. The syntax is
module_instance.register[bit].
DMA request
eQADC_FISR0_CFFF0
eQADC_FISR0_RFDF0
eQADC_FISR1_CFFF1
eQADC_FISR1_RFDF1
Freescale Semiconductor
Table 8-22. DMA request summary for eDMA
Channe
Source
l
0 EQADC.FISR0[CFFF0]
1 EQADC.FISR0[RFDF0]
2 EQADC.FISR1[CFFF1]
3 EQADC.FISR1[RFDF1]
MPC5644A Microcontroller Reference Manual, Rev. 6
Enhanced Direct Memory Access Controller (eDMA)
Description
eQADC Command FIFO 0 Fill Flag
eQADC Receive FIFO 0 Drain Flag
eQADC Command FIFO 1 Fill Flag
eQADC Receive FIFO 1 Drain Flag
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