Table of Contents
Advertisement
19.4.2.1
STM Control Register (STM_CR)
The STM Control Register (STM_CR) includes the prescale value, freeze control and timer enable bits.
Offset 0x000
0
1
R
0
0
W
Reset
0
0
16
17
18
R
W
Reset
0
0
Field
CPS
Counter Prescaler
Selects the clock divide value for the prescaler (1 – 256)
0x00 = Divide system clock by 1
0x01 = Divide system clock by 2
...
0xFF = Divide system clock by 256
FRZ
Freeze
Allows the timer counter to be stopped when the device enters debug mode
0 = STM counter continues to run in debug mode.
1 = STM counter is stopped in debug mode.
TEN
Timer Counter Enabled
0 = Counter is disabled
1 = Counter is enabled
19.4.2.2
STM Count Register (STM_CNT)
The STM Count Register (STM_CNT) holds the timer count value.
Offset 0x004
0
1
2
3
4
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Freescale Semiconductor
2
3
4
5
6
0
0
0
0
0
0
0
0
0
0
19
20
21
22
CPS
0
0
0
0
0
Figure 19-1. STM Control Register (STM_CR)
Table 19-2. STM_CR field description
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Figure 19-2. STM Count Register (STM_CNT)
MPC5644A Microcontroller Reference Manual, Rev. 6
7
8
9
10
11
0
0
0
0
0
0
0
0
0
0
23
24
25
26
27
0
0
0
0
0
0
0
0
0
Description
CNT
System Timer Module (STM)
Access: Read/Write
12
13
14
15
0
0
0
0
0
0
0
0
28
29
30
31
0
0
FRZ TEN
0
0
0
0
Access: Read/Write
609
Advertisement
Table of Contents
