Overview - NXP Semiconductors MPC5644A Reference Manual

Frequency-modulated phase locked loop (FMPLL)
17.2.1

Overview

The frequency modulated phase locked loop (FMPLL) allows the user to generate high speed system
clocks from a crystal oscillator or from an external clock generator. Furthermore, the FMPLL supports
programmable frequency modulation of the system clock. The FMPLL multiplication factor, reference
clock predivider factor, output clock divider ratio, modulation depth and multiplication rate are all
controllable through programmable registers.
Figure 17-1 shows the block diagram of the FMPLL.
EXTAL
XTAL
OSC
XTAL
PLLREF
RC
OSC
17.2.2 Features
The FMPLL has the following features:
• Reference clock predivider for finer frequency synthesis resolution
• Reduced frequency divider for reducing the FMPLL output clock frequency without forcing the
FMPLL to relock
• Input clock frequency range from 4 MHz to 20 or 40 MHz
to 16 MHz after the predivider
• Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz
• VCO free-running frequency range from 25 MHz to 125 MHz
• 4 bypass modes: crystal or external reference with PLL on or off
• 2 normal modes: crystal or external reference
• Programmable frequency modulation
— Triangle wave modulation
— Register programmable modulation frequency and depth
1. See Section 17.1, Information specific to this
560
PLL
Predivider
Phase
PREDIV
Detector
PREDIV RFD MFD Lock
Control/Status Registers
Reference FMPLL
Failure Failure
Clock Quality Monitor
Figure 17-1. FMPLL block diagram
device, for information on crystal frequencies supported.
MPC5644A Microcontroller Reference Manual, Rev. 6
Charge
Pump
Out Divider
VCO
Low Pass
RFD
Filter
Divider
MFD
FM
Controller
1
before the predivider, and from 4 MHz
Freescale Semiconductor