Table of Contents
Advertisement
Resets
4.5.1
Power-on reset (POR)
The internal power-on reset signal is asserted when either the supply voltages, nominally 3.3 V or 1.2 V
or the RESET supply (VDDEH6a) fall below defined values. See the device data sheet for the threshold
specifications of these voltages. The output signals from the power-on reset circuits are active low signals.
All power-on reset output signals are combined into one POR signal at the 1.2 V level and input to the reset
controller. Although assertion of the power-on reset signal causes reset, the RESET pin must be asserted
during a power-on reset to guarantee proper operation of the MCU.
The PLLREF pin determines the source of reference clock, either crystal or external, at the negation of
RSTOUT. During the assertion of RSTOUT, the system clock will switch to the input specified by the
PLLREF pin. The value on the PLLREF pin must be kept constant during reset to avoid transients in the
system clock. See
Section 17.2.3, Modes of
The signal on the WKPCFG pin determines whether weak pull up or pull down devices are enabled after
reset on the eTPU and eMIOS pins. The WKPCFG pin is applied on the assertion of the internal reset
signal (assertion of RSTOUT). See
information.
Once a power-on-reset is triggered, if the clock reference is the crystal (PLLREF = 1), then the clock to
the whole chip, including the reset state machine, is kept frozen until the Clock Quality Monitor detects
that the crystal oscillator has already stabilized. If the clock reference is external (PLLREF = 0) the clock
is released to the system immediately. When the clock is stable and released to the chip, the reset controller
counts a predetermined number of clock cycles (refer to
RSTOUT pin. The WKPCFG and BOOTCFG[0:1] pins are sampled four clock cycles before the negation
of RSTOUT, and the associated bits/fields are updated in the SIU_RSR. In addition, SIU_RSR[PORS] and
SIU_RSR[ERS] are set, and all other reset status bits are cleared in the SIU_RSR.
4.5.2
External reset
When the reset controller detects assertion of the RESET pin, the internal reset signal and RSTOUT pin
are asserted. The values on the WKPCFG pin and PLLCFG pins are applied at the assertion of the internal
reset signal (assertion of RSTOUT). Once the RESET pin is negated and the FMPLL Loss of Lock reset
request signal is negated, the reset controller waits for a predetermined number of clock cycles (refer to
Section 4.3.2,
RSTOUT). Once the clock count finishes, the reset configuration pins are latched. The reset
controller then waits four clock cycles before negating RSTOUT, and the associated bits/fields are updated
in the SIU_RSR. In addition, SIU_RSR[ERS] is set, and all other reset status bits in the SIU_RSR are
cleared.
4.5.3
Loss of lock
A Loss of Lock Reset occurs when the FMPLL loses lock and the Loss of Lock Reset Enable (LOLRE)
bit in the FMPLL Synthesizer Control Register (SYNCR) is set. The internal reset signal and RSTOUT
pin are asserted. The value on the WKPCFG pin is applied at the assertion of the internal reset signal
(assertion of RSTOUT), as is the PLLREF value. Once the FMPLL Loss of Lock reset request signal is
negated, the reset controller waits for a predetermined number of clock cycles (refer to
RSTOUT). Once the clock count finishes, the WKPCFG and BOOTCFG[0:1] pins are sampled. The reset
98
operation, for more details.
Section 4.7.3, Reset weak pull up/down
MPC5644A Microcontroller Reference Manual, Rev. 6
configuration, for more
Section 4.3.2,
RSTOUT) before negating the
Section 4.3.2,
Freescale Semiconductor
Advertisement
Table of Contents
