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14.5.1.4
Burst Support (wrapped only)
The EBI supports burst read accesses of external burstable memory. To enable bursts to a particular
memory region, clear the BI (Burst Inhibit) bit in the appropriate Base Register. External burst lengths of
4 and 8 words are supported. Burst length is configured for each chip select by using the BL bit in the
appropriate Base Register. See
In 16-bit data bus mode (DBM=1 in EBI_MCR), a special 2-beat burst case is supported for reads and
writes for 32-bit non-chip-select accesses only. This is to allow 32-bit coherent accesses to another MCU.
See
Section 14.5.2.9, Non-chip-select burst in 16-bit data bus
Bursting of accesses that are not controlled by the chip selects is not supported for any other case besides
the special case of 32-bit accesses in 16-bit data bus mode.
Burst writes are not supported for any other case besides the special case of 32-bit non-chip-select writes
in 16-bit data bus mode. Internal requests to write >32 bits (such as a cache line) externally are broken up
into separate 32-bit or 16-bit external transactions according to the port size. See
accesses (Small port size and short burst length)
14.5.1.5
Bus Monitor
When enabled (via the BME bit in the EBI_BMCR), the bus monitor detects when no TA assertion is
received within a maximum timeout period for external TA accesses. The timeout for the bus monitor is
specified by the BMT field in the EBI_BMCR. Each time a timeout error occurs, the BMTF bit is set in
the EBI_TESR. The timeout period is measured in external bus (CLKOUT) cycles. Thus the effective
real-time period is multiplied (by 2, 3, etc.) when a slower-speed mode is used, even though the BMT field
itself is unchanged.
14.5.1.6
Port Size Configuration per Chip Select (16 or 32 bits)
The EBI supports memories with data widths of 16 or 32 bits. The port size for a particular chip select is
configured by writing the PS bit in the corresponding Base Register.
14.5.1.7
Configurable Wait States
From 0 to 15 wait states can be programmed for any cycle that the memory controller generates, via the
SCY bits in the appropriate Option Register. From 0 to 3 wait states between burst beats can be
programmed using the BSCY bits in the appropriate Option Register.
14.5.1.8
Configurable internal or external TA per chip select
Each chip select can be configured (via the SETA bit) to have TA driven internally (by the EBI), or
externally (by an external device). See
EBI_CAL_BR0-3)" for more details on SETA bit usage.
Freescale Semiconductor
Section 14.5.2.5, Burst transfer
for more detail on these cases.
Section 14.4.1.4, EBI Base Registers (EBI_BR0-EBI_BR3,
MPC5644A Microcontroller Reference Manual, Rev. 6
External Bus Interface (EBI)
for more details on burst operation.
mode.
Section 14.5.2.6, Small
297
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