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System Integration Unit (SIU)
16.6.12 External IRQ Falling-Edge Event Enable Register (SIU_IFEER)
The External IRQ Falling-Edge Event Enable Register allows falling edge triggered events to be enabled
on the corresponding IRQx inputs. Rising and falling edge events can be enabled by setting the
corresponding bits in both the SIU_IREER and SIU_IFEER.
SIU_BASE + 0x2C
0
1
R
0
W
Reset
0
0
16
17
R
W
Reset
0
0
= Unimplemented or Reserved
1
This bit is cleared only by a reset.
Figure 16-12. External IRQ Falling-Edge Event Enable Register (SIU_IFEER)
Field
NMIFE
NMI Falling-Edge Event Enable (NMI Input)
This write once bit enables falling-edge triggered events on the NMI input. This bit is cleared only by a
reset.
1: Falling edge event is enabled
0: Falling edge event is disabled
NMIFE0
NMI Falling-Edge Event Enable (SWT)
This write once bit enables falling-edge triggered events by SWT. This bit is cleared only by a reset.
1: Falling edge event is enabled
0: Falling edge event is disabled
IFEEx
IRQ Falling-Edge Event Enable x
This bit enables falling-edge triggered events on the corresponding IRQx input.
1: Falling edge event is enabled
0: Falling edge event is disabled
16.6.13 External IRQ Digital Filter Register (SIU_IDFR)
The External IRQ Digital Filter Register specifies the amount of digital filtering on the IRQ0 – IRQ15
inputs. The Digital Filter Length field specifies the number of system clocks that define the period of the
digital filter.
398
2
3
4
5
6
0
0
0
0
0
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
Table 16-16. SIU_IFEER field description
MPC5644A Microcontroller Reference Manual, Rev. 6
7
8
9
10
11
0
0
0
0
0
0
0
0
0
23
24
25
26
27
0
0
0
0
0
Description
12
13
14
15
0
0
0
0
0
0
0
0
28
29
30
31
0
0
0
0
Freescale Semiconductor
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