NXP Semiconductors PN7150 Hardware Design Manual
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NXP Semiconductors PN7150 Hardware Design Manual

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AN11756
PN7150 Hardware Design Guide
Rev. 1.2 — 15 January 2018
347612
Document information
Info
Content
Keywords
PN7150, Hardware Design, Power modes, Chip interfaces
Abstract
This document is intended to provide an overview on how to integrate the
NFC Controller PN7150 from hardware perspective.
It presents the different hardware design options offered by the IC and
provides guidelines on how to select the most appropriate ones for a
given implementation.
In particular, this document highlights the different chip power states and
how to operate them in order to minimize the average NFC-related power
consumption.
Application note
COMPANY PUBLIC

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Summary of Contents for NXP Semiconductors PN7150

  • Page 1 Document information Info Content Keywords PN7150, Hardware Design, Power modes, Chip interfaces Abstract This document is intended to provide an overview on how to integrate the NFC Controller PN7150 from hardware perspective. It presents the different hardware design options offered by the IC and provides guidelines on how to select the most appropriate ones for a given implementation.
  • Page 2 AN11756 NXP Semiconductors PN7150 Hardware Design Guide Revision history Date Description 20180115 Adding information related to WLCSP42 package Editorial changes 20160523 Security status changed into “COMPANY PUBLIC” 20151204 First official version of the document Contact information For additional information, please visit: http://www.nxp.com...

  • Page 3: Introduction

    Detailed chip features set can be found in the PN7150 Product Datasheet [1]. This application note is intended to give an overview of the way the PN7150 must be integrated into a hardware platform. It presents in particular the different hardware design options offered by the PN7150 and it provides guidelines on how to select the most appropriate ones for a given implementation.

  • Page 4: Fig 1. Interfaces Summary

    PN7150 Hardware Design Guide 2. Interfaces The purpose of this chapter is to give an overview of the PN7150 interfaces and to show how the chip is interconnected to the external world. PN7150 external connections are shown in Fig 1.
  • Page 5 AN11756 NXP Semiconductors PN7150 Hardware Design Guide Table 1. Interface summary Interface Short description Options Host interface Link with host controller • I²C address configuration • IRQ or polling • Reset control Clock interface Input clock required when • Input clock characteristics generating RF field •...

  • Page 6: Fig 2. Typical Application Schematic In Hvqfn Package

    PN7150 Hardware Design Guide 3. Typical application schematics The purpose of this chapter is to propose an application schematic for PN7150. The below depicted configuration is based on the following implementation choices: a. The use of a crystal as input clock source (see 5.1) b.

  • Page 7: Host Interface

    I2CADR0 and I2CADR1 pins: b' 0 1 0 1 0 I2CADR1 I2CADR0’ where I2CADR0 and I2CADR1 are the least significant bits. For instance, if both I2CADR0 and I2CADR1 are tied to ground, the 7-bits slave address of the PN7150 is “0x28” (gives 0x50 as 8-bits write address).

  • Page 8: Frames Reading Synchronization

     2- IRQ pin polling  3- Read polling For 1-, connect pin IRQ of the PN7150 to an external interrupt line on the host controller side. In this case, when the PN7150 has some data available, the IRQ line will be asserted and if configured accordingly, a software interrupt is generated on the host controller side.
  • Page 9 NXP Semiconductors PN7150 Hardware Design Guide For VEN lower than 0.4V the PN7150 is in hard power down state and the chip’s internal core is no more supplied. The chip is reset when VEN is switched back to a voltage level higher than 1.1V.

  • Page 10: Fig 4. Crystal Based Clock Configuration

    PN7150 User Manual [2]. 5.1 Use of crystal oscillator A 27.12MHz crystal can be used as input clock for PN7150. For instance, when there is no clock on the system complying with the PN7150 input clock specification. When using a crystal, frequency accuracy and drive level must be carefully selected according to the specification provided in the PN7150 Product Datasheet [1].

  • Page 11: Fig 5. Clock Request Through Clk_Req Pin

    When an external system clock is used, the input clock frequency must be one of the following values: 13MHz, 19.2MHz, 24MHz, 26MHz, 38.4MHz or 52MHz Please note that the voltage level of the system clock signal provided to PN7150 must be 1.8V.

  • Page 12: Fig 6. External System Clock Configuration

    PN7150 Hardware Design Guide Warning: XTAL1 pin is referenced to VDD(PAD) supply. Therefore VDD(PAD) must always be supplied to the PN7150 when a valid input clock signal is required (i.e. to generate an RF field) The dedicated clock request pin (CLK_REQ) can be optionally connected to a clock buffer.

  • Page 13: Fig 7. Power Application Schematic

    6. Power interface 6.1 Power Management Unit The PN7150 supports to be directly connected to a battery power supply. It can operate with a wide voltage input range from 5.5V down to 2.75V. Detailed current consumption versus the different power mode and min/typical/max voltage information can be found in the PN7150 Product Datasheet [1].

  • Page 14: Fig 8. Typical Reading Distance Vs Tvdd Using Om5578 Board

    PN7150 Hardware Design Guide 6.4 TVDD supply options The strength of the field emitted by the PN7150 is linked to several parameters such as the antenna geometrical characteristics, the antenna matching circuit and the voltage level on TX output buffer.

  • Page 15: Fig 9. Configuration 1: Vbat Used To Generate Tvdd

    AN11756 NXP Semiconductors PN7150 Hardware Design Guide Fig 9. Configuration 1: VBAT used to generate TVDD TVDD value shall be chosen according the minimum targeted VBAT value for which reader mode shall work. Fig 10. Configuration 1: TVDD offset behavior For example, if chosen TVDD is 3.6V and current to be delivered by the TxLDO is Itx, it...

  • Page 16: Fig 11. Configuration 2: External 5V Used To Generate Tvdd

    AN11756 NXP Semiconductors PN7150 Hardware Design Guide 6.4.2 Config 2: external 5V used to generate TVDD In this case the TXLDO can provide a TVDD of 3V/3.3V/3.6V/4.5V or 4.75V. Fig 11. Configuration 2: external 5V used to generate TVDD Fig 12. Configuration 2: TVDD offset behavior Depending on the wanted behaviour of the external 5V in card mode, 2 different programming are available.

  • Page 17: Fig 13. Battery Discharge Curve

    1 - Use the internal TXLDO to filter the 5V power supply PN7150 can operate at fixed RF field strength in Poll mode with a continuous battery voltage down to: a. 3.1V when TVDD is set to 2.7V b. 3.5V when TVDD is set to 3.1V The figure below shows 2 typical battery discharge cycles.

  • Page 18: Fig 14. Typical Antenna Matching Circuit

    R must not be placed) How to select or design a proper antenna for the PN7150 and how to calculate the value of the matching components is explained in a dedicated application note. Please refer to the PN7150 Antenna Design and Matching Guide [4].

  • Page 19: Fig 15. Optimized Matching Circuit

    Proof point: Once the customer has measured its NFC antenna within its final environment he should calculate the resulting quality factor as explained in the PN7150 Antenna Design Guide [4]. If the quality factor is below or equal to 35, R resistors can be safely removed.

  • Page 20: Rx Path

    See circle 2 in above Fig 15. 7.2.3 Rx path In case a small antenna is connected to the PN7150, the peak to peak voltage generated at antenna ends will be limited. Then this offers the possibility to simplify the RF path circuitry by removing the...

  • Page 21: Fig 16. Power Modes

    • Full Power • Standby A simplified figure is depicted below to provide an overview of the different PN7150 power modes, with VEN and VBAT as input parameters. The complete diagram including VDD(PAD) is given in PN7150 Product Datasheet [1].

  • Page 22: Layout Guidelines

    Please take care of the rules provided by your supplier for the optimal placement. During the matching process this might not be directly seen as an impedance analyzer typically delivers some few mW of power. During operation, the PN7150 can introduce far more AN11756 All information provided in this document is subject to legal disclaimers.

  • Page 23: Fig 17. Recommended Emc Inductances Placement

    Fig 17. Recommended EMC Inductances Placement PN7150 EMC inductors have been verified with several references as given below. Other references might be suitable, but only the ones below have been properly checked by NXP.

  • Page 24: Fig 18. Rf Paths Floorplan

    NXP Semiconductors PN7150 Hardware Design Guide Fig 18. RF paths floorplan The PN7150 reference design layout depicted below can be used as an example of proper antenna components routing. Fig 19. Antenna matching layout example Please note that you shall take care of having multiple vias to connect different ground layers to avoid too resistive bottleneck, especially on the TX path grounding.

  • Page 25: Fig 20. Xtal Connection Example

    9.3 XTAL layout recommendations The XTAL must be connected as close as possible to the CLK1 and CLK2 pins from the PN7150 to achieve the best performances as possible. Please follow these guidelines for the layout of the XTAL connections:...
  • Page 26 • How to optimize the NFC controller power consumption when the host controller is shutdown or enters stand-by mode? The PN7150 can be configured to enter standby mode when there is no activity from the host controller side after a programmable timeout (see configuration details in the PN7150 User Manual [2]).

  • Page 27: References

    11. References PN7150 Product Datasheet UM10936 – PN7150 User Manual I²C Bus Specification AN11755 – PN7150 Antenna Design and Matching Guide AN11756 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.

  • Page 28: Abbreviations

    AN11756 NXP Semiconductors PN7150 Hardware Design Guide 12. Abbreviations Abbr. Meaning Application Note Bill of material Clock EEPROM Electrically Erasable Programmable Read Only Memory Ground GPIO General Purpose Input Output Hardware I²C Inter-Integrated Circuit (serial data bus) Integrated Circuit Input / Output...

  • Page 29: Legal Information

    NXP Semiconductors and its suppliers accept no liability for Purchase of an NXP Semiconductors IC that complies with one of the Near inclusion and/or use of NXP Semiconductors products in such equipment or Field Communication (NFC) standards ISO/IEC 18092 and ISO/IEC 21481 applications and therefore such inclusion and/or use is at the customer’s own...

  • Page 30: Table Of Contents

    AN11756 NXP Semiconductors PN7150 Hardware Design Guide 14. List of figures Fig 1. Interfaces summary .......... 4 Fig 2. Typical Application Schematic in HVQFN package ............6 Fig 3. Typical Application Schematic in WLCSP package ............6 Fig 4. Crystal based clock configuration ....10 Fig 5.

  • Page 31: List Of Tables

    AN11756 NXP Semiconductors PN7150 Hardware Design Guide 15. List of tables Table 1. Interface summary ..........5 Table 2. Host interface pinning ........7 Table 3. I²C slave 8-bits address ........7 Table 4. Decoupling capacitors need ......13 Table 5.

  • Page 32: Contents

    AN11756 NXP Semiconductors PN7150 Hardware Design Guide 16. Contents Introduction ............3 List of figures ............. 30 Interfaces ............. 4 List of tables ............31 Typical application schematics ......6 Contents ............. 32 Host interface ............7 Host interface pinning ........7 Host interface pin characteristics .......

Table of Contents