NXP Semiconductors MPC5644A Reference Manual page 795

Offset: eTPU_A: eTPU_Base + 0x220; eTPU_B: eTPU_Base + 0x224
0 1
R CIOS CIOS
31 30
W CIOC CIOC
31 30
Reset 0 0
16 17
R CIOS CIOS
15 14
W CIOC CIOC
15 14
Reset 0 0
= Unimplemented or Reserved
Field
0-31 CIOSx—Channel x Interrupt Overflow Status
1: indicates that interrupt overflow occurred in the channel.
0: indicates that no interrupt overflow occurred in the channel.
0-31 CIOCx—Channel x Interrupt Overflow Clear
1: clear status bit.
0: keep status bit unaltered.
For details about interrupt overflow, see
Freescale Semiconductor
2 3 4 5 6
CIOS CIOS CIOS CIOS CIOS
29 28 27 26 25
CIOC CIO CIO CIO CIO
29 C C C C
28 27 26 25
0 0 0 0 0
18 19 20 21 22
CIOS CIOS CIOS CIOS CIOS
13 12 11 10 9
CIOC CIO CIO CIO CIO
13 C C C C
12 11 10 9
0 0 0 0 0
Figure 24-15. ETPU_CIOSR Register
Table 24-25. ETPU_CIOSR field description
Section 24.5.2.2.2, Interrupt and data transfer request
MPC5644A Microcontroller Reference Manual, Rev. 6
Enhanced Time Processing Unit (eTPU2)
7 8 9 10 11
CIOS CIOS CIOS CIOS CIOS
24 23 22 21 20
CIO CIOC CIOC CIO CIO
C 23 22 C C
24 21 20
0 0 0 0 0
23 24 25 26 27
CIOS CIOS CIOS CIOS CIOS
8 7 6 5 4
CIO CIOC CIOC CIO CIO
C 7 6 C C
8 5 4
0 0 0 0 0
Description
Access: User read/write
12 13 14 15
CIOS CIOS CIOS CIOS
19 18 17 16
CIO CIO CIO CIO
C C C C
19 18 17 16
0 0 0 0
28 29 30 31
CIOS CIOS CIOS CIOS
3 2 1 0
CIO CIO CIO CIO
C C C C
3 2 1 0
0 0 0 0
overflow.
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