Xbar Register Descriptions - NXP Semiconductors MPC5644A Reference Manual

Multi-Layer AHB Crossbar Switch (XBAR)
Address
XBAR_Base (0xFFF0_4000)
XBAR_Base + 0x004 –
XBAR_Base + 0x00F
XBAR_Base + 0x010
XBAR_Base + 0x014 –
XBAR_Base + 0x0FF
XBAR_Base + 0x100
XBAR_Base + 0x104 –
XBAR_Base + 0x10F
XBAR_Base + 0x110
XBAR_Base + 0x114 –
XBAR_Base + 0X1FF
XBAR_Base + 0x200
XBAR_Base + 0x204 –
XBAR_Base + 0x20F
XBAR_Base + 0x210
XBAR_Base + 0x214 –
XBAR_Base + 0X6FF
XBAR_Base + 0x700
XBAR_Base + 0x704 –
XBAR_Base + 0X70F
XBAR_Base + 0x710
XBAR_Base + 0x714 –
XBAR_Base + 0XF03
9.2.2

XBAR register descriptions

The following paragraphs provide detailed descriptions of the various XBAR registers.
Refer to Figure 9-2 for the various bit configurations that appear in the register maps.
Always 1 Always
reads 1 reads 0
1
"BIT" refers to a field name in the register. Some fields span multiple bits.
196
Table 9-2. XBAR Register Configuration Summary
MPR0 — Master Priority Register for Slave port 0
Reserved
SGPCR0 — General Purpose Control Register for
Reserved
MPR1 — Master Priority Register for Slave port 1
Reserved
SGPCR1 — General Purpose Control Register for
Reserved
MPR2 — Master Priority Register for Slave port 2
Reserved
SGPCR2 — General Purpose Control Register for
Reserved
MPR7 — Master Priority Register for Slave port 7
Reserved
SGPCR7 — General Purpose Control Register for
Reserved
1
0 R/W BIT Read- BIT
bit only bit
Figure 9-2. Key to Register Fields
MPC5644A Microcontroller Reference Manual, Rev. 6
Register
Slave port 0
Slave port 1
Slave port 2
Slave port 7
1
Write- Write 1 BIT
only bit to clear
1
BIT w1c
Location
on page
9-197
—
on page
9-199
—
on page
9-197
—
on page
9-199
—
on page
9-197
—
on page
9-199
—
on page
9-197
—
on page
9-199
—
1
Self-clear 0 N/A
bit
1
BIT
Freescale Semiconductor