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NXP Semiconductors MC9S12ZVH64 Reference Manual

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MC9S12ZVH-Family

Reference Manual

S12 MagniV

Microcontrollers

MC9S12ZVHRMV1

Rev. 1.05

03/2015

freescale.com

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Summary of Contents for NXP Semiconductors MC9S12ZVH64

Page 1 MC9S12ZVH-Family Reference Manual S12 MagniV Microcontrollers MC9S12ZVHRMV1 Rev. 1.05 03/2015 freescale.com...
Page 2 To provide the most up-t o -date information, the online revision of ou r documents is the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: freescale.com The following revision history table summarizes changes. This document contains information for all constituent modules, with the exception of the S12Z CPU.
Page 3: Table Of Contents
Chapter 1 Device Overview MC9S12ZVH-Family Introduction ..............19 Features .
Page 4 1.10.3 Low Power Modes ............56 1.11 Security .
Page 5 Chapter 3 Memory Mapping Control (S12ZMMCV1) Introduction ..............111 3.1.1 Glossary .
Page 6 5.1.2 Features ............. 138 5.1.3 Modes of Operation .
Page 7 6.5.1 Avoiding Unintended Breakpoint Re-triggering ......223 6.5.2 Debugging Through Reset ..........223 6.5.3 Breakpoints from other S12Z sources .
Page 8 7.7.1 General Initialization Information ......... 289 7.7.2 Application information for COP and API usage .
Page 9 Resets ..............347 Interrupts .
Page 10 11.2 External Signal Description ........... . . 420 11.2.1 RXCAN —...
Page 11 Chapter 13 Inter-Integrated Circuit (IICV3) Block Description 13.1 Introduction ..............497 13.1.1 Features .
Page 12 Chapter 15 Serial Communication Interface (S12SCIV6) 15.1 Introduction ..............549 15.1.1 Glossary .
Page 13 16.4.1 Modes of Operation ........... . 601 16.4.2 PWM Duty Cycle .
Page 14 18.4.2 RTC Control Register 2 (RTCCTL2) ........644 18.4.3 RTC Control Register 3 (RTCCTL3) .
Page 15 20.1.1 Features ............. 677 20.2 Memory Map and Register Definition .
Page 16 22.1.2 Modes of Operation ........... . 744 22.1.3 Block Diagram .
Page 17 A.1.1 Pins ..............774 A.1.2 Current Injection .
Page 18 Appendix I VREG Electrical Specifications Appendix J S12CANPHY Electrical Specifications Maximum Ratings ............. 811 Static Electrical Characteristics.
Page 19: Introduction
Chapter 1 Device Overview MC9S12ZVH-Family Table 1-1. Revision History Version Revision Description of Changes Number Date May 2011 • initial Draft Nov 2011 • add the 100LQFP VSSC Dec 2011 • update base on review feedback • update the pin names for ADC/CAN/IIC/CANPHY/SPI/SSG with index number Feb 2012 •...
Page 20: Features
Table 1-2 provides a summary of feature set differences within the MC9S12ZVH-Family. All other features are common to all MC9S12ZVH-Family members. MC9S12ZVH-Family features Table 1-2. Feature MC9S12ZVH128 MC9S12ZVH64 HCS12Z HCS12Z Flash memory (ECC) 128 KB 64 KB EEPROM (ECC) 4 KB...
Page 21: Maskset 0N65E And 1N65E Device Compare
Chapter 1 Device Overview MC9S12ZVH-Family Feature MC9S12ZVH128 MC9S12ZVH64 Frequency modulated PLL Internal 1 MHz RC oscillator 1 (with independent Autonomous window watchdog 1 (with independent clock source) clock source) Direct Battery Voltage sense pin Vsup sense Chip temperature sensor 1 General sensor 1 General sensor 5.5 V –...
Page 22: Maskset 2N65E And 1N65E/0N65E Device Compare
Chapter 1 Device Overview MC9S12ZVH-Family NOTE User should take care when switch from 0N65E to 1N65E device Table 1-3. Device Difference for 0N65E and 1N65E 0N65E 1N65E CPMU FTMRZ CANPHY BDC fast clock source to CORE clock BDC fast clock source to Bus clock ADC reference voltage to IFR Maskset 2N65E and 1N65E/0N65E device compare on 2N65E, the CANPHY is update in order to pass conformance test.
Page 23: Module Features
Chapter 1 Device Overview MC9S12ZVH-Family • One Pulse Width Modulation (PWM) modules with up to 8 x 8-bit channels • Simple Sound Generation (SSG) for monotonic tone generation • One Inter-Integrated Circuit (IIC) module • One Serial Peripheral Interface (SPI) module •...
Page 24: Embedded Memory
Chapter 1 Device Overview MC9S12ZVH-Family — Supports in-circuit programming of on-chip nonvolatile memory 1.6.1.2 Debugger (DBG) • Enhanced DBG module including: — Four comparators (A, B, C and D) each configurable to monitor PC addresses or addresses of data accesses —...
Page 25: Clocks, Reset & Power Management Unit (Cpmu)
Chapter 1 Device Overview MC9S12ZVH-Family — Single bit error correction and double bit error detection 1.6.3 Clocks, Reset & Power Management Unit (CPMU) • Real Time Interrupt (RTI) • Clock Monitor, supervising the correct function of the oscillator (CM) • System reset generation •...
Page 26: K External Oscillator
Chapter 1 Device Overview MC9S12ZVH-Family — Low power — Good noise immunity — Eliminates need for external current limiting resistor — Transconductance sized for optimum start-up margin for typical crystals — Oscillator pins shared with GPIO functionality 1.6.5 32K External Oscillator •...
Page 27: Pulse Width Modulation Module (Pwm)
Chapter 1 Device Overview MC9S12ZVH-Family • 16-bit pulse accumulator 1.6.9 Pulse Width Modulation Module (PWM) • 8 channels x 8-bit (4 channels x 16-bit) • Programmable period and duty cycle per channel • Center-aligned or edge-aligned outputs • Programmable clock select logic with a wide range of frequencies 1.6.10 Simple Sound Generator (SSG) •...
Page 28: Can Physical Layer (Canphy) Transceiver
Chapter 1 Device Overview MC9S12ZVH-Family • Blanking (recirculation) state • 16-bit Integration Accumulator register • 16-Bit Modulus Down Counter with interrupt 1.6.14 CAN Physical Layer (CANPHY) transceiver • High speed CAN interface for baud rates of up to 1 Mbit/s •...
Page 29: Serial Communication Interface Module (Sci)
Chapter 1 Device Overview MC9S12ZVH-Family 1.6.17 Serial Communication Interface Module (SCI) • Full-duplex or single-wire operation • Standard mark/space non-return-to-zero (NRZ) format • 13-bit baud rate selection for 0N65E device • 16-bit baud rate selection for 1N65E device • Programmable character length •...
Page 30 Chapter 1 Device Overview MC9S12ZVH-Family — Linear voltage regulator directly supplied by V (protected V — Low-voltage detect with low-voltage interrupt V — Power-On Reset (POR) — Low-Voltage Reset (LVR) — External ballast device support to reduce internal power dissipation —...
Page 31: Block Diagram
Chapter 1 Device Overview MC9S12ZVH-Family Block Diagram Figure 1-1. MC9S12ZVH-Family Block Diagram VDDA/VRH ADC0 64 KB, 128 KB Flash with ECC VSSA/VRL 10-bit 8-channel 4 KB, 8KB RAM with ECC Analog-Digital Converter AN0_[7:0] PAD[7:0] 4 KB EEPROM with ECC VSS2 ECLK VDDF VSS1...
Page 32: Device Memory Map
Chapter 1 Device Overview MC9S12ZVH-Family 1.7.1 Device Memory Map Table 1-4 shows the device register memory map. Table 1-4. Module Register Address Ranges Size Address Module (Bytes) 0x0000-0x0003 ID Registers 0x0004-0x000F Reserved 0x0010-0x001F INT 16 0x0020-0x006F Reserved 0x0070-0x00FF MMC 14 0x0100-0x017F DBG 12 0x0180-0x01FF...
Page 33 Chapter 1 Device Overview MC9S12ZVH-Family Table 1-4. Module Register Address Ranges Size Address Module (Bytes) 0x0788-0x07BF Reserved 0x07C0-0x07C7 IIC0 0x07C8-0x07FF Reserved 0x0800-0x083F CAN0 0x0840-0x098F Reserved 0x0990-0x0997 CANPHY0 0x0998-0x09FF Reserved 0x0A00-0x0A1F 0x0A20-0x0A3F Reserved 0x0A40-0x0A7F 0x0A80-0x0A87 SSD0 0x0A88-0x0A8F Reserved 0x0A90-0x0A97 SSD1 0x0A98-0x0A9F Reserved 0x0AA0-0x0AA7 SSD2...
Page 34 Chapter 1 Device Overview MC9S12ZVH-Family Register Space 0x00_0000 4 KByte 0x00_1000 max. 1 MB - 4 KB 0x10_0000 EEPROM max. 1 MB - 48 KB 0x1F_4000 Reserved 512 Byte 0x1F_8000 Reserved (read only) 6 KB 0x1F_C000 NVM IFR 256 Byte 0x20_0000 Unimplemented 6 MB...
Page 35: Part Id Registers Assignments
ID for each revision of the chip. Table 1-5 shows the assigned Part ID register value. Table 1-5. Assigned IDs Numbers Device Mask Set number Part ID MC9S12ZVH128 0N65E 32’h01170000 MC9S12ZVH64 0N65E 32’h01170000 MC9S12ZVH128 1N65E 32’h01171000 MC9S12ZVH64 1N65E 32’h01171000 MC9S12ZVH128 2N65E 32’h01171100...
Page 36: Detailed Signal Descriptions
Chapter 1 Device Overview MC9S12ZVH-Family Table 1-6. Port Availability by Package Option Port 144 LQFP 100 LQFP Port V PV[7:0] — sum of ports NOTE To avoid current drawn from floating inputs, all non-bonded pins should be configured as output or configured as input with a pull up or pull down device enabled 1.8.2 Detailed Signal Descriptions...
Page 37 Chapter 1 Device Overview MC9S12ZVH-Family 1.8.2.6 PB[3:0] — Port B I/O Signals PB[3:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected and enabled on per signal basis. Out of reset the pull-down devices are enabled. 1.8.2.7 PC[7:0] —...
Page 38 Chapter 1 Device Overview MC9S12ZVH-Family 1.8.2.15 PT[7:0] / KWT[7:0] — Port T I/O signals PT[7:0] are general-purpose input or output signals. The signals can be configured on per signal basis as interrupt inputs with wake-up capability (KWT[7:0]). These signals can have a pull-up or pull-down device selected and enabled on per signal basis.
Page 39 Chapter 1 Device Overview MC9S12ZVH-Family 1.8.2.21 SCI[1:0] Signals 1.8.2.21.1 RXD[1:0] Signals These signals are associated with the receive functionality of the serial communication interfaces (SCI[1:0]). 1.8.2.21.2 TXD[1:0] Signals These signals are associated with the transmit functionality of the serial communication interfaces (SCI[1:0]).
Page 40 Chapter 1 Device Overview MC9S12ZVH-Family 1.8.2.26 RTC Signals 1.8.2.26.1 RTC_CAL Signal The signal can be the RTC output clock CALCLK for external clock calibration or external 1HZ standard clock input for on chip clock calibration. 1.8.2.27 SSG0 Signals 1.8.2.27.1 SGT0 Signals The signal is from SSG0 output, it contain tone or tone mixed with amplitude digital output.
Page 41 Chapter 1 Device Overview MC9S12ZVH-Family 1.8.2.30 SSD[3:0] Signals 1.8.2.30.1 M0COSM, M0COSP, M0SINM and M0SINP Signals These signal are used to measure the back EMF to calibrate the pointer reset position which are associated with SSD[0]. 1.8.2.30.2 M1COSM, M1COSP, M1SINM and M1SINP Signals These signal are used to measure the back EMF to calibrate the pointer reset position which are associated with SSD[1].
Page 42 Chapter 1 Device Overview MC9S12ZVH-Family 32K OSC 32K_XTAL 32K_EXTAL Crystal or Resonator Figure 1-3. 32K OSC Crystal/Resonator Connection 1.8.2.32.3 API_EXTCLK This signal is associated with the output of the API. 1.8.2.32.4 ECLK This signal is associated with the output of the divided bus clock (ECLK). NOTE This feature is only intended for debug purposes at room temperature.
Page 43: Vsense - Voltage Sensor Input
Chapter 1 Device Overview MC9S12ZVH-Family 1.8.2.33.3 PDOCLK — Profiling Data Output Clock This is the PDO clock signal used when the DBG module profiling feature is enabled. This signal is output only. During code profiling this is the clock signal that can be used by external development tools to sample the PDO signal.
Page 44: Bctlc
Chapter 1 Device Overview MC9S12ZVH-Family 1.8.4 BCTLC BCTLC provides the base current of an external bipolar that supplies an external or internal CAN physical interface. 1.8.5 VDDC This is connect to the output voltage of the external bipolar. It is the feed back pin to the MCU also. When VDDC is not used, it must be shorted with VDDX and user must keep the EXTCON in CPMUVREGCTL be enabled.
Page 45: Package And Pinouts
Chapter 1 Device Overview MC9S12ZVH-Family 1.8.7.4 VLCD- Power Supply Reference Pin for LCD driver VLCD is the voltage reference pin for the LCD driver. Adjusting the voltage on this pin will change the display contrast. 1.8.7.5 VDD, VSS2 — Core Power and Ground Pin The VDD voltage supply of nominally 1.8V is generated by the internal voltage regulator.
Page 46 Chapter 1 Device Overview MC9S12ZVH-Family FP26 / PG2 BKGD / MODC FP25 / PG1 PC7 / TXD1 FP24 / PG0 PC6 / RXD1 VLCD PC5 / SGA0 FP23 / PF7 PC4 / SGT0 KWT7 / IOC1_7 / PT7 PT4 / PDO / IOC1_4 / KWT4 PT3 / PDOCLK / IOC1_3 / KWT3 PT2 / DBGEEV / IOC1_2 / KWT2 M0COSM / M0C0M / IOC0_0 / PU0...
Page 47 Chapter 1 Device Overview MC9S12ZVH-Family FP27 / PG3 BKGD / MODC FP26 / PG2 PC5 / SGA0 FP25 / PG1 PC4 / SGT0 FP24 / PG0 PT4 / PDO / IOC1_4 / KWT4 VLCD PT3 / PDOCLK / IOC1_3 / KWT3 FP23 / PF7 PT2 / DBGEEV / IOC1_2 / KWT2 KWT7 / IOC1_7 / PT7...
Page 48 Chapter 1 Device Overview MC9S12ZVH-Family Table 1-7. Pin Summary LQFP Internal Pull Function Option Resistor Power Supply Reset CTRL Func. Func. Func. Func. Func. State FP24 — — — — VDDX PERG/ Pull PPSG Down VLCD — — — — —...
Page 49 Chapter 1 Device Overview MC9S12ZVH-Family Table 1-7. Pin Summary LQFP Internal Pull Function Option Resistor Power Supply Reset CTRL Func. Func. Func. Func. Func. State — VDDM2 — — — — — — — — — VSSM2 — — — —...
Page 50 Chapter 1 Device Overview MC9S12ZVH-Family Table 1-7. Pin Summary LQFP Internal Pull Function Option Resistor Power Supply Reset CTRL Func. Func. Func. Func. Func. State FP12 — — — — VDDX PERD/ Pull PPSD Down FP11 — — — — VDDX PERD/ Pull...
Page 51 Chapter 1 Device Overview MC9S12ZVH-Family Table 1-7. Pin Summary LQFP Internal Pull Function Option Resistor Power Supply Reset CTRL Func. Func. Func. Func. Func. State VDDF — — — — — — — — RXCAN0 — — — — PERC/ Disabled PPSC —...
Page 52 Chapter 1 Device Overview MC9S12ZVH-Family Table 1-7. Pin Summary LQFP Internal Pull Function Option Resistor Power Supply Reset CTRL Func. Func. Func. Func. Func. State — — — — — — — — — — VSENS — — — — —...
Page 53 Chapter 1 Device Overview MC9S12ZVH-Family Table 1-7. Pin Summary LQFP Internal Pull Function Option Resistor Power Supply Reset CTRL Func. Func. Func. Func. Func. State SGA0 — — — — PERC/ Disabled PPSC — RXD1 — — — — PERC/ Disabled PPSC —...
Page 54 Chapter 1 Device Overview MC9S12ZVH-Family Table 1-7. Pin Summary LQFP Internal Pull Function Option Resistor Power Supply Reset CTRL Func. Func. Func. Func. Func. State — PWM4 — — — — PERP/ Disabled PPSP — — — — PERB/ Pull PPSB Down —...
Page 55: Modes Of Operation
Chapter 1 Device Overview MC9S12ZVH-Family Table 1-7. Pin Summary LQFP Internal Pull Function Option Resistor Power Supply Reset CTRL Func. Func. Func. Func. Func. State FP27 — — — — VDDX PERG/ Pull PPSG Down 1.10 Modes of Operation The MCU can operate in different modes. These are described in 1.10.1 Chip Configuration Modes.
Page 56: Debugging Modes
Chapter 1 Device Overview MC9S12ZVH-Family 1.10.2 Debugging Modes The background debug mode (BDM) can be activated by the BDC module or directly when resetting into Special Single-Chip mode. Detailed information can be found in the BDC module section. Writing to internal memory locations using the debugger, whilst code is running or at a breakpoint, can change the flow of application code.
Page 57: Security
Chapter 1 Device Overview MC9S12ZVH-Family With the BDC enabled during Stop, the VREG full performance mode and clock activity lead to higher current consumption than with BDC disabled — If the BDC is enabled in Stop mode, then the voltage monitoring remains enabled. 1.11 Security The MCU security mechanism prevents unauthorized access to the flash memory.
Page 58: Operation Of The Secured Microcontroller
Chapter 1 Device Overview MC9S12ZVH-Family NOTE Please refer to the 21.5 Security for more security byte details. 1.11.3 Operation of the Secured Microcontroller By securing the device, unauthorized access to the EEPROM and Flash memory contents is prevented. Secured operation has the following effects on the microcontroller: 1.11.3.1 Normal Single Chip Mode (NS) •...
Page 59: Reprogramming The Security Bits
Chapter 1 Device Overview MC9S12ZVH-Family NOTE No word backdoor key word is allowed to have the value 0x0000 or 0xFFFF. 1.11.5 Reprogramming the Security Bits In normal single chip mode, security can also be disabled by erasing and reprogramming the security bits within Flash options/security byte to the unsecured value.
Page 60: Interrupt Vectors
Chapter 1 Device Overview MC9S12ZVH-Family 1.12.2 Interrupt Vectors Table 1-11 lists all interrupt sources and vectors in the default order of priority. The interrupt module description provides an Interrupt Vector Base register (IVBR) to relocate the vectors. Table 1-11. Interrupt Vector Locations (Sheet 1 of 3) Wake up Wake up Vector Address...
Page 61 Chapter 1 Device Overview MC9S12ZVH-Family Table 1-11. Interrupt Vector Locations (Sheet 2 of 3) Wake up Wake up Vector Address Interrupt Source Local Enable Mask from STOP from WAIT Vector base + 0x18C ADC0 Error I bit ADC0EIE(IA_EIE,CMD_EIE, EOL_EIE,TRIG_EIE,RSTAR_ EIE,LDOK_EIE) ADC0IE(CONIF_OIE) Vector base + 0x188 ADC0 conversion sequence abort...
Page 62: Effects Of Reset
Chapter 1 Device Overview MC9S12ZVH-Family Table 1-11. Interrupt Vector Locations (Sheet 3 of 3) Wake up Wake up Vector Address Interrupt Source Local Enable Mask from STOP from WAIT Vector base + 0xF4 Port AD interrupt I bit PIEADL(PIEADL[7:0]) Vector base + 0xF0 Reserved Vector base + 0xB8 Vector base + 0xB4...
Page 63: Cop Configuration
Chapter 1 Device Overview MC9S12ZVH-Family On each reset, the Flash module executes a reset sequence to load Flash configuration registers 1.12.3.1 Flash Configuration Reset Sequence Phase On each reset, the Flash module will hold CPU activity while loading Flash module registers from the Flash memory.
Page 64: Adc0 Internal Channels
Chapter 1 Device Overview MC9S12ZVH-Family Table 1-13. Initial WCOP Configuration NV[3] in WCOP in FOPT Register COPCTL Register 1.14 ADC0 Internal Channels Table 1-14 lists the internal sources which are connected to these special conversion channels. Table 1-14. ADC0 Channel Assignment ADC0CMD_1 CH_SEL[5:0] Analog Input Usage...
Page 65: Adc Result Reference
Chapter 1 Device Overview MC9S12ZVH-Family 1.17 ADC Result Reference MCUs of the MC9S12ZVH-Family are able to measure the internal reference voltage V (see Table 1- 14). V is a constant voltage with a narrow distribution over temperature and external voltage supply (see Table I-1).
Page 66: Lcd Clock Source Connectivity
Chapter 1 Device Overview MC9S12ZVH-Family OSC, user need to config the registers in CPMU block, refer to Chapter 7, “S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6)“ for more detailed information. And main OSC will be stop if silicon enter full stop mode. On 1N65E device, if the clock source is from IRC, it will be stop if silicon enter stop mode.
Page 67: Introduction
Chapter 2 Port Integration Module (S12ZVHPIMV0) Revision History Rev. No. Date (Submitted Sections Substantial Change(s) (Item No.) Affected V00.01 18 Mar 2011 • Initial Version V00.09 18 Mar 2012 • update the MODRR0 related description V00.10 12 Oct 2012 • fix typos, add XIRQ function explain Introduction 2.1.1 Overview...
Page 68: Features
Chapter 2 Port Integration Module (S12ZVHPIMV0) — DBG external signals PDO, PDOCLK and DBGEEV — ECLK output • 8-pin port AD associated with 8 ADC0 channels; associated with the key wakeup function also • 8-pin port U associated with SSD0, SSD1, 2 Motor controls and 4 TIM0 channels •...
Page 69: External Signal Description
Chapter 2 Port Integration Module (S12ZVHPIMV0) • 5V digital and analog input • Input with selectable pullup or pulldown device Optional features supported on dedicated pins: • Open drain for wired-or connections • Interrupt input with glitch filtering • Slew rate control on motor pads External Signal Description This section lists and describes the signals that do connect off-chip.
Page 70 Chapter 2 Port Integration Module (S12ZVHPIMV0) Pin Function Port Pin Name Description Routing Register Function & Priority after Reset O LCD FP7 signal GPIO (PWM6) O PWM channel 6 PWM6RR PTA[7] I/O General-purpose O LCD FP6 signal (PWM4) O PWM channel 4 PWM4RR PTA[6] I/O General-purpose...
Page 71 Chapter 2 Port Integration Module (S12ZVHPIMV0) Pin Function Port Pin Name Description Routing Register Function & Priority after Reset TXD1 O TXD of SCI1 GPIO PTC[7] I/O General-purpose RXD1 RXD of SCI1 PTC[6] I/O General-purpose SGA0 O SGA of SSG0 PTC[5] I/O General-purpose SGT0...
Page 72 Chapter 2 Port Integration Module (S12ZVHPIMV0) Pin Function Port Pin Name Description Routing Register Function & Priority after Reset 32K_XTAL 32K OSC signal PTE[3] I/O General-purpose 32K_EXTAL 32K OSC signal PTE[2] I/O General-purpose GPIO XTAL CPMU OSC signal PTE[1] I/O General-purpose EXTAL CPMU OSC signal PTE[0]...
Page 73 Chapter 2 Port Integration Module (S12ZVHPIMV0) Pin Function Port Pin Name Description Routing Register Function & Priority after Reset FP31 O LCD FP31 signal GPIO PTG[7] I/O General-purpose FP30 O LCD FP30 signal PTG[6] I/O General-purpose FP29 O LCD FP29 signal PTG[5] I/O General-purpose FP28...
Page 74 Chapter 2 Port Integration Module (S12ZVHPIMV0) Pin Function Port Pin Name Description Routing Register Function & Priority after Reset (TXD1) O TXD of SCI1 SCI1RR GPIO PWM7 O PWM channel 7 PP[7] I/O General-purpose PWM6 O PWM channel 6 PP[6] I/O General-purpose (RXD1) O RXD of SCI1...
Page 75 Chapter 2 Port Integration Module (S12ZVHPIMV0) Pin Function Port Pin Name Description Routing Register Function & Priority after Reset IOC1_7 O TIM1 channel 7 GPIO PTT[7]/KWT[7] I/O General-purpose; with interrupt and wakeup IOC1_6 I/O TIM1 channel 6 ECLK O Free running clock output PTT[6]/KWT[6] I/O General-purpose;...
Page 76 Chapter 2 Port Integration Module (S12ZVHPIMV0) Pin Function Port Pin Name Description Routing Register Function & Priority after Reset PAD7 AN0_7 ADC0 analog input 7 PTADL[7]/ I/O General-purpose; with interrupt and wakeup KWADL[7] PAD6 AN0_6 ADC0 analog input 6 PTADL[6]/ I/O General-purpose;...
Page 77 Chapter 2 Port Integration Module (S12ZVHPIMV0) Pin Function Port Pin Name Description Routing Register Function & Priority after Reset PU[7] M1SINP I/O SSD1 Sine+ Node GPIO M1C1P O Motor control output for motor 1 PTU[7] I/O General purpose PU[6] M1SINM I/O SSD1 Sine- Node M1C1M O Motor control output for motor 1...
Page 78: Memory Map And Register Definition
Chapter 2 Port Integration Module (S12ZVHPIMV0) Pin Function Port Pin Name Description Routing Register Function & Priority after Reset PV[7] M3SINP I/O SSD3 Sine+ Node GPIO M3C1P O Motor control output for motor 3 PTV[7] I/O General purpose PV[6] M3SINM I/O SSD3 Sine- Node M3C1M O Motor control output for motor 3...
Page 79: Register Map
Chapter 2 Port Integration Module (S12ZVHPIMV0) 2.3.1 Register Map Global Register Bit 7 Bit 0 Address Name C0CP0RR C0CP0RR C0CP0RR C0CP0RR 0x0200 MODRR0 0x0201 MODRR1 PWM6RR PWM4RR PWM2RR PWM0RR 0x0202 MODRR2 SCI1RR IIC0RR T1IC0RR1 T1IC0RR0 0x0203– Reserved 0x0207 0x0208 ECLKCTL NECLK 0x0209 IRQCR...
Page 80 Chapter 2 Port Integration Module (S12ZVHPIMV0) Global Register Bit 7 Bit 0 Address Name 0x0224 DDRA DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 0x0225 DDRB DDRB3 DDRB2 DDRB1 DDRB0 0x0226 PERA PERA7 PERA6 PERA5 PERA4 PERA3 PERA2 PERA1 PERA0 0x0227 PERB PERB3...
Page 81 Chapter 2 Port Integration Module (S12ZVHPIMV0) Global Register Bit 7 Bit 0 Address Name 0x0247 PERD PERD7 PERD6 PERD5 PERD4 PERD3 PERD2 PERD1 PERD0 0x0248 PPSC PPSC7 PPSC6 PPSC5 PPSC4 PPSC3 PPSC2 PPSC1 PPSC0 0x0249 PPSD PPSD7 PPSD6 PPSD5 PPSD4 PPSD3 PPSD2 PPSD1...
Page 82 Chapter 2 Port Integration Module (S12ZVHPIMV0) Global Register Bit 7 Bit 0 Address Name 0x0281 PTADL PTADL7 PTADL6 PTADL5 PTADL4 PTADL3 PTADL2 PTADL1 PTADL0 0x0282 Reserved R PTIADL7 PTIADL6 PTIADL5 PTIADL4 PTIADL3 PTIADL2 PTIADL1 PTIADL0 0x0283 PTIADL 0x0284 Reserved 0x0285 DDRADL DDRADL7 DDRADL6 DDRADL5 DDRADL4 DDRADL3 DDRADL2 DDRADL1 DDRADL0 0x0286...
Page 83 Chapter 2 Port Integration Module (S12ZVHPIMV0) Global Register Bit 7 Bit 0 Address Name 0x029A– Reserved 0x02BF 0x02C0 PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 0x02C1 PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0 PTIT 0x02C2 DDRT DDRT7 DDRT6 DDRT5 DDRT4 DDRT3...
Page 84 Chapter 2 Port Integration Module (S12ZVHPIMV0) Global Register Bit 7 Bit 0 Address Name 0x02D6 PIES PIES7 PIES6 PIES5 PIES4 PIES3 PIES2 PIES1 PIES0 0x02D7 PIFS PIFS7 PIFS6 PIFS5 PIFS4 PIFS3 PIFS2 PIFS1 PIFS0 0x02D8– Reserved 0x02DE 0x02DF WOMS WOMS7 WOMS6 WOMS5 WOMS4...
Page 85 Chapter 2 Port Integration Module (S12ZVHPIMV0) Global Register Bit 7 Bit 0 Address Name 0x0305– Reserved 0x030F 0x0310– Reserved 0x031F 0x0320 PTG7 PTG6 PTG5 PTG4 PTG3 PTG2 PTG1 PTG0 0x0321 PTIG PTIG7 PTIG6 PTIG5 PTIG4 PTIG3 PTIG2 PTIG1 PTIG0 0x0322 DDRG DDRG7 DDRG6...
Page 86: Register Descriptions
Chapter 2 Port Integration Module (S12ZVHPIMV0) Global Register Bit 7 Bit 0 Address Name 0x0360 PTV7 PTV6 PTV5 PTV4 PTV3 PTV2 PTV1 PTV0 PTIV7 PTIV6 PTIV5 PTIV4 PTIV3 PTIV2 PTIV1 PTIV0 0x0361 PTIV 0x0362 DDRV DDRV7 DDRV6 DDRV5 DDRV4 DDRV3 DDRV2 DDRV1 DDRV0...
Page 87 Chapter 2 Port Integration Module (S12ZVHPIMV0) 2.3.2.1 Module Routing Register 0 (MODRR0) Address 0x0200 Access: User read/write C0CP0RR3 C0CP0RR2 C0CP0RR1 C0CP0RR0 — — — — CAN0-CANPHY0 (see Figure 2-2) Reset Figure 2-1. Module Routing Register 0 (MODRR0) 1. Read: Anytime Write: Once in normal, anytime in special mode For routing options refer to Figure...
Page 88 Chapter 2 Port Integration Module (S12ZVHPIMV0) C0CP0RR[3:0] Signal Routing Description TXCAN0->PS5 Conformance test mode, interface opened and all 4 PC3->CPTXD0 signals routed externally CPRXD0->PC2 PS4->RXCAN0 1. if CANPHY is not enabled, then PC3/PC2 will be controlled by other functions. The configure can be use for standalone MSCAN connection.
Page 89 Chapter 2 Port Integration Module (S12ZVHPIMV0) 2.3.2.2 Module Routing Register 1 (MODRR1) Address 0x0201 Access: User read/write PWM6RR PWM4RR PWM2RR PWM0RR — — — — PWM6 PWM4 PWM2 PWM0 Reset Figure 2-3. Module Routing Register 1 (MODRR1) 1. Read: Anytime Write: Once in normal, anytime in special mode Table 2-4.
Page 90 Chapter 2 Port Integration Module (S12ZVHPIMV0) 2.3.2.3 Module Routing Register 2 (MODRR2) Address 0x0202 Access: User read/write SCI1RR IIC0RR T1IC0RR1 T1IC0RR0 SCI1 IIC0 TI M1 IC0 Reset Figure 2-4. Module Routing Register 2 (MODRR2) 1. Read: Anytime Write: Once in normal, anytime in special mode Table 2-5.
Page 91 Chapter 2 Port Integration Module (S12ZVHPIMV0) 2.3.2.4 ECLK Control Register (ECLKCTL) Address 0x0208 Access: User read/write NECLK Reset: Figure 2-5. ECLK Control Register (ECLKCTL) 1. Read: Anytime Write: Anytime Table 2-6. ECLKCTL Register Field Descriptions Field Description No ECLK — Disable ECLK output NECLK This bit controls the availability of a free-running clock on the ECLK pin.
Page 92 Chapter 2 Port Integration Module (S12ZVHPIMV0) Table 2-7. IRQCR Register Field Descriptions Field Description IRQ select edge sensitive only — IRQE 1 IRQ pin configured to respond only to falling edges. Falling edges on the IRQ pin are detected anytime when IRQE=1 and will be cleared only upon a reset or the servicing of the IRQ interrupt.
Page 93 Chapter 2 Port Integration Module (S12ZVHPIMV0) 2.3.2.7 Reserved Register PIM Test Register Address 0x020E Access: User read/write Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reset Figure 2-8. Reserved Register 1. Read: Anytime Write: Only in special mode These reserved registers are designed for factory test purposes only and are not intended for general user access.
Page 94 Chapter 2 Port Integration Module (S12ZVHPIMV0) Table 2-9. Port C Polarity Select Register Field Descriptions Field Description Pull Polarity Select — Configure pull device on input pin PPSC This bits select a pullup or a pulldown device if enabled on the associated port input pin. 1 pulldown device selected 0 pullup device selected Port P Pull Polarity Select —...
Page 95 Chapter 2 Port Integration Module (S12ZVHPIMV0) Table 2-10. Port S Polarity Select Register Field Descriptions Field Description Pull Polarity Select — Configure pull device and pin interrupt edge polarity on input pin PPSS This bits select a pullup or a pulldown device if enabled on the associated port input pin. 1 pulldown device selected;...
Page 96 Chapter 2 Port Integration Module (S12ZVHPIMV0) Table 2-11. Port Data Register Field Descriptions Field Description Port — General purpose input/output data This register holds the value driven out to the pin if the pin is used as a general purpose output. When not used with the alternative function (refer to Table 2-1), these pins can be used as general purpose I/O.
Page 97 Chapter 2 Port Integration Module (S12ZVHPIMV0) 2.3.2.12 Data Direction Register Address 0x0224 DDRA Access: User read/write 0x0225 DDRB 0x0244 DDRC 0x0245 DDRD 0x0264 DDRE 0x0265 DDRF 0x0285 DDRADL 0x02C2 DDRT 0x02D2 DDRS 0x02F2 DDRP 0x0302 DDRH 0x0322 DDRG 0x0352 DDRU 0x0362 DDRV DDRx7 DDRx6...
Page 98 Chapter 2 Port Integration Module (S12ZVHPIMV0) 2.3.2.13 Digital Input Enable Register Address 0x0299 DIENADL Access: User read/write DIENx7 DIENx6 DIENx5 DIENx4 DIENx3 DIENx2 DIENx1 DIENx0 Reset Figure 2-15. Digital Input Enable Register 1. Read: Anytime Write: Anytime Table 2-14. Digital Input Enable Register Field Descriptions Field Description Digital Input Enable —...
Page 99 Chapter 2 Port Integration Module (S12ZVHPIMV0) 2.3.2.14 Pull Device Enable Register Address 0x0226 PERA Access: User read/write 0x0227 PERB 0x0246 PERC 0x0247 PERD 0x0266 PERE 0x0267 PERF 0x0287 PERADL 0x02C3 PERT 0x02D3 PERS 0x02F3 PERP 0x0303 PERH 0x0323 PERG 0x0353 PERU 0x0363 PERV PERx7 PERx6...
Page 100 Chapter 2 Port Integration Module (S12ZVHPIMV0) 2.3.2.15 Polarity Select Register Address 0x0228 PPSA Access: User read/write 0x0229 PPSB 0x0248 PPSC 0x0249 PPSD 0x0268 PPSE 0x0269 PPSF 0x0289 PPSADL 0x02C4 PPST 0x02D4 PPSS 0x02F4 PPSP 0x0304 PPSH 0x0324 PPSG 0x0354 PPSU 0x0364 PPSV PPSx7 PPSx6...
Page 101 Chapter 2 Port Integration Module (S12ZVHPIMV0) 2.3.2.16 Wired-Or Mode Register Address 0x023E WOMA Access: User read/write 0x02DF WOMS WOMx7 WOMx6 WOMx5 WOMx4 WOMx3 WOMx2 WOMx1 WOMx0 Reset Figure 2-18. Wired-Or Mode Register 1. Read: Anytime Write: Anytime Table 2-17. Wired-Or Mode Register Field Descriptions Field Description Wired-Or Mode —...
Page 102 Chapter 2 Port Integration Module (S12ZVHPIMV0) 2.3.2.18 Port Interrupt Flag Register Address 0x02C7 PIFT Access: User read/write 0x02D7 PIFS 0x028F PIFADL PIFx7 PIFx6 PIFx5 PIFx4 PIFx3 PIFx2 PIFx1 PIFx0 Reset Figure 2-20. Port Interrupt Flag Register 1. Read: Anytime Write: Anytime Table 2-19.
Page 103: Functional Description
Chapter 2 Port Integration Module (S12ZVHPIMV0) 1. When change SRRx from non-zero value to zero value or vice versa, It will need to wait about 300 nanoseconds delay before the slew rate control to be real function as setting. When enter STOP, to save the power, the slew rate control will be force to off state.
Page 104 Chapter 2 Port Integration Module (S12ZVHPIMV0) Table 2-21. Register availability per port Slew Data Pull Polarity Wired- Interrupt Interrupt Port Data Input Rate Direction Enable Select Or Mode Enable Flag Enable 1. Each cell represents one register with individual configuration bits 2.
Page 105 Chapter 2 Port Integration Module (S12ZVHPIMV0) 1. To use the digital input function the related bit in Digital Input Enable Register (DIENADx) must be set to logic level “1”. To use the digital input function the related bit in Slew Rate Register (SRRx) must be set to logic level “0”. 2.4.2.1 Data register (PTx) This register holds the value driven out to the pin if the pin is used as a general-purpose I/O.
Page 106 Chapter 2 Port Integration Module (S12ZVHPIMV0) data out Module output enable module enable Figure 2-23. Illustration of I/O pin functionality 2.4.2.4 Pull device enable register (PERx) This register turns on a pullup or pulldown device on the related pins determined by the associated polarity select register (Section 2.4.2.5, “Polarity select register (PPSx)”).
Page 107: Interrupts
Chapter 2 Port Integration Module (S12ZVHPIMV0) 2.4.2.8 Interrupt flag register (PIFx) If the pin is used as an interrupt input this register holds the interrupt flag after a valid pin event. 2.4.2.9 Digital input enable register (DIENADx) This register controls the digital input buffer. If DIENADx is set to logic level “1”, then it will enable the digital input buffer.
Page 108: Pin Interrupts And Wakeup
Chapter 2 Port Integration Module (S12ZVHPIMV0) Both interrupts are capable to wake-up the device from stop mode. Means for glitch filtering are not provided on these pins. 2.4.4 Pin interrupts and Wakeup Ports S, T and AD offer pin interrupt and key-wakeup capability. The related interrupt enable (PIE) as well as the sensitivity to rising or falling edges (PPS) can be individually configured on per-pin basis.
Page 109: Initialization And Application Information
Chapter 2 Port Integration Module (S12ZVHPIMV0) Initialization and Application Information 2.5.1 Port Data and Data Direction Register writes It is not recommended to write PORTx/PTx and DDRx in a word access. When changing the register pins from inputs to outputs, the data may have extra transitions during the write access. Initialize the port data register before enabling the outputs.
Page 110 Chapter 2 Port Integration Module (S12ZVHPIMV0) S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 111: Introduction
Chapter 3 Memory Mapping Control (S12ZMMCV1) Table 3-1. Revision History Revision Sections Revision Date Description of Changes Number Affected • Fixed typos V01.07 3 May 2013 • Removed PTU references Introduction The S12ZMMC module controls the access to all internal memories and peripherals for the S12ZCPU, and the S12ZBDC module.
Page 112: Glossary
Chapter 3 Memory Mapping Control (S12ZMMCV1) 3.1.1 Glossary Table 3-2. Glossary Of Terms Term Definition Microcontroller Unit S12Z Central Processing Unit S12Z Background Debug Controller Analog-to-Digital Converter unmapped Address space that is not assigned to a memory address range reserved address Address space that is reserved for future use cases range illegal access...
Page 113: Block Diagram
Chapter 3 Memory Mapping Control (S12ZMMCV1) 3.1.4.2 Power modes The S12ZMMC module is only active in run and wait mode.There is no bus activity in stop mode. 3.1.5 Block Diagram S12ZCPU S12ZBDC Memory Protection Register Block Crossbar Switch Program EEPROM Peripherals Flash Figure 3-1.
Page 114: Register Descriptions
Chapter 3 Memory Mapping Control (S12ZMMCV1) Address Name Bit 7 Bit 0 0x0070 MODE MODC 0x0071- Reserved 0x007F 0x0080 MMCECH ITR[3:0] TGT[3:0] 0x0081 MMCECL ACC[3:0] ERR[3:0] 0x0082 MMCCCRH CPUU 0x0083 MMCCCRL CPUX CPUI 0x0084 Reserved 0x0085 MMCPCH CPUPC[23:16] 0x0086 MMCPCM CPUPC[15:8] 0x0087 MMCPCL...
Page 115 Chapter 3 Memory Mapping Control (S12ZMMCV1) 3.3.2.1 Mode Register (MODE) Address: 0x0070 MODC Reset MODC 1. External signal (see Table 3-3). = Unimplemented or Reserved Figure 3-3. Mode Register (MODE) Read: Anytime. Write: Only if a transition is allowed (see Figure 3-4).
Page 116 Chapter 3 Memory Mapping Control (S12ZMMCV1) 3.3.2.2 Error Code Register (MMCECH, MMCECL) Address: 0x0080 (MMCECH) ITR[3:0] TGT[3:0] Reset Address: 0x0081 (MMCECL) ACC[3:0] ERR[3:0] Reset Figure 3-5. Error Code Register (MMCEC) Read: Anytime Write: Write of 0xFFFF to MMCECH:MMCECL resets both registers to 0x0000 Table 3-5.
Page 117 Chapter 3 Memory Mapping Control (S12ZMMCV1) Field Description Access Type Field — The ACC[3:0] bits capture the type of memory access, which caused the access (MMCECL) ACC[3:0] violation. The access type is captured in form of a 4 bit value which is assigned as follows: none (no error condition detected) opcode fetch vector fetch...
Page 118 Chapter 3 Memory Mapping Control (S12ZMMCV1) Table 3-6. MMCCCRH and MMCCCRL Field Descriptions Field Description S12ZCPU User State Flag — This bit shows the state of the user/supervisor mode bit in the S12ZCPU’s CCR (MMCCCRH) CPUU at the time the access violation has occurred. The S12ZCPU user state flag is read-only; it will be automatically updated when the next error condition is flagged through the MMCEC register.
Page 119: Functional Description
Chapter 3 Memory Mapping Control (S12ZMMCV1) Table 3-7. MMCPCH, MMCPCM, and MMCPCL Field Descriptions Field Description 7–0 S12ZCPU Program Counter Value— The CPUPC[23:0] stores the CPU’s program counter value at the time (MMCPCH) 7–0 the access violation occurred. CPUPC[23:0] always points to the instruction which triggered the violation. These (MMCPCM) 7–0 bits are undefined if the error code registers (MMCECn) are cleared.
Page 120 Chapter 3 Memory Mapping Control (S12ZMMCV1) Register Space 0x00_0000 4 KB 0x00_1000 max. 1 MByte - 4 KB 0x10_0000 EEPROM max. 1 MByte - 48 KB 0x1F_4000 512 Byte Reserved 0x1F_8000 6 KBKB Reserved (read only) 0x1F_C000 256 Byte NVM IFR 0x20_0000 Unmapped 6 MByte...
Page 121: Illegal Accesses
Chapter 3 Memory Mapping Control (S12ZMMCV1) 3.4.2 Illegal Accesses The S12ZMMC module monitors all memory traffic for illegal accesses. See Table 3-8 for a complete list of all illegal accesses. Table 3-8. Illegal memory accesses S12ZCPU S12ZBDC Read access illegal access Register Write access illegal access...
Page 122: Uncorrectable Ecc Faults
Chapter 3 Memory Mapping Control (S12ZMMCV1) • All illegal accesses performed by the ADC module trigger error interrupts. See ADC section for details. NOTE Illegal accesses caused by S12ZCPU opcode prefetches will also trigger machine exceptions, even if those opcodes might not be executed in the program flow.
Page 123: Introduction
Chapter 4 Interrupt (S12ZINTV0) Table 4-1. Revision History Version Revision Effective Description of Changes Number Date Date V00.01 17 Apr 2009 Initial version based on S12XINT V2.06 V00.02 14 Jul 2009 Reduce RESET vectors from three to one. V00.03 05 Oct 2009 Removed dedicated ECC machine exception vector and marked vector-table entry “reserved for future use”.
Page 124: Glossary
Chapter 4 Interrupt (S12ZINTV0) • One non-maskable system call interrupt (SYS) • One non-maskable machine exception vector request • One spurious interrupt vector request • One system reset vector request Each of the I-bit maskable interrupt requests can be assigned to one of seven priority levels supporting a flexible priority scheme.
Page 125: Modes Of Operation
Chapter 4 Interrupt (S12ZINTV0) • up to 113 additional I-bit maskable interrupt vector requests (at addresses vector base + 0x000010 .. vector base + 0x0001D0). • Each I-bit maskable interrupt request has a configurable priority level. • I-bit maskable interrupts can be nested, depending on their priority levels. •...
Page 126: External Signal Description
Chapter 4 Interrupt (S12ZINTV0) Peripheral Wake Up Interrupt Requests Vector Address Non I Bit Maskable Channels IVBR Interrupt Requests Priority PRIOLVL2 Level One Set Per Channel PRIOLVL1 Filter (Up to 117 Channels) PRIOLVL0 Current Highest Pending Priority Level PRIOLVLn = configuration bits from the associated channel configuration register = Interrupt Vector Base IVBR...
Page 127: Register Descriptions
Chapter 4 Interrupt (S12ZINTV0) Table 4-3. INT Memory Map 0x000019 Interrupt Request Configuration Data Register 1 (INT_CFDATA1) 0x00001A Interrupt Request Configuration Data Register 2 (INT_CFDATA2 0x00001B Interrupt Request Configuration Data Register 3 (INT_CFDATA3) 0x00001C Interrupt Request Configuration Data Register 4 (INT_CFDATA4) 0x00001D Interrupt Request Configuration Data Register 5...
Page 128 Chapter 4 Interrupt (S12ZINTV0) Register Address Bit 7 Bit 0 Name 0x00001D INT_CFDATA5 R PRIOLVL[2:0] 0x00001E INT_CFDATA6 R PRIOLVL[2:0] 0x00001F INT_CFDATA7 R PRIOLVL[2:0] = Unimplemented or Reserved Figure 4-2. INT Register Summary 4.3.2.1 Interrupt Vector Base Register (IVBR) Address: 0x000010 IVB_ADDR[15:1] Reset Figure 4-3.
Page 129 Chapter 4 Interrupt (S12ZINTV0) Write: Anytime Table 4-5. INT_CFADDR Field Descriptions Field Description 6–3 Interrupt Request Configuration Data Register Select Bits — These bits determine which of the 128 INT_CFADDR[6:3] configuration data registers are accessible in the 8 register window at INT_CFDATA0–7. The hexadecimal value written to this register corresponds to the upper 4 bits of the vector number (multiply with 4 to get the vector address offset).
Page 130 Chapter 4 Interrupt (S12ZINTV0) 1. Please refer to the notes following the PRIOLVL[2:0] description below. Address: 0x00001B PRIOLVL[2:0] Reset = Unimplemented or Reserved Figure 4-8. Interrupt Request Configuration Data Register 3 (INT_CFDATA3) 1. Please refer to the notes following the PRIOLVL[2:0] description below. Address: 0x00001C PRIOLVL[2:0] Reset...
Page 131: Functional Description
Chapter 4 Interrupt (S12ZINTV0) Address: 0x00001F PRIOLVL[2:0] Reset = Unimplemented or Reserved Figure 4-12. Interrupt Request Configuration Data Register 7 (INT_CFDATA7) 1. Please refer to the notes following the PRIOLVL[2:0] description below. Read: Anytime Write: Anytime Table 4-6. INT_CFDATA0–7 Field Descriptions Field Description 2–0...
Page 132: S12Z Exception Requests
Chapter 4 Interrupt (S12ZINTV0) 4.4.1 S12Z Exception Requests The CPU handles both reset requests and interrupt requests. The INT module contains registers to configure the priority level of each I-bit maskable interrupt request which can be used to implement an interrupt priority scheme.
Page 133: Priority Decoder
Chapter 4 Interrupt (S12ZINTV0) 4.4.3 Priority Decoder The INT module contains a priority decoder to determine the relative priority for all interrupt requests pending for the CPU. A CPU interrupt vector is not supplied until the CPU requests it. Therefore, it is possible that a higher priority interrupt request could override the original exception which caused the CPU to request the vector.
Page 134: Interrupt Vector Table Layout
Chapter 4 Interrupt (S12ZINTV0) Table 4-8. Exception Vector Map and Priority Vector Address Source (Vector base + 0x0001E8) Machine exception vector request (Vector base + 0x0001E4) Reserved (Vector base + 0x0001E0) Reserved (Vector base + 0x0001DC) Spurious interrupt (Vector base + 0x0001D8) XIRQ interrupt request (Vector base + 0x0001D4) IRQ interrupt request...
Page 135: Wake Up From Stop Or Wait Mode
Chapter 4 Interrupt (S12ZINTV0) I-bit maskable interrupt requests cannot be interrupted by other I-bit maskable interrupt requests per default. In order to make an interrupt service routine (ISR) interruptible, the ISR must explicitly clear the I-bit in the CCW (CLI). After clearing the I-bit, I-bit maskable interrupt requests with higher priority can interrupt the current ISR.
Page 136 Chapter 4 Interrupt (S12ZINTV0) bit in the CCW set, the associated ISR is not called. The CPU then resumes program execution with the instruction following the WAI or STOP instruction. This feature works following the same rules like any interrupt request, i.e. care must be taken that the X-bit maskable interrupt request used for wake-up remains active at least until the system begins execution of the instruction following the WAI or STOP instruction;...
Page 137: Introduction
Chapter 5 Background Debug Controller (S12ZBDCV2) Table 5-1. Revision History Revision Revision Sections Description of Changes Number Date Affected V2.04 03.Dec.2012 Section 5.1.3.3 Included BACKGROUND/ Stop mode dependency V2.05 22.Jan.2013 Section 5.3.2.2 Improved NORESP description and added STEP1/ Wait mode dependency V2.06 22.Mar.2013 Section 5.3.2.2...
Page 138: S12Zvh Family Reference Manual, Rev. 1.05 Freescale Semiconductor
Chapter 5 Background Debug Controller (S12ZBDCV2) 5.1.2 Features The BDC includes these distinctive features: • Single-wire communication with host development system • SYNC command to determine communication rate • Genuine non-intrusive handshake protocol • Enhanced handshake protocol for error detection and stop mode recognition •...
Page 139 Chapter 5 Background Debug Controller (S12ZBDCV2) 5.1.3.3 Low-Power Modes 5.1.3.3.1 Stop Mode The execution of the CPU STOP instruction leads to stop mode only when all bus masters (CPU, or others, depending on the device) have finished processing. The operation during stop mode depends on the ENBDC and BDCCIS bit settings as summarized in Table 5-3 Table 5-3.
Page 140: Block Diagram
Chapter 5 Background Debug Controller (S12ZBDCV2) STOP Mode With BDC Enabled And BDCCIS Set If the BDC is enabled and BDCCIS is set, then the BDC prevents core clocks being disabled in stop mode. This allows BDC communication, for access of internal memory mapped resources, but not CPU registers, to continue throughout stop mode.
Page 141: External Signal Description
Chapter 5 Background Debug Controller (S12ZBDCV2) HOST SERIAL INTERFACE CONTROL SYSTEM AND SHIFT REGISTER BKGD CLOCK DOMAIN BDCSI CONTROL CORE CLOCK INSTRUCTION DECODE AND ADDRESS BUS INTERFACE DATA CONTROL LOGIC BUS CONTROL CPU CONTROL BDCCSR REGISTER ERASE FLASH AND DATAPATH FLASH ERASED CONTROL FLASH SECURE...
Page 142: Register Descriptions
Chapter 5 Background Debug Controller (S12ZBDCV2) 5.3.2 Register Descriptions The BDC registers are shown in Figure 5-2. Registers are accessed only by host-driven communications to the BDC hardware using READ_BDCCSR and WRITE_BDCCSR commands. They are not accessible in the device memory map. Global Register Bit 7...
Page 143 Chapter 5 Background Debug Controller (S12ZBDCV2) Table 5-5. BDCCSRH Field Descriptions Field Description Enable BDC — This bit controls whether the BDC is enabled or disabled. When enabled, active BDM can be ENBDC entered and non-intrusive commands can be carried out. When disabled, active BDM is not possible and the valid command set is restricted.
Page 144 Chapter 5 Background Debug Controller (S12ZBDCV2) 5.3.2.2 BDC Control Status Register Low (BDCCSRL) Register Address: This register is not in the device memory map. It is accessible using BDC inherent addressing commands WAIT STOP RAMWF OVRUN NORESP RDINV ILLACC ILLCMD Reset Figure 5-4.
Page 145 Chapter 5 Background Debug Controller (S12ZBDCV2) Table 5-6. BDCCSRL Field Descriptions (continued) Field Description Overrun Flag — Indicates unexpected host activity before command completion. OVRUN This occurs if a new command is received before the current command completion. With ACK enabled this also occurs if the host drives the BKGD pin low whilst a target ACK pulse is pending To protect internal resources from misinterpreted BDC accesses following an overrun, internal accesses are suppressed until a SYNC clears this bit.
Page 146: Functional Description
Chapter 5 Background Debug Controller (S12ZBDCV2) Table 5-6. BDCCSRL Field Descriptions (continued) Field Description Illegal Command Flag — Indicates an illegal BDC command. This bit is set in the following cases: ILLCMD When an unimplemented BDC command opcode is received. When a DUMP_MEM{_WS}, FILL_MEM{_WS} or READ_SAME{_WS} is attempted in an illegal sequence.
Page 147: Clock Source
Chapter 5 Background Debug Controller (S12ZBDCV2) When BDM is activated, the CPU finishes executing the current instruction. Thereafter only BDC commands can affect CPU register contents until the BDC GO command returns from active BDM to user code or a device reset occurs. When BDM is activated by a breakpoint, the type of breakpoint used determines if BDM becomes active before or after execution of the next instruction.
Page 148 Chapter 5 Background Debug Controller (S12ZBDCV2) Table 5-7. BDC Command Types Secure Command Type CPU Status Command Set Status Status • Read/write access to BDCCSR Secure or Enabled or • Mass erase flash memory using ERASE_FLASH Always-available — Unsecure Disabled •...
Page 149 Chapter 5 Background Debug Controller (S12ZBDCV2) If the ACK pulse handshake protocol is enabled and STEAL is cleared, then the BDC waits for the first free bus cycle to make a non-intrusive access. If no free bus cycle occurs within 512 core clock cycles then the BDC aborts the access, sets the NORESP bit and uses a long ACK pulse to indicate an error condition to the host.
Page 150 Chapter 5 Background Debug Controller (S12ZBDCV2) Table 5-8. BDC Command Summary (continued) Command Command Command Description Mnemonic Classification Structure DUMP_MEM.sz Non-Intrusive (0x32+4 x sz)/dack/rd.sz Dump (read) memory based on operand size (sz). Used with READ_MEM to dump large blocks of memory. An initial READ_MEM is executed to set up the starting address of the block and to retrieve the first result.
Page 151 Chapter 5 Background Debug Controller (S12ZBDCV2) Table 5-8. BDC Command Summary (continued) Command Command Command Description Mnemonic Classification Structure READ_SAME.sz Non-Intrusive (0x50+4 x sz)/dack/rd.sz Read from location. An initial READ_MEM defines the address, subsequent READ_SAME reads return content of same address READ_SAME.sz_WS Non-Intrusive (0x51+4 x sz)/d/ss/rd.sz...
Page 152 Chapter 5 Background Debug Controller (S12ZBDCV2) Upon detecting the sync request from the host (which is a much longer low time than would ever occur during normal BDC communications), the target: 1. Discards any incomplete command 2. Waits for BKGD to return to a logic high. 3.
Page 153 Chapter 5 Background Debug Controller (S12ZBDCV2) with the CPU. An ACK pulse is issued by the target device after this command is executed. This command can be used by the host to evaluate if the target supports the hardware handshake protocol. If the target supports the hardware handshake protocol, subsequent commands are enabled to execute the hardware handshake protocol, otherwise this command is ignored by the target.
Page 154: Dump_Mem.sz_Ws
Chapter 5 Background Debug Controller (S12ZBDCV2) DUMP_MEM.sz host  target  target host 0x36 Data[15-8] Data[7-0] host  target  target  target host host 0x3A Data[31-24] Data[23-16] Data[15-8] Data[7-0] host  target  target  target  target  host host host...
Page 155: Fill_Mem.sz
Chapter 5 Background Debug Controller (S12ZBDCV2) NOTE DUMP_MEM{_WS} is a valid command only when preceded by SYNC, NOP, READ_MEM{_WS}, or another DUMP_MEM{_WS} command. Otherwise, an illegal command response is returned, setting the ILLCMD bit. NOP can be used for inter-command padding without corrupting the address pointer.
Page 156 Chapter 5 Background Debug Controller (S12ZBDCV2) FILL_MEM.sz_WS 0x1B Data[31-24] Data[23-16] Data[15-8] Data[7-0] BDCCSRL host  host  host  host  host  target  target target target target target host FILL_MEM{_WS} is used with the WRITE_MEM{_WS} command to access large blocks of memory. An initial WRITE_MEM{_WS} is executed to set up the starting address of the block and write the first datum.
Page 157: Go_Until
Chapter 5 Background Debug Controller (S12ZBDCV2) 5.4.4.8 GO_UNTIL Go Until Active Background 0x0C host  target This command is used to exit active BDM and begin (or resume) execution of application code. The CPU pipeline is flushed and refilled before normal instruction execution resumes. Prefetching begins at the current address in the PC.
Page 158: Read_Mem.sz
Chapter 5 Background Debug Controller (S12ZBDCV2) zero. The register is addressed through the CPU register number (CRN). See Section 5.4.5.1 for the CRN address decoding. If enabled, an ACK pulse is driven before the data bytes are transmitted. If the device is not in active BDM, this command is illegal, the ILLCMD bit is set and no access is performed.
Page 159: Read_Dbgtb
Chapter 5 Background Debug Controller (S12ZBDCV2) after the memory read was performed. If enabled, an ACK pulse is driven before the data bytes are transmitted. The examples show the READ_MEM.B{_WS}, READ_MEM.W{_WS} and READ_MEM.L{_WS} commands. 5.4.4.12 READ_DBGTB Read DBG trace buffer Non-intrusive TB Line [31- TB Line [23-...
Page 160 Chapter 5 Background Debug Controller (S12ZBDCV2) Read from location defined by the previous READ_MEM. The previous READ_MEM command defines the address, subsequent READ_SAME commands return contents of same address. The example shows the sequence for reading a 16-bit word size. Byte alignment details are described in Section 5.4.5.2”.
Page 161 Chapter 5 Background Debug Controller (S12ZBDCV2) 5.4.4.16 WRITE_MEM.sz, WRITE_MEM.sz_WS WRITE_MEM.sz Write memory at the specified address Non-intrusive 0x10 Address[23-0] Data[7–0] host  host  host  target target target 0x14 Address[23-0] Data[15–8] Data[7–0] host  host  host  host  target target target target...
Page 162 Chapter 5 Background Debug Controller (S12ZBDCV2) 5.4.4.17 WRITE_Rn Write general-purpose CPU register Active Background 0x40+CRN Data [31–24] Data [23–16] Data [15–8] Data [7–0] host  host  host  host  host  target target target target target If the device is in active BDM, this command writes the 32-bit operand to the selected CPU general- purpose register.
Page 163: Bdc Access Of Internal Resources
Chapter 5 Background Debug Controller (S12ZBDCV2) During the mass erase operation, which takes many clock cycles, the command status is indicated by the ERASE bit in BDCCSR. Whilst a mass erase operation is ongoing, Always-available commands can be issued. This allows the status of the erase operation to be polled by reading BDCCSR to determine when the operation is finished.
Page 164 Chapter 5 Background Debug Controller (S12ZBDCV2) commands is 32-bits long. The valid bits of the transfer are listed in the Valid Data Bits column. The other bits of the transmission are redundant. Attempted accesses of CPU registers using a CRN of 0xD,0xE or 0xF is invalid, returning the value 0xEE for each byte and setting the ILLACC bit.
Page 165 Chapter 5 Background Debug Controller (S12ZBDCV2) Table 5-10. Field Location to Byte Access Mapping Address[1:0] Access Size Note 32-bit Dat a[31:24] Data[23:16] Data [15:8] Data [7:0] 32-bit Dat a[31:24] Data[23:16] Data [15:8] Data [7:0] Realigned 32-bit Dat a[31:24] Data[23:16] Data [15:8] Data [7:0] Realigned 32-bit Dat...
Page 166: Bdc Serial Interface
Chapter 5 Background Debug Controller (S12ZBDCV2) 5.4.5.2.2 READ_SAME Effects Of Variable Access Size READ_SAME uses the unadjusted address given in the previous READ_MEM command as a base address for subsequent READ_SAME commands. When the READ_MEM and READ_SAME size parameters differ then READ_SAME uses the original base address buts aligns 32-bit and 16-bit accesses, where those accesses would otherwise cross the aligned 4-byte boundary.
Page 167 Chapter 5 Background Debug Controller (S12ZBDCV2) The BDC serial interface uses a clocking scheme in which the external host generates a falling edge on the BKGD pin to indicate the start of each bit time. This falling edge is sent for every bit whether data is transmitted or received.
Page 168 Chapter 5 Background Debug Controller (S12ZBDCV2) drive at the latest after 6 clock cycles, before the target drives a brief high speedup pulse seven target clock cycles after the perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it started the bit time.
Page 169: Serial Interface Hardware Handshake (Ack Pulse) Protocol
Chapter 5 Background Debug Controller (S12ZBDCV2) BDCSI clock (TARGET MCU) HOST DRIVE HIGH-IMPEDANCE TO BKGD PIN SPEEDUP TARGET MCU PULSE DRIVE AND SPEED-UP PULSE PERCEIVED START OF BIT TIME BKGD PIN 10 CYCLES EARLIEST START OF NEXT BIT 10 CYCLES HOST SAMPLES BKGD PIN Figure 5-8.
Page 170 Chapter 5 Background Debug Controller (S12ZBDCV2) The handshake protocol is enabled by the ACK_ENABLE command. The BDC sends an ACK pulse when the ACK_ENABLE command has been completed. This feature can be used by the host to evaluate if the target supports the hardware handshake protocol.
Page 171: Hardware Handshake Abort Procedure
Chapter 5 Background Debug Controller (S12ZBDCV2) The ACK handshake protocol does not support nested ACK pulses. If a BDC command is not acknowledged by an ACK pulse, the host needs to abort the pending command first in order to be able to issue a new BDC command.
Page 172: Hardware Handshake Disabled (Ack Pulse Disabled)
Chapter 5 Background Debug Controller (S12ZBDCV2) READ_MEM.B CMD SYNC RESPONSE IS ABORTED BY THE SYNC REQUEST FROM THE TARGET (NOT TO SCALE) (NOT TO SCALE) BKGD PIN READ_MEM.B ADDRESS[23-0] READ_BDCCSR NEW BDC COMMAND HOST T ARGET HOST T ARGET HOST T ARGET NEW BDC COMMAND BDC DECODES...
Page 173: Single Stepping
Chapter 5 Background Debug Controller (S12ZBDCV2) If the handshake protocol is disabled, the access is always independent of free cycles, whereby BDC has higher priority than CPU. Since at least 2 bytes (command byte + data byte) are transferred over BKGD the maximum intrusiveness is only once every few hundred cycles.
Page 174: Serial Communication Timeout
Chapter 5 Background Debug Controller (S12ZBDCV2) 5.4.11 Serial Communication Timeout The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If BKGD is kept low for more than 128 target clock cycles, the target understands that a SYNC command was issued.
Page 175: Introduction
Chapter 6 S12Z Debug (S12ZDBGV2) Module Table 6-1. Revision History Table Revision Revision Sections Description Of Changes Number Date Affected 2.04 19.APR.2012 Section 6.4.5.2.1 Documented DBGTB read dependency on PROFILE bit 2.05 23.MAY.2012 General Formatting changes to support DBGV3 from single source 2.06 10.SEP.2012 Section 6.4.5.3...
Page 176: Overview
Chapter 6 S12Z Debug (S12ZDBGV2) Module Table 6-2. Glossary Of Terms Term Definition Background Debug Mode. In this mode CPU application code execution is halted. Execution of BDC “active BDM” commands is possible. Background Debug Controller 16-bit data entity WORD 64-bit data entity Data Line S12Z CPU module...
Page 177: Modes Of Operation
Chapter 6 S12Z Debug (S12ZDBGV2) Module — Tracing session triggered by state sequencer — Begin, End, and Mid alignment of tracing to trigger • Four trace modes — Normal: change of flow (COF) PC information is stored (see Section 6.4.5.2.1) for change of flow definition.
Page 178: External Signal Description
Chapter 6 S12Z Debug (S12ZDBGV2) Module External Signal Description 6.2.1 External Event Input The DBG module features an external event input signal, DBGEEV. The mapping of this signal to a device pin is specified in the device specific documentation. This function can be enabled and configured by the EEVE field in the DBGC1 control register.
Page 179 Chapter 6 S12Z Debug (S12ZDBGV2) Module Address Name Bit 7 Bit 0 0x0102 DBGTCRH reserved TSOURCE TRANGE TRCMOD TALIGN 0x0103 DBGTCRL DSTAMP PDOE PROFILE STAMP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0x0104 DBGTB Bit 7...
Page 180 Chapter 6 S12Z Debug (S12ZDBGV2) Module Address Name Bit 7 Bit 0 0x011B DBGAD3 Bit 0 0x011C DBGADM0 Bit 31 Bit 24 0x011D DBGADM1 Bit 23 Bit 16 0x011E DBGADM2 Bit 15 Bit 8 0x011F DBGADM3 Bit 0 0x0120 DBGBCTL INST reserved COMPE...
Page 181: Register Descriptions
Chapter 6 S12Z Debug (S12ZDBGV2) Module Address Name Bit 7 Bit 0 0x013B DBGCD3 Bit 0 0x013C DBGCDM0 Bit 31 Bit 24 0x013D DBGCDM1 Bit 23 Bit 16 0x013E DBGCDM2 Bit 15 Bit 8 0x013F DBGCDM3 Bit 0 0x0140 DBGDCTL INST reserved COMPE...
Page 182 Chapter 6 S12Z Debug (S12ZDBGV2) Module Write: Bit 7 Anytime with the exception that it cannot be set if PTACT is set. An ongoing profiling session must be finished before DBG can be armed again. Bit 6 can be written anytime but always reads back as 0. Bits 5:0 anytime DBG is not armed and PTACT is clear.
Page 183 Chapter 6 S12Z Debug (S12ZDBGV2) Module 6.3.2.2 Debug Control Register2 (DBGC2) Address: 0x0101 CDCM ABCM Reset = Unimplemented or Reserved Figure 6-4. Debug Control Register2 (DBGC2) Read: Anytime. Write: Anytime the module is disarmed and PTACT is clear. This register configures the comparators for range matching. Table 6-5.
Page 184 Chapter 6 S12Z Debug (S12ZDBGV2) Module 6.3.2.3 Debug Trace Control Register High (DBGTCRH) Address: 0x0102 reserved TSOURCE TRANGE TRCMOD TALIGN Reset Figure 6-5. Debug Trace Control Register (DBGTCRH) Read: Anytime. Write: Anytime the module is disarmed and PTACT is clear. WARNING DBGTCR[7] is reserved.
Page 185 Chapter 6 S12Z Debug (S12ZDBGV2) Module Table 6-10. TRCMOD Trace Mode Bit Encoding TRCMOD Description Detail Pure PC Table 6-11. TALIGN Trace Alignment Encoding TALIGN Description Trigger ends data trace Trigger starts data trace 32 lines of data trace follow trigger Reserved 1.
Page 186 Chapter 6 S12Z Debug (S12ZDBGV2) Module Table 6-12. DBGTCRL Field Descriptions (continued) Field Description Timestamp Enable — This bit, when set, enables the timestamp function. The timestamp function adds a STAMP timestamp to each trace buffer entry in Detail, Normal and Loop1 trace modes. 0 Timestamp function disabled 1 Timestamp function enabled 6.3.2.5...
Page 187 Chapter 6 S12Z Debug (S12ZDBGV2) Module Read: Anytime. Write: Never. Table 6-14. DBGCNT Field Descriptions Field Description 6–0 Count Value — The CNT bits [6:0] indicate the number of valid data lines stored in the trace buffer. Table 6-15 CNT[6:0] shows the correlation between the CNT bits and the number of valid data lines in the trace buffer.
Page 188 Chapter 6 S12Z Debug (S12ZDBGV2) Module Table 6-16. DBGSCR1 Field Descriptions Field Description 1–0 Channel 0 State Control. C0SC[1:0] These bits select the targeted next state whilst in State1 following a match0. 3–2 Channel 1 State Control. C1SC[1:0] These bits select the targeted next state whilst in State1 following a match1. 5–4 Channel 2 State Control.
Page 189 Chapter 6 S12Z Debug (S12ZDBGV2) Module Table 6-18. DBGSCR2 Field Descriptions (continued) Field Description 5–4 Channel 2 State Control. C2SC[1:0] These bits select the targeted next state whilst in State2 following a match2. 7–6 Channel 3 State Control. C3SC[1:0] If EEVE !=10, these bits select the targeted next state whilst in State2 following a match3. If EEVE =10, these bits select the targeted next state whilst in State2 following an external event.
Page 190 Chapter 6 S12Z Debug (S12ZDBGV2) Module Table 6-20. DBGSCR3 Field Descriptions (continued) Field Description 7–6 Channel 3 State Control. C3SC[1:0] If EEVE !=10, these bits select the targeted next state whilst in State3 following a match3. If EEVE =10, these bits select the targeted next state whilst in State3 following an external event. Table 6-21.
Page 191 Chapter 6 S12Z Debug (S12ZDBGV2) Module Table 6-22. DBGEFR Field Descriptions Field Description External Event Flag — Indicates the occurrence of an external event during the debug session. EEVF 0 No external event 1 External event 3–0 Match Event[3:0]— Indicates a comparator match event on the corresponding comparator channel ME[3:0] 6.3.2.11 Debug Status Register (DBGSR)
Page 192 Chapter 6 S12Z Debug (S12ZDBGV2) Module Table 6-24. SSF[2:0] — State Sequence Flag Bit Encoding SSF[2:0] Current State 101,110,111 Reserved 6.3.2.12 Debug Comparator A Control Register (DBGACTL) Address: 0x0110 INST reserved COMPE Reset = Unimplemented or Reserved Figure 6-14. Debug Comparator A Control Register Read: Anytime.
Page 193 Chapter 6 S12Z Debug (S12ZDBGV2) Module Table 6-26. Read or Write Comparison Logic Table RWE Bit RW Bit RW Signal Comment RW not used in comparison RW not used in comparison Write match atch atch Read match 6.3.2.13 Debug Comparator A Address Register (DBGAAH, DBGAAM, DBGAAL) Address: 0x0115, DBGAAH DBGAA[23:16] Reset...
Page 194 Chapter 6 S12Z Debug (S12ZDBGV2) Module 6.3.2.14 Debug Comparator A Data Register (DBGAD) Address: 0x0118, 0x0119, 0x011A, 0x011B Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 eset Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8...
Page 195 Chapter 6 S12Z Debug (S12ZDBGV2) Module Write: If DBG not armed and PTACT is clear. This register can be accessed with a byte resolution, whereby DBGADM0, DBGADM1, DBGADM2, DBGADM3 map to DBGADM[31:0] respectively. Table 6-29. DBGADM Field Descriptions Field Description 31–16 Comparator Data Mask Bits —...
Page 196 Chapter 6 S12Z Debug (S12ZDBGV2) Module Table 6-31 shows the effect for RWE and RW on the comparison conditions. These bits are ignored if INST is set, as matches based on instructions reaching the execution stage are data independent. Table 6-31. Read or Write Comparison Logic Table RWE Bit RW Bit RW Signal...
Page 197 Chapter 6 S12Z Debug (S12ZDBGV2) Module 6.3.2.18 Debug Comparator C Control Register (DBGCCTL) Address: 0x0130 INST reserved COMPE Reset = Unimplemented or Reserved Figure 6-20. Debug Comparator C Control Register Read: Anytime. Write: If DBG not armed and PTACT is clear. Table 6-33.
Page 198 Chapter 6 S12Z Debug (S12ZDBGV2) Module Table 6-34. Read or Write Comparison Logic Table RWE Bit RW Bit RW Signal Comment Read match 6.3.2.19 Debug Comparator C Address Register (DBGCAH, DBGCAM, DBGCAL) Address: 0x0135, DBGCAH DBGCA[23:16] Reset Address: 0x0136, DBGCAM DBGCA[15:8] Reset Address: 0x0137, DBGCAL...
Page 199 Chapter 6 S12Z Debug (S12ZDBGV2) Module 6.3.2.20 Debug Comparator C Data Register (DBGCD) Address: 0x0138, 0x0139, 0x013A, 0x013B Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 eset Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8...
Page 200 Chapter 6 S12Z Debug (S12ZDBGV2) Module Write: If DBG not armed and PTACT is clear. This register can be accessed with a byte resolution, whereby DBGCDM0, DBGCDM1, DBGCDM2, DBGCDM3 map to DBGCDM[31:0] respectively. XGATE data accesses have a maximum width of 16-bits and are mapped to DBGCDM[15:0]. Table 6-37.
Page 201 Chapter 6 S12Z Debug (S12ZDBGV2) Module 1. If the CDCM field selects range mode comparisons, then DBGCCTL bits configure the comparison, DBGDCTL is ignored. Table 6-39 shows the effect for RWE and RW on the comparison conditions. These bits are ignored if INST is set, because matches based on opcodes reaching the execution stage are data independent.
Page 202: Functional Description
Chapter 6 S12Z Debug (S12ZDBGV2) Module Table 6-40. DBGDAH, DBGDAM, DBGDAL Field Descriptions Field Description 15–0 Comparator Address Bits[15:0]— These comparator address bits control whether the comparator compares DBGDA the address bus bits [15:0] to a logic one or logic zero. [15:0] 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one...
Page 203 Chapter 6 S12Z Debug (S12ZDBGV2) Module accesses). Furthermore, comparators A and C can compare the data buses to values stored in DBGXD3-0 and allow data bit masking. The comparators can monitor the buses for an exact address or an address range. The comparator configuration is controlled by the control register contents and the range control by the DBGC2 contents.
Page 204 Chapter 6 S12Z Debug (S12ZDBGV2) Module Table 6-41. Comparator Address Bus Matches Access Address ADDR[n] ADDR[n+1] ADDR[n+2] ADDR[n+3] 8-bit ADDR[n] Match No Match No Match No Match If the comparator INST bit is set, the comparator address register contents are compared with the PC, the data register contents and access type bits are ignored.
Page 205 Chapter 6 S12Z Debug (S12ZDBGV2) Module Memory Address[2:0] Access Access Case Address Size 8-bit D BGxD0 8-bit DBGxD1 8-bit DBGxD2 8-bit DBGxD3 8-bit DBGxD0 Denotes byte that is not accessed. For a match of a 32-bit access with data compare, the address comparator must be loaded with the address of the lowest accessed byte.
Page 206: Events
Chapter 6 S12Z Debug (S12ZDBGV2) Module When using the AB comparator pair for a range comparison, the data bus can be used for qualification by using the comparator A data and data mask registers. Similarly when using the CD comparator pair for a range comparison, the data bus can be used for qualification by using the comparator C data and data mask registers.
Page 207 Chapter 6 S12Z Debug (S12ZDBGV2) Module 6.4.3.1.2 Data Access Comparator Match Data access matches are generated when an access occurs at the address contained in the comparator address register. The match can be qualified by the access data and by the access type (read/write). The breakpoint occurs a maximum of 2 instructions after the access in the CPU flow.
Page 208: State Sequence Control
Chapter 6 S12Z Debug (S12ZDBGV2) Module Table 6-45. Event Priorities TRIG Force immediately to final state DBGEEV Force to next state as defined by state control registers (EEVE=2’b10) Match3 Force to next state as defined by state control registers Match2 Force to next state as defined by state control registers Match1 Force to next state as defined by state control registers...
Page 209: Trace Buffer Operation
Chapter 6 S12Z Debug (S12ZDBGV2) Module 6.4.5 Trace Buffer Operation The trace buffer is a 64 lines deep by 64-bits wide RAM array. If the TSOURCE bit is set the DBG module can store trace information in the RAM array in a circular buffer format. Data is stored in mode dependent formats, as described in the following sections.
Page 210 Chapter 6 S12Z Debug (S12ZDBGV2) Module Using Begin-Alignment together with opcode address comparisons, if the instruction is about to be executed then the trace is started. If the trigger is at the address of a COF instruction, whilst tracing COF addresses, then that COF address is stored to the trace buffer.
Page 211 Chapter 6 S12Z Debug (S12ZDBGV2) Module NOTE When a CPU indexed jump instruction is executed, the destination address is stored to the trace buffer on instruction completion, indicating the COF has taken place. If an interrupt occurs simultaneously then the next instruction carried out is actually from the interrupt service routine.
Page 212 Chapter 6 S12Z Debug (S12ZDBGV2) Module Table 6-47. Normal and Loop1 Mode Trace Buffer Format without Timestamp CINF1 CPCH1 CPCM1 CPCL1 CINF0 CPCH0 CPCM0 CPCL0 CINF3 CPCH3 CPCM3 CPCL3 CINF2 CPCH2 CPCM2 CPCL2 Table 6-48. Normal and Loop1 Mode Trace Buffer Format with Timestamp 8-Byte Wide Trace Buffer Line Mode Timestamp...
Page 213 Chapter 6 S12Z Debug (S12ZDBGV2) Module 6.4.5.2.2 Loop1 Mode Loop1 Mode, similarly to Normal Mode also stores only COF address information to the trace buffer, it however allows the filtering out of redundant information. The intent of Loop1 Mode is to prevent the trace buffer from being filled entirely with duplicate information from a looping construct such as delays using the DBNE instruction.
Page 214 Chapter 6 S12Z Debug (S12ZDBGV2) Module Table 6-52. Detail Mode Trace Buffer Format with Timestamp 8-Byte Wide Trace Buffer Line Mode CDATA31 CDATA21 CDATA11 CDATA01 CINF1 CADRH1 CADRM1 CADRL1 Detail Timestamp Timestamp Reserved Reserved TSINF1 CPCH1 CPCM1 CPCL1 CDATA32 CDATA22 CDATA12 CDATA02 CINF2...
Page 215 Chapter 6 S12Z Debug (S12ZDBGV2) Module TSINF provides information about a timestamp. Bit1 indicates if the byte is a TSINF byte. Table 6-54. CINF Field Descriptions Field Description 7–6 Access Type Indicator — This field indicates the CPU access size. 00 8-bit Access 0116-bit Access 10 24-bit Access...
Page 216 Chapter 6 S12Z Debug (S12ZDBGV2) Module in bytes[6:4], the other payload bytes may be compressed or complete addresses as indicated by the info byte bits. Table 6-56. Pure PC Mode Trace Buffer Format Single Source 8-Byte Wide Trace Buffer Line Mode CXINF BASE...
Page 217 Chapter 6 S12Z Debug (S12ZDBGV2) Module The number of core clock cycles since the last entry equals the timestamp + 1. The core clock runs at twice the frequency of the bus clock. The timestamp of the first trace buffer entry is 0x0000. With timestamps enabled trace buffer entries are initiated in the following ways: •...
Page 218: Code Profiling
Chapter 6 S12Z Debug (S12ZDBGV2) Module pointer is initialized by each aligned write to DBGTB to point to the oldest data again. This enables an interrupted trace buffer read sequence to be easily restarted from the oldest data entry. After reading all trace buffer lines, the next read wraps around and returns the contents of line0.
Page 219 Chapter 6 S12Z Debug (S12ZDBGV2) Module Figure 6-31 shows the profiling clock, PDOCLK, whose edges are offset from the bus clock, to ease setup and hold time requirements relative to PDO, which is synchronous to the bus clock. Figure 6-31. PDO Profiling Clock Control STROBE BUS CLOCK CLOCK ENABLE...
Page 220 Chapter 6 S12Z Debug (S12ZDBGV2) Module 6.4.6.3 Code Profiling Internal Data Storage Format When profiling starts, the first trace buffer entry is made to provide the start address. This uses a 4 byte format (PTS), including the INFO byte and a 3-byte PC start address. In order to avoid trace buffer overflow a fully compressed format is used for direct (conditional branch) COF information.
Page 221 Chapter 6 S12Z Debug (S12ZDBGV2) Module transmission of the INFO byte starts when a line is complete. Whole bytes are always transmitted. The grey shaded bytes of Table 6-58 are not transmitted. Figure 6-32. INFO byte encoding TSOVF TBOVF TERM Line Format Table 6-59.
Page 222: Breakpoints
Chapter 6 S12Z Debug (S12ZDBGV2) Module Line Byte4 Byte3 Byte2 Byte1 Line0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 0 0 1 0 0 0 0 1 1 0 0 0 0 1 1 0 Line1 0 1 1 0 0 1 0 1 1 0 0 1 0 0 1 0 1 1 0 0 1 0 0 1 0 1 1 0 0 1 0 0 Line2...
Page 223: Application Information
Chapter 6 S12Z Debug (S12ZDBGV2) Module 6.4.7.3.1 DBG Breakpoint Priorities And BDC Interfacing Breakpoint operation is dependent on the state of the S12ZBDC module. BDM cannot be entered from a breakpoint unless the BDC is enabled (ENBDC bit is set in the BDC). If BDM is already active, breakpoints are disabled.
Page 224: Breakpoints From Other S12Z Sources
Chapter 6 S12Z Debug (S12ZDBGV2) Module • When a reset occurs the debugger pulls BKGD low until the reset ends, forcing SSC mode entry. • Then the debugger reads the reset flags to determine the cause of reset. • If required, the debugger can read the trace buffer to see what happened just before reset. Since the trace buffer and DBGCNT register are not affected by resets other than POR.
Page 225: Introduction
Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) Table 7-1. Revision History Rev. No. Date Sections Affected Substantial Change(s) (Item No) (Submitted By) • corrected bit numbering for CSAD Bit changed to f • f PLLRST VCORST 21 Aug. 2013 V06.04 •...
Page 226: Features
Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) 7.1.1 Features The Pierce Oscillator (XOSCLCP) contains circuitry to dynamically control current gain in the output amplitude. This ensures a signal with low harmonic distortion, low power and good noise immunity. •...
Page 227 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) • Frequency trimming (A factory trim value for 1MHz is loaded from Flash Memory into the IRCTRIM register after reset, which can be overwritten by application if required) • Temperature Coefficient (TC) trimming. (A factory trim value is loaded from Flash Memory into the IRCTRIM register to turn off TC trimming after reset.
Page 228: Modes Of Operation
Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) 7.1.2 Modes of Operation This subsection lists and briefly describes all operating modes supported by the S12CPMU_UHV_V6. 7.1.2.1 Run Mode The voltage regulator is in Full Performance Mode (FPM). NOTE The voltage regulator is active, providing the nominal supply voltages with full current sourcing capability (see also Appendix for VREG electrical parameters).
Page 229 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) – Enable the external oscillator (OSCE bit). – Wait for oscillator to start up (UPOSC=1). – Select the Oscillator Clock (OSCCLK) as source of the Bus Clock (PLLSEL=0). — The PLLCLK is on and used to qualify the external oscillator clock. 7.1.2.2 Wait Mode For S12CPMU_UHV_V6 Wait Mode is the same as Run Mode.
Page 230 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) Mode. For this COP configuration (ACLK clock source, CSAD set) a latency time (please refer to CSAD bit description for details) occurs when entering or exiting (Full, Pseudo) Stop Mode. When bit CSAD is clear the ACLK clock source is on for the COP during Full Stop Mode and COP is operating.
Page 231: S12Cpmu_Uhv_V6 Block Diagram
Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) 7.1.3 S12CPMU_UHV_V6 Block Diagram VSUP vsup monitor VDDA Low Voltage Detect VDDA Low Voltage Interrupt LVDS LVIE VSSA Low Voltage Detect Voltage VDDX VDDX, VDD, VDDF Regulator LVRF VSSX 6V to 18V Power-On Detect S12CPMU_UHV (VREGAUTO)
Page 232 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) Figure 7-2 shows a block diagram of the XOSCLCP. OSCMOD Clock monitor fail Monitor OSCCLK Peak Gain Control Detector VDD=1.8V Quartz Crystals XTAL EXTAL Ceramic Resonators Figure 7-2. XOSCLCP Block Diagram S12ZVH Family Reference Manual, Rev.
Page 233: Signal Description
Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) Signal Description This section lists and describes the signals that connect off chip as well as internal supply nodes and special signals. 7.2.1 RESET Pin RESET is an active-low bidirectional pin. As an input it initializes the MCU asynchronously to a known start-up state.
Page 234: Bctl— Base Control Pin For External Pnp
Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) This supply domain is monitored by the Low Voltage Reset circuit. VDDX has to be connected externally to VDDA. 7.2.6 BCTL— Base Control Pin for external PNP BCTL is the ballast connection for the on chip voltage regulator. It provides the base current of an external BJT (PNP) of the VDDX and VDDA supplies.
Page 235: Tempsense — Internal Temperature Sensor Output Voltage
Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) 7.2.12 TEMPSENSE — Internal Temperature Sensor Output Voltage Depending on the VSEL setting either the voltage level generated by the temperature sensor or the VREG bandgap voltage is driven to a special channel input of the ADC Converter. See device level specification for connectivity of ADC special channels.
Page 236: Memory Map And Registers
Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) Memory Map and Registers This section provides a detailed description of all registers accessible in the S12CPMU_UHV_V6. 7.3.1 Module Memory Map The S12CPMU_UHV_V6 registers are shown in Figure 7-3. Address Register Bit 7 Bit 0...
Page 237 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) Address Register Bit 7 Bit 0 Offset Name CPMU 0x000F ARMCOP Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HTDS CPMU 0x0010 VSEL HTIE HTIF...
Page 238: Register Descriptions
Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) 7.3.2 Register Descriptions This section describes all the S12CPMU_UHV_V6 registers and their individual bits. Address order is as listed in Figure 7-3 7.3.2.1 S12CPMU_UHV_V6 Reset Flags Register (CPMURFLG) This register provides S12CPMU_UHV_V6 reset flags. Module Base + 0x0003 PORF LVRF...
Page 239 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) Table 7-2. CPMURFLG Field Descriptions (continued) Field Description Oscillator Clock Monitor Reset Flag — OMRF is set to 1 when a loss of oscillator (crystal) clock occurs. Refer OMRF to7.5.3, “Oscillator Clock Monitor Reset for details.This flag can only be cleared by writing a 1.
Page 240 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) frequency as shown in Table 7-3. Setting the VCOFRQ[1:0] bits incorrectly can result in a non functional PLL (no locking and/or insufficient stability). Table 7-3. VCO Clock Frequency Selection VCOCLK Frequency Ranges VCOFRQ[1:0] 32MHz <= f <= 48MHz...
Page 241 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) Table 7-4. Reference Clock Frequency Selection if OSC_LCP is enabled REFCLK Frequency Ranges REFFRQ[1:0] (OSCE=1) 1MHz <= f <= 2MHz 2MHz < f <= 6MHz 6MHz < f <= 12MHz >12MHz S12ZVH Family Reference Manual, Rev.
Page 242 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) 7.3.2.4 S12CPMU_UHV_V6 Post Divider Register (CPMUPOSTDIV) The POSTDIV register controls the frequency ratio between the VCOCLK and the PLLCLK. Module Base + 0x0006 POSTDIV[4:0] Reset = Unimplemented or Reserved Figure 7-7. S12CPMU_UHV_V6 Post Divider Register (CPMUPOSTDIV) Read: Anytime Write: If PLLSEL=1 write anytime, else write has no effect f VCO...
Page 243 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) Module Base + 0x0007 LOCK UPOSC RTIF LOCKIF OSCIF Reset = Unimplemented or Reserved Figure 7-8. S12CPMU_UHV_V6 Flags Register (CPMUIFLG) Read: Anytime Write: Refer to each bit for individual write conditions Table 7-5.
Page 244 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) 7.3.2.6 S12CPMU_UHV_V6 Interrupt Enable Register (CPMUINT) This register enables S12CPMU_UHV_V6 interrupt requests. Module Base + 0x0008 RTIE LOCKIE OSCIE Reset = Unimplemented or Reserved Figure 7-9. S12CPMU_UHV_V6 Interrupt Enable Register (CPMUINT) Read: Anytime Write: Anytime Table 7-6.
Page 245 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) 7.3.2.7 S12CPMU_UHV_V6 Clock Select Register (CPMUCLKS) This register controls S12CPMU_UHV_V6 clock selection. Module Base + 0x0009 PLLSEL PSTP CSAD OSCSEL1 OSCSEL OSCSEL0 Reset = Unimplemented or Reserved Figure 7-10. S12CPMU_UHV_V6 Clock Select Register (CPMUCLKS) Read: Anytime Write: •...
Page 246 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) Table 7-7. CPMUCLKS Descriptions Field Description PLL Select Bit PLLSEL This bit selects the PLLCLK as source of the System Clocks (Core Clock and Bus Clock). PLLSEL can only be set to 0, if UPOSC=1. UPOSC= 0 sets the PLLSEL bit.
Page 247 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) Table 7-7. CPMUCLKS Descriptions (continued) Field Description RTI Clock Select— RTIOSCSEL selects the clock source to the RTI. Either IRCCLK or OSCCLK. Changing the RTIOSCSEL RTIOSCSEL bit re-starts the RTI time-out period. RTIOSCSEL can only be set to 1, if UPOSC=1.
Page 248 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) 7.3.2.8 S12CPMU_UHV_V6 PLL Control Register (CPMUPLL) This register controls the PLL functionality. Module Base + 0x000A Reset Figure 7-11. S12CPMU_UHV_V6 PLL Control Register (CPMUPLL) Read: Anytime Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has no effect.
Page 249 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) 7.3.2.9 S12CPMU_UHV_V6 RTI Control Register (CPMURTI) This register selects the time-out period for the Real Time Interrupt. The clock source for the RTI is either IRCCLK or OSCCLK depending on the setting of the RTIOSCSEL bit.
Page 250 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) Table 7-12. RTI Frequency Divide Rates for RTDEC = 0 RTR[6:4] = RTR[3:0] (OFF) 0000 (1) 0001 (2) 0010 (3) 0011 (4) 0100 (5) 0101 (6) 0110 (7) 0111 (8) 1000 (9) 10x2 10x2...
Page 251 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) Table 7-13. RTI Frequency Divide Rates for RTDEC=1 RTR[6:4] = RTR[3:0] (1x10 (2x10 (5x10 (10x10 (20x10 (50x10 (100x10 (200x10 1x10 2x10 5x10 10x10 20x10 50x10 100x10 200x10 0000 (1) 2x10 4x10 10x10 20x10...
Page 252 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) 7.3.2.10 S12CPMU_UHV_V6 COP Control Register (CPMUCOP) This register controls the COP (Computer Operating Properly) watchdog. The clock source for the COP is either ACLK, IRCCLK or OSCCLK depending on the setting of the COPOSCSEL0 and COPOSCSEL1 bit (see also Table 7-8).
Page 253 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) Table 7-14. CPMUCOP Field Descriptions Field Description Window COP Mode Bit — When set, a write to the CPMUARMCOP register must occur in the last 25% of the WCOP selected period. A write during the first 75% of the selected period generates a COP reset. As long as all writes occur during this window, $55 can be written as often as desired.
Page 254 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) Table 7-16. COP Watchdog Rates if COPOSCSEL1=1. COPCLK Cycles to time-out (COPCLK is ACLK divided by 2) COP disabled S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 255 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) 7.3.2.11 Reserved Register CPMUTEST0 NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in Special Mode can alter the S12CPMU_UHV_V6’s functionality.
Page 256 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) 7.3.2.13 S12CPMU_UHV_V6 COP Timer Arm/Reset Register (CPMUARMCOP) This register is used to restart the COP time-out period. Module Base + 0x000F W ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit Reset Figure 7-16.
Page 257 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) Table 7-17. CPMUHTCTL Field Descriptions Field Description Voltage Access Select Bit — If set, the bandgap reference voltage V can be accessed internally (i.e. VSEL multiplexed to an internal Analog to Digital Converter channel). If not set, the die temperature proportional voltage V of the temperature sensor can be accessed internally.
Page 258 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) 7.3.2.15 Low Voltage Control Register (CPMULVCTL) The CPMULVCTL register allows the configuration of the low-voltage detect features. Module Base + 0x0011 LVDS LVIE LVIF Reset The Reset state of LVDS and LVIF depends on the external supplied VDDA level = Unimplemented or Reserved Figure 7-19.
Page 259 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) 7.3.2.16 Autonomous Periodical Interrupt Control Register (CPMUAPICTL) The CPMUAPICTL register allows the configuration of the autonomous periodical interrupt features. Module Base + 0x0012 APICLK APIES APIEA APIFE APIE APIF Reset = Unimplemented or Reserved Figure 7-20.
Page 260 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) Figure 7-21. Waveform selected on API_EXTCLK pin (APIEA=1, APIFE=1) API min. period / 2 APIES=0 API period APIES=1 S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 261 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) 7.3.2.17 Autonomous Clock Trimming Register (CPMUACLKTR) The CPMUACLKTR register configures the trimming of the Autonomous Clock (ACLK - trimmable internal RC-Oscillator) which can be selected as clock source for some CPMU features Module Base + 0x0013 ACLKTR5 ACLKTR4...
Page 262 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) 7.3.2.18 Autonomous Periodical Interrupt Rate High and Low Register (CPMUAPIRH / CPMUAPIRL) The CPMUAPIRH and CPMUAPIRL registers allow the configuration of the autonomous periodical interrupt rate. Module Base + 0x0014 APIR15 APIR14 APIR13...
Page 263 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) Table 7-23. Selectable Autonomous Periodical Interrupt Periods APICLK APIR[15:0] Selected Period 0000 0.2 ms 0001 0.4 ms 0002 0.6 ms 0003 0.8 ms 0004 1.0 ms 0005 1.2 ms ..
Page 264 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) CPMUTEST3 7.3.2.19 Reserved Register NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in Special Mode can alter the S12CPMU_UHV_V6’s functionality.
Page 265 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) 7.3.2.20 High Temperature Trimming Register (CPMUHTTR) The CPMUHTTR register configures the trimming of the S12CPMU_UHV_V6 temperature sense. Module Base + 0x0017 HTOE HTTR3 HTTR2 HTTR1 HTTR0 Reset After de-assert of System Reset a trim value is automatically loaded from the Flash memory. See Device specification for details.
Page 266 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) 7.3.2.21 S12CPMU_UHV_V6 IRC1M Trim Registers (CPMUIRCTRIMH / CPMUIRCTRIML) Module Base + 0x0018 TCTRIM[4:0] IRCTRIM[9:8] Reset After de-assert of System Reset a factory programmed trim value is automatically loaded from the Flash memory to provide trimmed Internal Reference Frequency f IRC1M_TRIM Figure 7-27.
Page 267 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) IRC1M frequency (IRCCLK) IRCTRIM[9:6] 1.5MHz ..IRCTRIM[5:0] 1MHz 600KHz IRCTRIM[9:0] $000 $3FF Figure 7-29. IRC1M Frequency Trimming Diagram S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 268 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) frequency 0x11111 0x10101 0x10100 TC increases 0x10011 0x10010 0x10001 TCTRIM[4:0] = 0x10000 or 0x00000 (nominal TC) 0x00001 0x00010 0x00011 TC decreases 0x00100 0x00101 0x01111 150C - 40C temperature Figure 7-30. Influence of TCTRIM[4:0] on the Temperature Coefficient NOTE The frequency is not necessarily linear with the temperature (in most cases it will not be).
Page 269 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) Table 7-28. TC trimming of the frequency of the IRC1M at ambient temperature IRC1M Indicative IRC1M indicative frequency drift for relative TCTRIM[4:0] relative TC variation TC variation 00000 0 (nominal TC of the IRC) 00001 -0.27% -0.5%...
Page 270 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) Be aware that the output frequency varies with the TC trimming. A frequency trimming correction is therefore necessary. The values provided Table 7-28 are typical values at ambient temperature which can vary from device to device.
Page 271 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) Table 7-29. CPMUOSC Field Descriptions Field Description Oscillator Enable Bit — This bit enables the external oscillator (XOSCLCP). The UPOSC status bit in the OSCE CPMIUFLG register indicates when the oscillation is stable and when OSCCLK can be selected as source of the Bus Clock or source of the COP or RTI.If the oscillator clock monitor reset is enabled (OMRE = 1 in CPMUOSC2 register), then a loss of oscillation will lead to an oscillator clock monitor reset.
Page 272 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) 7.3.2.23 S12CPMU_UHV_V6 Protection Register (CPMUPROT) This register protects the clock configuration registers from accidental overwrite: CPMUSYNR, CPMUREFDIV, CPMUCLKS, CPMUPLL, CPMUIRCTRIMH/L, CPMUOSC and CPMUOSC2 Module Base + 0x001B PROT Reset Figure 7-32. S12CPMU_UHV_V6 Protection Register (CPMUPROT) Read: Anytime Write: Anytime Field...
Page 273 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) CPMUTEST2 7.3.2.24 Reserved Register NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in Special Mode can alter the S12CPMU_UHV_V6’s functionality.
Page 274 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) 7.3.2.25 Voltage Regulator Control Register (CPMUVREGCTL) The CPMUVREGCTL allows to enable or disable certain parts of the voltage regulator.This register must be configured after system startup. Module Base + 0x001D EXTCON EXTXON INTXON...
Page 275 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) 7.3.2.26 S12CPMU_UHV_V6 Oscillator Register 2 (CPMUOSC2) This registers configures the external oscillator (XOSCLCP). Module Base + 0x001E OMRE OSCMOD Reset Figure 7-35. S12CPMU_UHV_V6 Oscillator Register 2 (CPMUOSC2) Read: Anytime Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has no effect.
Page 276: Functional Description
Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) Functional Description 7.4.1 Phase Locked Loop with Internal Filter (PLL) The PLL is used to generate a high speed PLLCLK based on a low frequency REFCLK. The REFCLK is by default the IRCCLK which is trimmed to f =1MHz.
Page 277 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) Several examples of PLL divider settings are shown in Table 7-33. The following rules help to achieve optimum stability and shortest lock time: • Use lowest possible f ratio (SYNDIV value). •...
Page 278: Startup From Reset
Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) 7.4.2 Startup from Reset An example for startup of the clock system from Reset is given in Figure 7-36. Figure 7-36. Startup of clock system after Reset 256 cycles VCORST RESET 512 cycles VCORST...
Page 279: Stop Mode Using Pllclk As Source Of The Bus Clock
Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) 7.4.3 Stop Mode using PLLCLK as source of the Bus Clock An example of what happens going into Stop Mode and exiting Stop Mode after an interrupt is shown in Figure 7-37.
Page 280 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) Figure 7-38. Full Stop Mode using Oscillator Clock as source of the Bus Clock wake up interrupt continue execution execution STOP instruction Core STP_REC Clock lock PLLCLK crystal/resonator starts oscillating OSCCLK UPOSC UPOSC...
Page 281: External Oscillator
Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) 7.4.5 External Oscillator 7.4.5.1 Enabling the External Oscillator An example of how to use the oscillator as source of the Bus Clock is shown in Figure 7-39. Figure 7-39. Enabling the external oscillator enable external oscillator by writing OSCE bit to one.
Page 282: System Clock Configurations
Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) 7.4.6 System Clock Configurations 7.4.6.1 PLL Engaged Internal Mode (PEI) This mode is the default mode after System Reset or Power-On Reset. The Bus Clock is based on the PLLCLK, the reference clock for the PLL is internally generated (IRC1M). The PLL is configured to 50 MHz VCOCLK with POSTDIV set to 0x03.
Page 283: Resets
Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) 7.4.6.3 PLL Bypassed External Mode (PBE) In this mode, the Bus Clock is based on the external oscillator clock. The reference clock for the PLL is based on the external oscillator. The clock sources for COP and RTI can be based on the internal reference clock generator or on the external oscillator clock or the RC-Oscillator (ACLK).
Page 284: Description Of Reset Operation
Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) Table 7-34. Reset Summary Reset Source Local Enable Oscillator Clock Monitor Reset OSCE Bit in CPMUOSC register and OMRE Bit in CPMUOSC2 register COP Reset CR[2:0] in CPMUCOP register 7.5.2 Description of Reset Operation Upon detection of any reset of Table...
Page 285: Pll Clock Monitor Reset
Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) 7.5.4 PLL Clock Monitor Reset In case of loss of PLL clock oscillation or the PLL clock frequency is below the failure assert frequency (see device electrical characteristics for values), the S12CPMU_UHV_V6 generates a PLL Clock PMFA Monitor Reset.
Page 286: Power-On Reset (Por)
Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) Three control bits in the CPMUCOP register allow selection of seven COP time-out periods. When COP is enabled, the program must write $55 and $AA (in this order) to the CPMUARMCOP register during the selected time-out period.
Page 287: Interrupts
Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) Interrupts The interrupt vectors requested by the S12CPMU_UHV_V6 are listed in Table 7-36. Refer to MCU specification for related vector addresses and priorities. Table 7-36. S12CPMU_UHV_V6 Interrupt Vectors Interrupt Source Local Enable Mask RTI time-out interrupt...
Page 288 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) Upon detection of a status change (UPOSC) the OSCIF flag is set. Going into Full Stop Mode or disabling the oscillator can also cause a status change of UPOSC. Any change in PLL configuration or any other event which causes the PLL lock status to be cleared leads to a loss of the oscillator status information as well (UPOSC=0).
Page 289: Initialization/Application Information
Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) NOTE The first period after enabling the counter by APIFE might be reduced by API start up delay t sdel It is possible to generate with the API a waveform at the external pin API_EXTCLK by setting APIFE and enabling the external access with setting APIEA.
Page 290 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) /* Procedure proposed by to setup PLL and Oscillator */ /* example for OSC = 4 MHz and Bus Clock = 25MHz, That is VCOCLK = 50MHz */ /* Initialize */ /* PLL Clock = 50 MHz, divide by one */ CPMUPOSTDIV = 0x00;...
Page 291: Introduction
Chapter 8 Timer Module (TIM16B8CV3) Block Description Table 8-1. V03.02 Apri,12,2010 8.3.2.8/8-302 -Add Table 8-10 8.3.2.11/8-305 -update TCRE bit description 8.4.3/8-314 -add Figure 8-31 V03.03 Jan,14,2013 -single source generate different channel guide Introduction The basic scalable timer consists of a 16-bit, software-programmable counter driven by a flexible programmable prescaler.
Page 292: S12Zvh Family Reference Manual, Rev. 1.05 Freescale Semiconductor
Chapter 8 Timer Module (TIM16B8CV3) Block Description 8.1.2 Modes of Operation Stop: Timer is off because clocks are stopped. Freeze: Timer counter keeps on running, unless TSFRZ in TSCR1 is set to 1. Wait: Counters keeps on running, unless TSWAI in TSCR1 is set to 1. Normal: Timer counter keep on running, unless TEN in TSCR1 is cleared to 0.
Page 293 Chapter 8 Timer Module (TIM16B8CV3) Block Description Channel 0 Input capture Prescaler Bus clock IOC0 Output compare Channel 1 Input capture 16-bit Counter IOC1 Output compare Channel 2 Timer overflow Input capture interrupt IOC2 Output compare Timer channel 0 Channel 3 interrupt Input capture IOC3...
Page 294 Chapter 8 Timer Module (TIM16B8CV3) Block Description TIMCLK (Timer clock) CLK1 4:1 MUX CLK0 Clock select Prescaled clock (PCLK) (PAMOD) Edge detector IOC7 Interrupt PACNT Divide by 64 M clock Figure 8-2. 16-Bit Pulse Accumulator Block Diagram 16-bit Main Timer IOCn Edge detector Set CnF Interrupt...
Page 295: External Signal Description
Chapter 8 Timer Module (TIM16B8CV3) Block Description PULSE ACCUMULATOR CHANNEL 7 OUTPUT COMPARE OCPD TIOS7 Figure 8-4. Channel 7 Output Compare/Pulse Accumulator Logic External Signal Description The TIM16B8CV3 module has a selected number of external pins. Refer to device specification for exact number.
Page 296: Register Descriptions
Chapter 8 Timer Module (TIM16B8CV3) Block Description 8.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
Page 297 Chapter 8 Timer Module (TIM16B8CV3) Block Description Register Bit 7 Bit 0 Name 0x0021 PAOVF PAIF PAFLG 0x0022 PACNT15 PACNT14 PACNT13 PACNT12 PACNT11 PACNT10 PACNT9 PACNT8 PACNTH 0x0023 PACNT7 PACNT6 PACNT5 PACNT4 PACNT3 PACNT2 PACNT1 PACNT0 PACNTL 0x0024–0x002B Reserved 0x002C OCPD7 OCPD6 OCPD5...
Page 298 Chapter 8 Timer Module (TIM16B8CV3) Block Description 8.3.2.2 Timer Compare Force Register (CFORC) FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0 Reset Figure 8-7. Timer Compare Force Register (CFORC) Read: Anytime but will always return 0x0000 (1 state is transient) Write: Anytime Table 8-3.
Page 299 Chapter 8 Timer Module (TIM16B8CV3) Block Description Table 8-4. OC7M Field Descriptions Field Description Output Compare 7 Mask — A channel 7 event, which can be a counter overflow when TTOV[7] is set or a OC7M[7:0] successful output compare on channel 7, overrides any channel 6:0 compares. For each OC7M bit that is set, the output compare action reflects the corresponding OC7D bit.
Page 300 Chapter 8 Timer Module (TIM16B8CV3) Block Description TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 Reset Figure 8-11. Timer Count Register Low (TCNTL) The 16-bit main timer is an up counter. A full access for the counter register should take place in one clock cycle. A separate read/write for high byte and low byte will give a different result than accessing them as a word.
Page 301 Chapter 8 Timer Module (TIM16B8CV3) Block Description Table 8-6. TSCR1 Field Descriptions (continued) Field Description Timer Stops While in Freeze Mode TSFRZ 0 Allows the timer counter to continue running while in freeze mode. 1 Disables the timer counter whenever the MCU is in freeze mode. This is useful for emulation. TSFRZ does not stop the pulse accumulator.
Page 302 Chapter 8 Timer Module (TIM16B8CV3) Block Description 8.3.2.8 Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2) Reset Figure 8-14. Timer Control Register 1 (TCTL1) Reset Figure 8-15. Timer Control Register 2 (TCTL2) Read: Anytime Write: Anytime Table 8-8. TCTL1/TCTL2 Field Descriptions Note: Writing to unavailable bits has no effect.
Page 303 Chapter 8 Timer Module (TIM16B8CV3) Block Description Table 8-10. The OC7 and OCx event priority OC7M7=0 OC7M7=1 OC7Mx=1 OC7Mx=0 OC7Mx=1 OC7Mx=0 TC7=TCx TC7>TCx TC7=TCx TC7>TCx TC7=TCx TC7>TCx TC7=TCx TC7>TCx IOCx=OC7Dx IOCx=OC7Dx IOCx=OMx/OLx IOCx=OC7Dx IOCx=OC7Dx IOCx=OMx/OLx IOC7=OM7/O +OMx/OLx IOC7=OM7/OL7 IOC7=OC7D7 +OMx/OLx IOC7=OC7D7 IOC7=OM7/O IOC7=OC7D7...
Page 304 Chapter 8 Timer Module (TIM16B8CV3) Block Description Table 8-11. TCTL3/TCTL4 Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero. Field Description Input Capture Edge Control — These eight pairs of control bits configure the input capture edge detector EDGnB circuits.
Page 305 Chapter 8 Timer Module (TIM16B8CV3) Block Description 8.3.2.11 Timer System Control Register 2 (TSCR2) TCRE Reset = Unimplemented or Reserved Figure 8-19. Timer System Control Register 2 (TSCR2) Read: Anytime Write: Anytime. Table 8-14. TSCR2 Field Descriptions Field Description Timer Overflow Interrupt Enable 0 Interrupt inhibited.
Page 306 Chapter 8 Timer Module (TIM16B8CV3) Block Description NOTE The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero. 8.3.2.12 Main Timer Interrupt Flag 1 (TFLG1) Reset Figure 8-20. Main Timer Interrupt Flag 1 (TFLG1) Read: Anytime Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared).
Page 307 Chapter 8 Timer Module (TIM16B8CV3) Block Description Table 8-17. TRLG2 Field Descriptions Field Description Timer Overflow Flag — Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000. Clearing this bit requires writing a one to bit 7 of TFLG2 register while the TEN bit of TSCR1 or PAEN bit of PACTL is set to one (See also TCRE control bit explanation) .
Page 308 Chapter 8 Timer Module (TIM16B8CV3) Block Description 8.3.2.15 16-Bit Pulse Accumulator Control Register (PACTL) Module Base + 0x0020 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI Reset Unimplemented or Reserved Figure 8-24. 16-Bit Pulse Accumulator Control Register (PACTL) Read: Any time Write: Any time When PAEN is set, the Pulse Accumulator counter is enabled.
Page 309 Chapter 8 Timer Module (TIM16B8CV3) Block Description Table 8-19. Pin Action PAMOD PEDGE Pin Action Falling edge Rising edge Div. by 64 clock enabled with pin high level Div. by 64 clock enabled with pin low level NOTE If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64 because the 64 clock is generated by the timer prescaler.
Page 310 Chapter 8 Timer Module (TIM16B8CV3) Block Description Table 8-21. PAFLG Field Descriptions Field Description Pulse Accumulator Overflow Flag — Set when the 16-bit pulse accumulator overflows from 0xFFFF to 0x0000. PAOVF Clearing this bit requires writing a one to this bit in the PAFLG register while TEN bit of TSCR1 or PAEN bit of PACTL register is set to one.
Page 311 Chapter 8 Timer Module (TIM16B8CV3) Block Description 8.3.2.18 Output Compare Pin Disconnect Register(OCPD) OCPD7 OCPD6 OCPD5 OCPD4 OCPD3 OCPD2 OCPD1 OCPD0 Reset Figure 8-28. Output Compare Pin Disconnect Register (OCPD) Read: Anytime Write: Anytime All bits reset to zero. Table 8-22. OCPD Field Description Note: Writing to unavailable bits has no effect.
Page 312: Functional Description
Chapter 8 Timer Module (TIM16B8CV3) Block Description Table 8-23. PTPSR Field Descriptions Field Description Precision Timer Prescaler Select Bits — These eight bits specify the division rate of the main Timer prescaler. PTPS[7:0] These are effective only when the PRNT bit of TSCR1 is set to 1. Table 8-24 shows some selection examples in this case.
Page 313 Chapter 8 Timer Module (TIM16B8CV3) Block Description PTPSR[7:0] CLK[1:0] PACLK PRE-PRESCALER PACLK/256 PACLK/65536 channel 7 output PR[2:1:0] compare TCRE PRESCALER TCNT(hi):TCNT(lo) CLEAR COUNTER 16-BIT COUNTER INTERRUPT LOGIC CHANNEL 0 16-BIT COMPARATOR CH. 0 CAPTURE OM:OL0 IOC0 PIN IOC0 PIN TOV0 LOGIC CH.
Page 314: Prescaler
Chapter 8 Timer Module (TIM16B8CV3) Block Description 8.4.1 Prescaler The prescaler divides the Bus clock by 1, 2, 4, 8, 16, 32, 64 or 128. The prescaler select bits, PR[2:0], select the prescaler divisor. PR[2:0] are in timer system control register 2 (TSCR2). The prescaler divides the Bus clock by a prescalar value.
Page 315: Pulse Accumulator
Chapter 8 Timer Module (TIM16B8CV3) Block Description Writing to the timer port bit of an output compare pin does not affect the pin state. The value written is stored in an internal latch. When the pin becomes available for general-purpose output, the last value written to the bit appears at the pin.
Page 316: Event Counter Mode
Chapter 8 Timer Module (TIM16B8CV3) Block Description 8.4.5 Event Counter Mode Clearing the PAMOD bit configures the PACNT for event counter operation. An active edge on the IOC7 pin increments the pulse accumulator counter. The PEDGE bit selects falling edges or rising edges to increment the count.
Page 317: Channel [7:0] Interrupt (C[7:0]F)
Chapter 8 Timer Module (TIM16B8CV3) Block Description TIM16B8CV3 Table 8-25. Interrupts Interrupt Offset Vector Priority Source Description C[7:0]F — — — Timer Channel 7–0 Active high timer channel interrupts 7–0 PAOVI — — — Pulse Accumulator Active high pulse accumulator input interrupt Input PAOVF —...
Page 318 Chapter 8 Timer Module (TIM16B8CV3) Block Description S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 319: Introduction
Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2) Table 9-1. Revision History Revision Sections Revision Date Description of Changes Number Affected v02.00 Feb. 20, 2009 Initial revision of scalable PWM. Started from pwm_8b8c (v01.08). Introduction The Version 2 of S12 PWM module is a channel scalable and optimized implementation of S12 PWM8B8C Version 1.
Page 320: Block Diagram
Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2) In freeze mode there is a software programmable option to disable the input clock to the prescaler. This is useful for emulation. Wait: The prescaler keeps on running, unless PSWAI in PWMCTL is set to 1. Freeze: The prescaler keeps on running, unless PFRZ in PWMCTL is set to 1.
Page 321: Pwm7 - Pwm0 — Pwm Channel 7 - 0
Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2) 9.2.1 PWM7 - PWM0 — PWM Channel 7 - 0 Those pins serve as waveform output of PWM channel 7 - 0. Memory Map and Register Definition 9.3.1 Module Memory Map This section describes the content of the registers in the scalable PWM module. The base address of the scalable PWM module is determined at the MCU level when the MCU is defined.
Page 322 Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2) Register Bit 7 Bit 0 Name 0x0006 PWMCLKAB PCLKAB7 PCLKAB6 PCLKAB5 PCLKAB4 PCLKAB3 PCLKAB2 PCLKAB1 PCLKAB0 0x0007 RESERVED 0x0008 Bit 7 Bit 0 PWMSCLA 0x0009 Bit 7 Bit 0 PWMSCLB 0x000A RESERVED 0x000B RESERVED 0x000C Bit 7 Bit 0 PWMCNT0...
Page 323 Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2) Register Bit 7 Bit 0 Name 0x0014 Bit 7 Bit 0 PWMPER0 0x0015 Bit 7 Bit 0 PWMPER1 0x0016 Bit 7 Bit 0 PWMPER2 0x0017 Bit 7 Bit 0 PWMPER3 0x0018 Bit 7 Bit 0 PWMPER4 0x0019 Bit 7...
Page 324 Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2) Register Bit 7 Bit 0 Name 0x0023 Bit 7 Bit 0 PWMDTY7 0x0024 RESERVED 0x0025 RESERVED 0x0026 RESERVED 0x0027 RESERVED = Unimplemented or Reserved Figure 9-2. The scalable PWM Register Summary (Sheet 4 of 4) 1.
Page 325 Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2) Table 9-2. PWME Field Descriptions Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from unavailable bits return a zero Field Description Pulse Width Channel 7 Enable PWME7 0 Pulse width channel 7 is disabled.
Page 326 Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2) Module Base + 0x0001 PPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0 Reset Figure 9-4. PWM Polarity Register (PWMPOL) Read: Anytime Write: Anytime NOTE PPOLx register bits can be written anytime. If the polarity is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition Table 9-3.
Page 327 Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2) Table 9-4. PWMCLK Field Descriptions Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from unavailable bits return a zero Field Description Pulse Width Channel 7-0 Clock Select PCLK[7:0] 0 Clock A or B is the clock source for PWM channel 7-0, as shown in Table 9-5...
Page 328 Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2) Table 9-7. PWMPRCLK Field Descriptions Field Description 6–4 Prescaler Select for Clock B — Clock B is one of two clock sources which can be used for all channels. These PCKB[2:0] three bits determine the rate of clock B, as shown in Table 9-8.
Page 329 Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2) Table 9-9. PWMCAE Field Descriptions Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from unavailable bits return a zero Field Description 7–0 Center Aligned Output Modes on Channels 7–0 CAE[7:0] 0 Channels 7–0 operate in left aligned output mode.
Page 330 Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2) Table 9-10. PWMCTL Field Descriptions Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from unavailable bits return a zero Field Description Concatenate Channels 6 and 7 CON67 0 Channels 6 and 7 are separate 8-bit PWMs.
Page 331 Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2) Module Base + 0x00006 PCLKAB7 PCLKAB6 PCLKAB5 PCLKAB4 PCLKAB3 PCLKAB2 PCLKAB1 PCLKAB0 Reset Figure 9-9. PWM Clock Select Register (PWMCLK) Read: Anytime Write: Anytime NOTE Register bits PCLKAB0 to PCLKAB7 can be written anytime. If a clock select is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition.
Page 332 Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2) The clock source of each PWM channel is determined by PCLKx bits in PWMCLK (see Section 9.3.2.3, “PWM Clock Select Register (PWMCLK)) and PCLKABx bits in PWMCLKAB as shown in Table 9-5 Table 9-6. 9.3.2.8 PWM Scale A Register (PWMSCLA) PWMSCLA is the programmable scale value used in scaling clock A to generate clock SA.
Page 333 Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2) 9.3.2.10 PWM Channel Counter Registers (PWMCNTx) Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source. The counter can be read at any time without affecting the count or the operation of the PWM channel. In left aligned output mode, the counter counts from 0 to the value in the period register - 1.
Page 334 Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2) • The counter is written (counter resets to $00) • The channel is disabled In this way, the output of the PWM will always be either the old waveform or the new waveform, not some variation in between.
Page 335 Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2) • The channel is disabled In this way, the output of the PWM will always be either the old duty waveform or the new duty waveform, not some variation in between. If the channel is not enabled, then writes to the duty register will go directly to the latches as well as the buffer.
Page 336: Functional Description
Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2) Functional Description 9.4.1 PWM Clock Select There are four available clocks: clock A, clock B, clock SA (scaled A), and clock SB (scaled B). These four clocks are based on the bus clock. Clock A and B can be software selected to be 1, 1/2, 1/4, 1/8,..., 1/64, 1/128 times the bus clock. Clock SA uses clock A as an input and divides it further with a reloadable counter.
Page 337 Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2) Clock A Clock to PWM Ch 0 Clock A/2, A/4, A/6,..A/512 PCLK0 PCLKAB0 Count = 1 8-Bit Down Counter Clock to PWM Ch 1 Load Clock SA PCLK1 PCLKAB1 PWMSCLA DIV 2 Clock to PWM Ch 2 PCLK2 PCLKAB2 Clock to PWM Ch 3...
Page 338 Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2) Clock A is used as an input to an 8-bit down counter. This down counter loads a user programmable scale value from the scale register (PWMSCLA). When the down counter reaches one, a pulse is output and the 8-bit counter is re-loaded.
Page 339: Pwm Channel Timers
Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2) 9.4.2 PWM Channel Timers The main part of the PWM module are the actual timers. Each of the timer channels has a counter, a period register and a duty register (each are 8-bit). The waveform output period is controlled by a match between the period register and the value in the counter.
Page 340 Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2) On the front end of the PWM timer, the clock is enabled to the PWM circuit by the PWMEx bit being high. There is an edge-synchronizing circuit to guarantee that the clock will only be enabled or disabled at an edge.
Page 341 Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2) Each channel counter can be read at anytime without affecting the count or the operation of the PWM channel. Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up, the immediate load of both duty and period registers with values from the buffers, and the output to change according to the polarity bit.
Page 342 Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2) NOTE Changing the PWM output mode from left aligned to center aligned output (or vice versa) while channels are operating can cause irregularities in the PWM output. It is recommended to program the output mode before enabling the PWM channel.
Page 343 Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2) E = 100 ns Duty Cycle = 75% Period = 400 ns Figure 9-18. PWM Left Aligned Output Example Waveform 9.4.2.6 Center Aligned Outputs For center aligned output mode selection, set the CAEx bit (CAEx = 1) in the PWMCAE register and the corresponding PWM output will be center aligned.
Page 344 Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2) To calculate the output frequency in center aligned output mode for a particular channel, take the selected clock source frequency for the channel (A, B, SA, or SB) and divide it by twice the value in the period register for that channel.
Page 345 Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2) registers become the high order bytes of the double byte channel. When channels 2 and 3 are concatenated, channel 2 registers become the high order bytes of the double byte channel. When channels 0 and 1 are concatenated, channel 0 registers become the high order bytes of the double byte channel.
Page 346 Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2) Clock Source 7 High PWMCNT6 PWMCNT7 PWM7 Period/Duty Compare Clock Source 5 High PWMCNT4 PWMCNT5 PWM5 Period/Duty Compare Clock Source 3 High PWMCNT2 PWMCNT3 PWM3 Period/Duty Compare Clock Source 1 High PWMCNT0 PWMCNT1 PWM1 Period/Duty Compare Maximum possible 16-bit channels Figure 9-21.
Page 347: Resets
Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2) In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or high order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by 16-bit access to maintain data coherency.
Page 348: Interrupts
Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2) • For channels 0, 1, 4, and 5 the clock choices are clock A. • For channels 2, 3, 6, and 7 the clock choices are clock B. Interrupts The PWM module has no interrupt. S12ZVH Family Reference Manual, Rev.
Page 349: Introduction
Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) Table 10-1. Revision History Revision Revision Sections Affected Description of Changes Number Date V1.35 06. Nov 2012 10.4.2.9/10-372 Modified bit description of flag LDOK_EIF for better understanding. V1.36 08 Nov 2012 10.4.2.13/10-377 Updated description of bits RIDX_IMD for better understanding. V1.37 19.
Page 350 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) The four bits of register ADCFLWCTL reflect the captured request and status of the four internal interface Signals (LoadOK, Trigger, Restart, and Seq_abort; see also Figure 10-2) if access configuration is set accordingly and indicate event progress (when an event is processed and when it is finished). Conversion flow error situations are captured by corresponding interrupt flags in the ADCEIF register.
Page 351: Key Features
Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.2 Key Features • Programmer’s Model with List Based Architecture for conversion command and result value organization • Selectable resolution of 8-bit, 10-bit, or 12-bit • Channel select control for n external analog input channels •...
Page 352: Modes Of Operation
Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.2.1 Modes of Operation 10.2.1.1 Conversion Modes This architecture provides single, multiple, or continuous conversion on a single channel or on multiple channels based on the Command Sequence List. 10.2.1.2 MCU Operating Modes • MCU Stop Mode Before issuing an MCU Stop Mode request the ADC should be idle (no conversion or conversion sequence or Command Sequence List ongoing).
Page 353 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) • MCU Wait Mode Depending on the ADC Wait Mode configuration bit SWAI, the ADC either continues conversion in MCU Wait Mode or freezes conversion at the next conversion boundary before MCU Wait Mode is entered. ADC behavior for configuration SWAI =1’b0: The ADC continues conversion during Wait Mode according to the conversion flow control sequence.
Page 354 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) NOTE In principle, the MCU could stay in Wait Mode for a shorter period of time than the ADC needs to abort an ongoing conversion (range of µµµµs). Therefore in case a Sequence Abort Event is issued automatically due to MCU Wait Mode request a following Restart Event after exit from MCU Wait Mode can not be executed before ADC has finished this Sequence Abort Event.
Page 355: Block Diagram
Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.2.2 Block Diagram Error/ System Clock Clock ADC Clock Error FlowCtrl Issue Prescaler handler Int. (EN) Data Bus LoadOK Sequence Abort Int. Trigger Control Unit Conversion Int. Restart (Conversion Flow, Timing, Interrupt) Seq_abort see reference manual for DMA access connectivity...
Page 356: Signal Description
Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.3 Signal Description This section lists all inputs to the ADC12B_LBA block. 10.3.1 Detailed Signal Descriptions 10.3.1.1 ANx (x = n,..., 2, 1, 0) This pin serves as the analog input Channel x. The maximum input channel number is n. Please refer to the device reference manual for the maximum number of input channels.
Page 357: Memory Map And Register Definition
Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.4 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the ADC12B_LBA. 10.4.1 Module Memory Map Figure 10-3 gives an overview of all ADC12B_LBA registers. NOTE Register Address = Base Address + Address Offset, where the Base Address is defined at the MCU level and the Address Offset is defined at the module level.
Page 358: Address Name Bit
Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) Address Name Bit 7 Bit 0 R CSL_EOL RVL_EOL 0x0010 ADCEOLRI 0x0011 Reserved 0x0012 Reserved R Reserved Reserved 0x0013 Reserved 0x0014 ADCCMD_0 CMD_SEL INTFLG_SEL[3:0] 0x0015 ADCCMD_1 VRH_SEL VRL_SEL CH_SEL[5:0] 0x0016 ADCCMD_2 SMP[4:0] Reserved 0x0017 ADCCMD_3 Reserved Reserved Reserved 0x0018...
Page 359 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) Address Name Bit 7 Bit 0 0x0027 Reserved Reserved 0x0028 Reserved Reserved R Reserved Reserved 0x0029 Reserved 0x002A- Reserved 0x003F = Unimplemented or Reserved Figure 10-3. ADC12B_LBA Register Summary (Sheet 3 of 3) S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 360: Radc_En
Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.4.2 Register Descriptions This section describes in address order all the ADC12B_LBA registers and their individual bits. 10.4.2.1 ADC Control Register 0 (ADCCTL_0) Module Base + 0x0000 ADC_EN ADC_SR ACC_CFG[1:0] FRZ_MOD SWAI STR_SEQA MOD_CFG Reset = Unimplemented or Reserved Figure 10-4.
Page 361 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) Table 10-2. ADCCTL_0 Field Descriptions (continued) Field Description 11-10 ADCFLWCTL Register Access Configuration — These bits define if the register ADCFLWCTL is controlled via internal interface only or data bus only or both. See Table 10-3.
Page 362: Csl_Bmod Rvl_Bmod Smod_Acc Aut_Rsta
Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.4.2.2 ADC Control Register 1 (ADCCTL_1) Module Base + 0x0001 CSL_BMOD RVL_BMOD SMOD_ACC AUT_RSTA Reset = Unimplemented or Reserved Figure 10-5. ADC Control Register 1 (ADCCTL_1) Read: Anytime Write: • Bit CSL_BMOD and RVL_BMOD writable if bit ADC_EN clear or bit SMOD_ACC set •...
Page 363: Rvl_Sel
Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.4.2.3 ADC Status Register (ADCSTS) It is important to note that if flag DBECC_ERR is set the ADC ceases operation. In order to make the ADC operational again an ADC Soft-Reset must be issued. An ADC Soft-Reset clears bits CSL_SEL and RVL_SEL.
Page 364 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.4.2.4 ADC Timing Register (ADCTIM) Module Base + 0x0003 PRS[6:0] Reset = Unimplemented or Reserved Figure 10-7. ADC Timing Register (ADCTIM)) Read: Anytime Write: These bits are writable if bit ADC_EN is clear or bit SMOD_ACC is set Table 10-6.
Page 365 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.4.2.5 ADC Format Register (ADCFMT) Module Base + 0x0004 SRES[2:0] Reset = Unimplemented or Reserved Figure 10-8. ADC Format Register (ADCFMT) Read: Anytime Write: Bits DJM and SRES[2:0] are writable if bit ADC_EN clear or bit SMOD_ACC set Table 10-7.
Page 366 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.4.2.6 ADC Conversion Flow Control Register (ADCFLWCTL) Bit set and bit clear instructions should not be used to access this register. When the ADC is enabled the bits of ADCFLWCTL register can be modified after a latency time of three Bus Clock cycles.
Page 367 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) Table 10-9. ADCFLWCTL Field Descriptions Field Description Conversion Sequence Abort Event — This bit indicates that a conversion sequence abort event is in progress. SEQA When this bit is set the ongoing conversion sequence and current CSL will be aborted at the next conversion boundary.
Page 368 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) Table 10-9. ADCFLWCTL Field Descriptions (continued) Field Description Restart Event (Restart from Top of Command Sequence List) — This bit indicates that a Restart Event is RSTA executed. The ADC loads the conversion command from top of the active Sequence Command List when no conversion or conversion sequence is ongoing.
Page 369 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) Table 10-10. Summary of Conversion Flow Control Bit Scenarios RSTA TRIG SEQA LDOK Conversion Flow Conversion Flow Control Control Mode Scenario Both Modes Valid Both Modes Can Not Occur Both Modes Valid Both Modes Can Not Occur Both Modes Valid Both Modes...
Page 370: Cmd_Eie
Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.4.2.7 ADC Error Interrupt Enable Register (ADCEIE) Module Base + 0x0006 IA_EIE CMD_EIE EOL_EIE Reserved TRIG_EIE RSTAR_EIE LDOK_EIE Reset = Unimplemented or Reserved Figure 10-10. ADC Error Interrupt Enable Register (ADCEIE) Read: Anytime Write: Anytime Table 10-11.
Page 371: Seqad_Ie Conif_Oie
Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.4.2.8 ADC Interrupt Enable Register (ADCIE) Module Base + 0x0007 SEQAD_IE CONIF_OIE Reserved Reset = Unimplemented or Reserved Figure 10-11. ADC Interrupt Enable Register (ADCIE) Read: Anytime Write: Anytime Table 10-12. ADCIE Field Descriptions Field Description Conversion Sequence Abort Done Interrupt Enable Bit —...
Page 372: Cmd_Eif
Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.4.2.9 ADC Error Interrupt Flag Register (ADCEIF) If one of the following error flags is set the ADC ceases operation: • IA_EIF • CMD_EIF • EOL_EIF • TRIG_EIF In order to make the ADC operational again an ADC Soft-Reset must be issued which clears above listed error interrupt flags.
Page 373: Ldok_Eif
Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) Table 10-13. ADCEIF Field Descriptions (continued) Field Description Trigger Error Interrupt Flag — This flag indicates that a trigger error occurred. TRIG_EIF This flag is set in “Restart” Mode when a conversion sequence got aborted and no Restart Event occurred before the Trigger Event or if the Trigger Event occurred before the Restart Event was finished (conversion command has been loaded).
Page 374 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.4.2.10 ADC Interrupt Flag Register (ADCIF) After being set any of these bits can be cleared by writing a value of 1’b1 or via ADC soft-reset (bit ADC_SR). All bits are cleared if bit ADC_EN is clear. Writing any flag with value 1’b0 does not clear the flag.
Page 375: Eol_Ie
Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.4.2.11 ADC Conversion Interrupt Enable Register (ADCCONIE) Module Base + 0x000A CON_IE[15:1] EOL_IE Reset = Unimplemented or Reserved Figure 10-14. ADC Conversion Interrupt Enable Register (ADCCONIE) Read: Anytime Write: Anytime Table 10-15. ADCCONIE Field Descriptions Field Description 15-1...
Page 376: Eol_If
Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.4.2.12 ADC Conversion Interrupt Flag Register (ADCCONIF) After being set any of these bits can be cleared by writing a value of 1’b1. All bits are cleared if bit ADC_EN is clear or via ADC soft-reset (bit ADC_SR set). Writing any flag with value 1’b0 does not clear the flag.
Page 377 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.4.2.13 ADC Intermediate Result Information Register (ADCIMDRI) This register is cleared when bit ADC_SR is set or bit ADC_EN is clear. Module Base + 0x000E R CSL_IMD RVL_IMD RIDX_IMD[5:0] Reset = Unimplemented or Reserved Figure 10-16. ADC Intermediate Result Information Register (ADCIMDRI) Read: Anytime Write: Never Table 10-17.
Page 378 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.4.2.14 ADC End Of List Result Information Register (ADCEOLRI) This register is cleared when bit ADC_SR is set or bit ADC_EN is clear. Module Base + 0x0010 CSL_EOL RVL_EOL Reset = Unimplemented or Reserved Figure 10-17. ADC End Of List Result Information Register (ADCEOLRI) Read: Anytime Write: Never Table 10-18.
Page 379 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.4.2.15 ADC Command Register 0 (ADCCMD_0) Module Base + 0x0014 CMD_SEL INTFLG_SEL[3:0] Reset = Unimplemented or Reserved Figure 10-18. ADC Command Register 0 (ADCCMD_0) Read: Anytime Write: Only writable if bit SMOD_ACC is set (see also Section 10.4.2.2, “ADC Control Register 1 (ADCCTL_1) bit SMOD_ACC description for more details)
Page 380 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) Table 10-21. Conversion Interrupt Flag Select CON_IF[15:1] INTFLG_SEL[3] INTFLG_SEL[2] INTFLG_SEL[1] INTFLG_SEL[0] Comment 0x0000 No flag set 0x0001 0x0002 0x0004 0x0008 Only one flag can 0x0010 be set ..(one hot coding) 0x0800 0x1000 0x2000 0x4000 S12ZVH Family Reference Manual, Rev.
Page 381 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.4.2.16 ADC Command Register 1 (ADCCMD_1) A command which contains reserved bit settings causes the error flag CMD_EIF being set and ADC cease operation. Module Base + 0x0015 VRH_SEL VRL_SEL CH_SEL[5:0] Reset = Unimplemented or Reserved Figure 10-19.
Page 382 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) Table 10-23. Analog Input Channel Select CH_SEL[5] CH_SEL[4] CH_SEL[3] CH_SEL[2] CH_SEL[1] CH_SEL[0] Analog Input Channel Reserved Internal_0 (ADC temperature sense) Internal_1 (Vreg_3v3 sense) Internal_2 Internal_3 Internal_4 Internal_5 Internal_6 Internal_7 Reserved NOTE ANx in Table 10-23 is the maximum number of implemented analog input channels on the device.
Page 383 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.4.2.17 ADC Command Register 2 (ADCCMD_2) A command which contains reserved bit settings causes the error flag CMD_EIF being set and ADC cease operation. Module Base + 0x0016 SMP[4:0] Reserved Reset = Unimplemented or Reserved Figure 10-20.
Page 384 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) Table 10-25. Sample Time Select Sample Time SMP[4] SMP[3] SMP[2] SMP[1] SMP[0] in Number of ADC Clock Cycles Reserved Reserved Reserved Reserved S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 385 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.4.2.18 ADC Command Register 3 (ADCCMD_3) Module Base + 0x0017 Reserved Reserved Reserved Reset = Unimplemented or Reserved Figure 10-21. ADC Command Register 3 (ADCCMD_3) S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 386 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.4.2.19 ADC Command Index Register (ADCCIDX) It is important to note that these bits do not represent absolute addresses instead it is a sample index (object size 32bit). Module Base + 0x001C CMD_IDX[5:0] Reset = Unimplemented or Reserved Figure 10-22.
Page 387 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.4.2.20 ADC Command Base Pointer Register (ADCCBP) Module Base + 0x001D CMD_PTR[23:16] Reset Module Base + 0x001E CMD_PTR[15:8] Reset Module Base + 0x001F CMD_PTR[7:2] Reset = Unimplemented or Reserved Figure 10-23. ADC Command Base Pointer Registers (ADCCBP_0, ADCCBP_1, ADCCBP_2)) Read: Anytime Write: Bits CMD_PTR[23:2] writable if bit ADC_EN clear or bit SMOD_ACC set Table 10-27.
Page 388 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.4.2.21 ADC Result Index Register (ADCRIDX) It is important to note that these bits do not represent absolute addresses instead it is a sample index (object size 16bit). Module Base + 0x0020 RES_IDX[5:0] Reset = Unimplemented or Reserved Figure 10-24.
Page 389 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.4.2.22 ADC Result Base Pointer Register (ADCRBP) Module Base + 0x0021 RES_PTR[19:16] Reset Module Base + 0x0022 RES_PTR[15:8] Reset Module Base + 0x0023 RES_PTR[7:2] Reset = Unimplemented or Reserved Figure 10-25. ADC Result Base Pointer Registers (ADCRBP_0, ADCRBP_1, ADCRBP_2)) Read: Anytime Write: Bits RES_PTR[19:2] writeable if bit ADC_EN clear or bit SMOD_ACC set Table 10-29.
Page 390 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.4.2.23 ADC Command and Result Offset Register 0 (ADCCROFF0) Module Base + 0x0024 CMDRES_OFF0[6:0] Reset = Unimplemented or Reserved Figure 10-26. ADC Command and Result Offset Register 0 (ADCCROFF0) Read: Anytime Write: NA Table 10-30. ADCCROFF0 Field Descriptions Field Description ADC Command and Result Offset Value —...
Page 391 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.4.2.24 ADC Command and Result Offset Register 1 (ADCCROFF1) It is important to note that these bits do not represent absolute addresses instead it is an sample offset (object size 16bit for RVL, object size 32bit for CSL). Module Base + 0x0025 CMDRES_OFF1[6:0] Reset...
Page 392: Functional Description
Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.5 Functional Description 10.5.1 Overview The ADC12B_LBA consists of an analog sub-block and a digital sub-block. It is a successive approximation analog-to-digital converter including a sample-and-hold mechanism and an internal charge scaled C-DAC (switched capacitor scaled digital-to-analog converter) with a comparator to realize the successive approximation algorithm.
Page 393: Digital Sub-Block
Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) Please note that there is always a pump phase of two ADC_CLK cycles before the sample phase begins, hence glitches during the pump phase could impact the conversion accuracy for short sample times. 10.5.3 Digital Sub-Block The digital sub-block contains a list-based programmer’s model and the control logic for the analog sub- block circuits.
Page 394 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.5.3.2.1 Introduction of The Command Sequence List (CSL) Format A Command Sequence List (CSL) contains up to 64 conversion commands. A user selectable number of successive conversion commands in the CSL can be grouped as a command sequence. This sequence of conversion commands is successively executed by the ADC at the occurrence of a Trigger Event.
Page 395 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) CSL_0 Command coding information CMD_SEL[1:0] done by bits Initial trigger only Command_1 normal conversion Command_2 normal conversion Command_3 normal conversion Command_4 normal conversion Command_5 normal conversion Command_6 normal conversion continuous Command_7 normal conversion conversion Command_8 normal conversion Command_9 normal conversion...
Page 396 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.5.3.2.2 Introduction of the two Command Sequence Lists (CSLs) The two Command Sequence Lists (CSLs) can be referred to via the Command Base Pointer Register plus the Command and Result Offset Registers plus the Command Index Register (ADCCBP, ADCCROFF_0/1, ADCCIDX).
Page 397 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) CSL_SEL = 1’b0 (forced by CSL_BMOD) Memory Map 0x00_0000 Register Space RAM or NVM start address RAM or NVM Space ADCCBP+(ADCCROFF_0) CSL_0 (active) ADCCBP+(ADCCROFF_0+ ADCCIDX(max)) RAM or NVM end address Note: Address register names in () are not absolute addresses instead they are a sample offset or sample index Figure 10-32.
Page 398 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.5.3.2.3 Introduction of the two Result Value Lists (RVLs) The same list-based architecture as described above for the CSL has been implemented for the Result Value List (RVL) with corresponding address registers (ADCRBP, ADCCROFF_0/1, ADCRIDX). The final address for conversion result storage is calculated by the sum of these registers (e.g.: ADCRBP+ADCCROFF_0+ADCRIDX or ADCRBP+ADCCROFF_1+ADCRIDX).
Page 399 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) RVL_SEL = 1’b0 (forced by bit RVL_BMOD) Memory Map 0x00_0000 Register Space RAM start address RAM Space ADCRBP+(ADCCROFF_0) RVL_0 (active) ADCRBP+(ADCCROFF_0+ ADCRIDX(max)) RAM end address Note: Address register names in () are not absolute addresses instead they are a sample offset or sample index Figure 10-34.
Page 400 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.5.3.2.4 The two conversion flow control Mode Configurations The ADC provides two modes (“Trigger Mode” and “Restart Mode”) which are different in the conversion control flow. The “Restart Mode” provides precise timing control about the sample start point but is more complex from the flow control perspective, while the “Trigger Mode”...
Page 401 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) – Function: Start the first conversion of a conversion sequence which is defined in the active Command Sequence List – Requested by: - Positive edge of internal interface signal Trigger - Write Access via data bus to set control bit TRIG –...
Page 402 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) – When finished: This bit is cleared when the first conversion command of the sequence from top of active Sequence Command List is loaded – Mandatory Requirement: - In all ADC conversion flow control modes a Restart Event causes bit RSTA to be set. Bit SEQA is set simultaneously by ADC hardware if: * ADC not idle (a conversion or conversion sequence is ongoing and current CSL not finished) and no Sequence Abort Event in progress (bit SEQA not already set or set...
Page 403 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) If signal Restart is asserted before signal LoadOK is set the conversion starts from top of currently active CSL at the next Trigger Event (no exchange of CSL list). If signal Restart is asserted after or simultaneously with signal LoadOK the conversion starts from top of the other CSL at the next Trigger Event (CSL is switched) if CSL is configured for double buffer mode.
Page 404 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.5.3.2.6 Conversion flow control in case of conversion sequence control bit overrun scenarios Restart Request Overrun: If a legal Restart Request is detected and no Restart Event is in progress, the RSTA bit is set due to the request.
Page 405 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.5.3.3 ADC List Usage and Conversion/Conversion Sequence Flow Description It is the user’s responsibility to make sure that the different lists do not overlap or exceed the system RAM area respectively the CSL does not exceed the NVM area if located in the NVM. The error flag IA_EIF will be set for accesses done outside the system RAM area and will cause an error interrupt if enabled for lists that are located in the system RAM.
Page 406: Resets
Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.6 Resets At reset the ADC12B_LBA is disabled and in a power down state. The reset state of each individual bit is listed within Section 10.4.2, “Register Descriptions” which details the registers and their bit-fields. 10.7 Interrupts The ADC supports three types of interrupts:...
Page 407: Adc Error And Conversion Flow Control Issue Interrupt
Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.7.3 ADC Error and Conversion Flow Control Issue Interrupt The ADC provides one error interrupt for four error classes related to conversion interrupt overflow, command validness, DMA access status and Conversion Flow Control issues, and CSL failure. The following error interrupt flags belong to the group of severe issues which cause an error interrupt if enabled and cease ADC operation: •...
Page 408: Use Cases And Application Information
Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.8 Use Cases and Application Information 10.8.1 List Usage — CSL single buffer mode and RVL single buffer mode In this use case both list types are configured for single buffer mode (CSL_BMOD=1’b0 and RVL_BMOD=1’b0, CSL_SEL and RVL_SEL are forced to 1’b0). The index register for the CSL and RVL are cleared to start from the top of the list with next conversion command and result storage in the following cases: •...
Page 409: List Usage — Csl Double Buffer Mode And Rvl Double Buffer Mode
Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.8.3 List Usage — CSL double buffer mode and RVL double buffer mode In this use case both list types are configured for double buffer mode (CSL_BMOD=1’b1 and RVL_BMOD=1’b1) and whenever a Command Sequence List (CSL) is finished or aborted the command Sequence List is swapped by the simultaneous assertion of bits LDOK and RSTA.
Page 410: List Usage — Csl Double Buffer Mode And Rvl Double Buffer Mode
Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.8.5 List Usage — CSL double buffer mode and RVL double buffer mode In this use case both list types are configured for double buffer mode (CSL_BMOD=1’b1) and RVL_BMOD=1’b1). This setup is the same as Section 10.8.3, “List Usage —...
Page 411 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) Stop Mode request Wake-up Initial Event with while conversion Restart ongoing and before EOL AUT_RSTA= 1’b1 Event CSL Buffer CSL_0 CSL_1 CSL_0 CSL_0 INT_1 INT_2 Stop Mode INT_1 entry return to execute from top of CSL delay RVL swap due to EOL...
Page 412: Conversion Flow Control Application Information
Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.8.7 Conversion flow control application information The ADC12B_LBA provides various conversion control scenarios to the user accomplished by the following features. The ADC conversion flow control can be realized via the data bus only, the internal interface only, or by both access methods.
Page 413 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) mode “Trigger Mode” only a Restart Event is necessary if ADC is idle to restart Conversion Sequence List execution (the Trigger Event occurs automatically). It is possible to set bit RSTA and SEQA simultaneously, causing a Sequence Abort Event followed by a Restart Event.
Page 414: Continuous Conversion
Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) Please see also the detailed conversion flow control bit mandatory requirements and execution information for bit RSTA and SEQA described in Section 10.5.3.2.5, “The four ADC conversion flow control bits. 10.8.8 Continuous Conversion Applications that only need to continuously convert a list of channels, without the need for timing control or the ability to perform different sequences of conversions (grouped number of different channels to convert) can make use of the following simple setup: •...
Page 415: Triggered Conversion — Single Csl
Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.8.9 Triggered Conversion — Single CSL Applications that require the conversion of one or more groups of different channels in a periodic and timed manner can make use of a configuration in “Trigger Mode” with a single CSL containing a list of sequences.
Page 416: Fully Timing Controlled Conversion
Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.8.10 Fully Timing Controlled Conversion As described previously, in “Trigger Mode” a Restart Event automatically causes a trigger. To have full and precise timing control of the beginning of any conversion/sequence the “Restart Mode” is available. In “Restart Mode”...
Page 417: Introduction
Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) Revision History Revision Sections Revision Date Description of Changes Number Affected V03.14 12 Nov 2012 Table 11-10 • Corrected RxWRN and TxWRN threshold values V03.15 12 Jan 2013 Table 11-2 • Updated TIME bit description Table 11-25 •...
Page 418: Glossary
Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.1.1 Glossary Table 11-1. Terminology Acknowledge of CAN message Controller Area Network Cyclic Redundancy Code End of Frame FIFO First-In-First-Out Memory Inter-Frame Sequence Start of Frame CPU bus CPU related read/write data bus CAN bus CAN protocol related serial bus oscillator clock...
Page 419: Features
Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.1.3 Features The basic features of the MSCAN are as follows: • Implementation of the CAN protocol — Version 2.0A/B — Standard and extended data frames — Zero to eight bytes data length —...
Page 420: External Signal Description
Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.2 External Signal Description The MSCAN uses two external pins. NOTE On MCUs with an integrated CAN physical interface (transceiver) the MSCAN interface is connected internally to the transceiver interface. In these cases the external availability of signals TXCAN and RXCAN is optional.
Page 421: S12Zvh Family Reference Manual, Rev. 1.05 Freescale Semiconductor
Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the MSCAN. 11.3.1 Module Memory Map Figure 11-3 gives an overview on all registers and their individual bits in the MSCAN memory map. The register address results from the addition of base address and address offset.
Page 422 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) Register Bit 7 Bit 0 Name 0x0000 RXACT SYNCH RXFRM CSWAI TIME WUPE SLPRQ INITRQ CANCTL0 0x0001 SLPAK INITAK CANE CLKSRC LOOPB LISTEN BORM WUPM CANCTL1 0x0002 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0...
Page 423: Register Descriptions
Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) Register Bit 7 Bit 0 Name 0x000F TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 CANTXERR 0x0010–0x0013 CANIDAR0–3 0x0014–0x0017 CANIDMRx 0x0018–0x001B CANIDAR4–7 0x001C–0x001F CANIDMR4–7 0x0020–0x002F Section 11.3.3, “Programmer’s Model of Message Storage” CANRXFG 0x0030–0x003F Section 11.3.3, “Programmer’s Model of Message...
Page 424 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) 1. Read: Anytime Write: Anytime when out of initialization mode; exceptions are read-only RXACT and SYNCH, RXFRM (which is set by the module only), and INITRQ (which is also writable in initialization mode) NOTE The CANCTL0 register, except WUPE, INITRQ, and SLPRQ, is held in the reset state when the initialization mode is active (INITRQ = 1 and...
Page 425 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-2. CANCTL0 Register Field Descriptions (continued) Field Description Sleep Mode Request — This bit requests the MSCAN to enter sleep mode, which is an internal power saving SLPRQ mode (see Section 11.4.5.5, “MSCAN Sleep Mode”).
Page 426 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) Module Base + 0x0001 Access: User read/write SLPAK INITAK CANE CLKSRC LOOPB LISTEN BORM WUPM Reset: = Unimplemented Figure 11-5. MSCAN Control Register 1 (CANCTL1) 1. Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1), except CANE which is write once in normal and anytime in special system operation modes when the MSCAN is in initialization mode (INITRQ = 1 and INITAK = 1) Table 11-3.
Page 427 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-3. CANCTL1 Register Field Descriptions (continued) Field Description Sleep Mode Acknowledge — This flag indicates whether the MSCAN module has entered sleep mode (see SLPAK Section 11.4.5.5, “MSCAN Sleep Mode”). It is used as a handshake flag for the SLPRQ sleep mode request. Sleep mode is active when SLPRQ = 1 and SLPAK = 1.
Page 428 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-6. Baud Rate Prescaler BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Prescaler value (P) 11.3.2.4 MSCAN Bus Timing Register 1 (CANBTR1) The CANBTR1 register configures various CAN bus timing parameters of the MSCAN module. Module Base + 0x0003 Access: User read/write SAMP...
Page 429 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-8. Time Segment 2 Values TSEG22 TSEG21 TSEG20 Time Segment 2 1 Tq clock cycle 2 Tq clock cycles 7 Tq clock cycles 8 Tq clock cycles 1. This setting is not valid. Please refer to Table 11-36 for valid settings.
Page 430 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) 1. Read: Anytime Write: Anytime when not in initialization mode, except RSTAT[1:0] and TSTAT[1:0] flags which are read-only; write of 1 clears flag; write of 0 is ignored NOTE The CANRFLG register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1).
Page 431 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-10. CANRFLG Register Field Descriptions (continued) Field Description Overrun Interrupt Flag — This flag is set when a data overrun condition occurs. If not masked, an error interrupt OVRIF is pending while this flag is set. No data overrun condition A data overrun detected Receive Buffer Full Flag —...
Page 432 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-11. CANRIER Register Field Descriptions Field Description Wake-Up Interrupt Enable WUPIE 0 No interrupt request is generated from this event. 1 A wake-up event causes a Wake-Up interrupt request. CAN Status Change Interrupt Enable CSCIE 0 No interrupt request is generated from this event.
Page 433 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) Module Base + 0x0006 Access: User read/write TXE2 TXE1 TXE0 Reset: = Unimplemented Figure 11-10. MSCAN Transmitter Flag Register (CANTFLG) 1. Read: Anytime Write: Anytime when not in initialization mode; write of 1 clears flag, write of 0 is ignored NOTE The CANTFLG register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1).
Page 434 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) 1. Read: Anytime Write: Anytime when not in initialization mode NOTE The CANTIER register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0).
Page 435 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.3.2.10 MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK) The CANTAAK register indicates the successful abort of a queued message, if requested by the appropriate bits in the CANTARQ register. Module Base + 0x0009 Access: User read/write ABTAK2 ABTAK1...
Page 436 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) NOTE The CANTBSEL register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK=1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Table 11-16.
Page 437 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-17. CANIDAC Register Field Descriptions Field Description Identifier Acceptance Mode — The CPU sets these flags to define the identifier acceptance filter organization IDAM[1:0] (see Section 11.4.3, “Identifier Acceptance Filter”). Table 11-18 summarizes the different settings.
Page 438 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) Module Base + 0x000C Access: User read/write Reset: = Unimplemented Figure 11-16. MSCAN Reserved Register 1. Read: Always reads zero in normal system operation modes Write: Unimplemented in normal system operation modes NOTE Writing to this register when in special system operating modes can alter the MSCAN functionality.
Page 439 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) Module Base + 0x000E Access: User read/write RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 Reset: = Unimplemented Figure 11-18. MSCAN Receive Error Counter (CANRXERR) 1. Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1) Write: Unimplemented NOTE Reading this register when in any other mode other than sleep or...
Page 440 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.3.2.17 MSCAN Identifier Acceptance Registers (CANIDAR0-7) On reception, each message is written into the background receive buffer. The CPU is only signalled to read the message if it passes the criteria in the identifier acceptance and identifier mask registers (accepted);...
Page 441 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-22. CANIDAR4–CANIDAR7 Register Field Descriptions Field Description Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits AC[7:0] of the related identifier register (IDRn) of the re ceive message buffer are compared. The result of this comparison is then masked with the corresponding identifier mask register.
Page 442: Programmer's Model Of Message Storage
Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) 1. Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) Table 11-24. CANIDMR4–CANIDMR7 Register Field Descriptions Field Description Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in AM[7:0] the identifier acceptance register must be the same as its identifier bit before a match is detected.
Page 443 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-25. Message Buffer Organization Offset Register Access Address 0x00X0 IDR0 — Identifier Register 0 0x00X1 IDR1 — Identifier Register 1 0x00X2 IDR2 — Identifier Register 2 0x00X3 IDR3 — Identifier Register 3 0x00X4 DSR0 —...
Page 444 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) Figure 11-24. Receive/Transmit Message Buffer — Extended Identifier Mapping Register Bit 7 Bit0 Name 0x00X0 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 IDR0 0x00X1 ID20 ID19 ID18 SRR (=1) IDE (=1) ID17 ID16 ID15...
Page 445 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) Figure 11-24. Receive/Transmit Message Buffer — Extended Identifier Mapping (continued) Register Bit 7 Bit0 Name = Unused, always read ‘x’ Read: • For transmit buffers, anytime when TXEx flag is set (see Section 11.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see...
Page 446 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.3.3.1.1 IDR0–IDR3 for Extended Identifier Mapping Module Base + 0x00X0 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 Reset: Figure 11-26. Identifier Register 0 (IDR0) — Extended Identifier Mapping Table 11-26. IDR0 Register Field Descriptions — Extended Field Description Extended Format Identifier —...
Page 447 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) Module Base + 0x00X2 ID14 ID13 ID12 ID11 ID10 Reset: Figure 11-28. Identifier Register 2 (IDR2) — Extended Identifier Mapping Table 11-28. IDR2 Register Field Descriptions — Extended Field Description Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the ID[14:7] most significant bit and is transmitted first on the CAN bus during the arbitration procedure.
Page 448 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.3.3.1.2 IDR0–IDR3 for Standard Identifier Mapping Module Base + 0x00X0 ID10 Reset: Figure 11-30. Identifier Register 0 — Standard Mapping Table 11-30. IDR0 Register Field Descriptions — Standard Field Description Standard Format Identifier — The identifiers consist of 11 bits (ID[10:0]) for the standard format. ID10 is the ID[10:3] most significant bit and is transmitted first on the CAN bus during the arbitration procedure.
Page 449 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) Module Base + 0x00X2 Reset: = Unused; always read ‘x’ Figure 11-32. Identifier Register 2 — Standard Mapping Module Base + 0x00X3 Reset: = Unused; always read ‘x’ Figure 11-33. Identifier Register 3 — Standard Mapping 11.3.3.2 Data Segment Registers (DSR0-7) The eight data segment registers, each with bits DB[7:0], contain the data to be transmitted or received.
Page 450 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.3.3.3 Data Length Register (DLR) This register keeps the data length field of the CAN frame. Module Base + 0x00XC DLC3 DLC2 DLC1 DLC0 Reset: = Unused; always read “x” Figure 11-35. Data Length Register (DLR) — Extended Identifier Mapping Table 11-33.
Page 451 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) • The transmission buffer with the lowest local priority field wins the prioritization. In cases of more than one buffer having the same lowest priority, the message buffer with the lower index number wins.
Page 452 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) Module Base + 0x00XF Access: User read/write TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0 Reset: Figure 11-38. Time Stamp Register — Low Byte (TSRL) 1. Read: or transmit buffers: Anytime when TXEx flag is set (see Section 11.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 11.3.2.11, “MSCAN Transmit...
Page 453: Functional Description
Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.4 Functional Description 11.4.1 General This section provides a complete functional description of the MSCAN. 11.4.2 Message Storage CAN Receive / Transmit Engine Memory Mapped I/O MSCAN CPU bus Receiver TXE0 PRIO TXE1 CPU bus MSCAN...
Page 454 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) The MSCAN facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications. 11.4.2.1 Message Transmit Background Modern application layer software is built upon two fundamental assumptions: •...
Page 455 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) software simpler because only one address area is applicable for the transmit process, and the required address space is minimized. The CPU then stores the identifier, the control bits, and the data content into one of the transmit buffers. Finally, the buffer is flagged as ready for transmission by clearing the associated TXE flag.
Page 456: Identifier Acceptance Filter
Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) generates a receive interrupt (see Section 11.4.7.3, “Receive Interrupt”) to the CPU. The user’s receive handler must read the received message from the RxFG and then reset the RXF flag to acknowledge the interrupt and to release the foreground buffer.
Page 457 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) Figure 11-40 shows how the first 32-bit filter bank (CANIDAR0–CANIDAR3, CANIDMR0–CANIDMR3) produces a filter 0 hit. Similarly, the second filter bank (CANIDAR4–CANIDAR7, CANIDMR4–CANIDMR7) produces a filter 1 hit. • Four identifier acceptance filters, each to be applied to: —...
Page 458 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) CAN 2.0B ID28 IDR0 ID21 ID20 IDR1 ID15 ID14 IDR2 IDR3 Extended Identifier CAN 2.0A/B ID10 IDR0 IDR1 ID10 IDR2 ID10 IDR3 Standard Identifier CANIDMR0 CANIDMR1 CANIDAR0 CANIDAR1 ID Accepted (Filter 0 Hit) CANIDMR2 CANIDMR3 CANIDAR2...
Page 459 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) CAN 2.0B Extended Identifier ID28 IDR0 ID21 ID20 IDR1 ID15 ID14 IDR2 IDR3 CAN 2.0A/B ID10 IDR0 IDR1 ID10 IDR2 ID10 IDR3 Standard Identifier CIDMR0 CIDAR0 ID Accepted (Filter 0 Hit) CIDMR1 CIDAR1 ID Accepted (Filter 1 Hit) CIDMR2...
Page 460 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.4.3.1 Protocol Violation Protection The MSCAN protects the user from accidentally violating the CAN protocol through programming errors. The protection logic implements the following features: • The receive and transmit error counters cannot be written or otherwise manipulated. •...
Page 461 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) For microcontrollers without a clock and reset generator (CRG), CANCLK is driven from the crystal oscillator (oscillator clock). A programmable prescaler generates the time quanta (Tq) clock from CANCLK. A time quantum is the atomic unit of time handled by the MSCAN.
Page 462: Modes Of Operation
Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-35. Time Segment Syntax Syntax Description System expects transitions to occur on the CAN bus during this SYNC_SEG period. A node in transmit mode transfers a new value to the CAN bus at Transmit Point this point.
Page 463 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.4.4.2 Special System Operating Modes The MSCAN module behaves as described within this specification in all special system operating modes. Write restrictions which exist on specific registers in normal modes are lifted for test purposes in special modes.
Page 464: Low-Power Options
Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) Bus Clock Domain CAN Clock Domain INIT INITRQ SYNC sync. Flag INITRQ Init Request INITAK sync. SYNC INITAK Flag INITAK Figure 11-45. Initialization Request/Acknowledge Cycle Due to independent clock domains within the MSCAN, INITRQ must be synchronized to all domains by using a special handshake mechanism.
Page 465 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-37. CPU vs. MSCAN Operating Modes MSCAN Mode Reduced Power Consumption CPU Mode Normal Disabled Sleep Power Down (CANE=0) CSWAI = X CSWAI = X CSWAI = X SLPRQ = 1 SLPRQ = X SLPRQ = 0 SLPAK = 1...
Page 466 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.4.5.5 MSCAN Sleep Mode The CPU can request the MSCAN to enter this low power mode by asserting the SLPRQ bit in the CANCTL0 register. The time when the MSCAN enters sleep mode depends on a fixed synchronization delay and its current activity: •...
Page 467 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) If the WUPE bit in CANCTL0 is not asserted, the MSCAN will mask any activity it detects on CAN. RXCAN is therefore held internally in a recessive state. This locks the MSCAN in sleep mode. WUPE must be set before entering sleep mode to take effect.
Page 468: Reset Initialization
Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.4.5.7 Disabled Mode The MSCAN is in disabled mode out of reset (CANE=0). All module clocks are stopped for power saving, however the register map can still be accessed as specified. 11.4.5.8 Programmable Wake-Up Function The MSCAN can be programmed to wake up from sleep or power down mode as soon as CAN bus activity is detected (see control bit WUPE in MSCAN Control Register 0 (CANCTL0).
Page 469 Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.4.7.3 Receive Interrupt A message is successfully received and shifted into the foreground buffer (RxFG) of the receiver FIFO. This interrupt is generated immediately after receiving the EOF symbol. The RXF flag is set. If there are multiple messages in the receiver FIFO, the RXF flag is set as soon as the next message is shifted to the foreground buffer.
Page 470: Initialization/Application Information
Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.5 Initialization/Application Information 11.5.1 MSCAN initialization The procedure to initially start up the MSCAN module out of reset is as follows: 1. Assert CANE 2. Write to the configuration registers in initialization mode 3.
Page 471: Introduction
Chapter 12 Serial Peripheral Interface (S12SPIV5) Table 12-1. Revision History Revision Sections Revision Date Description of Changes Number Affected V05.00 24 Mar 2005 12.3.2/12-475 - Added 16-bit transfer width feature. 12.1 Introduction The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices.
Page 472: Block Diagram
Chapter 12 Serial Peripheral Interface (S12SPIV5) • Run mode This is the basic mode of operation. • Wait mode SPI operation in wait mode is a configurable low power mode, controlled by the SPISWAI bit located in the SPICR2 register. In wait mode, if the SPISWAI bit is clear, the SPI operates like in run mode.
Page 473: External Signal Description
Chapter 12 Serial Peripheral Interface (S12SPIV5) SPI Control Register 1 BIDIROE SPI Control Register 2 SPC0 SPI Status Register Slave CPOL CPHA MOSI Control SPIF MODF SPTEF Phase + SCK In Interrupt Control Polarity Slave Baud Rate Control MISO Interrupt Master Baud Rate Phase + SCK Out...
Page 474: Ss — Slave Select Pin
Chapter 12 Serial Peripheral Interface (S12SPIV5) 12.2.3 SS — Slave Select Pin This pin is used to output the select signal from the SPI module to another peripheral with which a data transfer is to take place when it is configured as a master and it is used as an input to receive the slave select signal when the SPI is configured as slave.
Page 475: Register Descriptions
Chapter 12 Serial Peripheral Interface (S12SPIV5) 12.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
Page 476 Chapter 12 Serial Peripheral Interface (S12SPIV5) Table 12-2. SPICR1 Field Descriptions (continued) Field Description Slave Select Output Enable — The SS output feature is enabled only in master mode, if MODFEN is set, by SSOE asserting the SSOE as shown in Table 12-3.
Page 477 Chapter 12 Serial Peripheral Interface (S12SPIV5) Table 12-4. SPICR2 Field Descriptions Field Description Transfer Width — This bit is used for sel e cting the data transfer width. If 8-bit transfer width is selected, SPIDRL XFRW becomes the dedicated data register and SPIDRH is unused. If 16-bit transfer width is selected, SPIDRH and SPIDRL form a 16-bit data register.
Page 478 Chapter 12 Serial Peripheral Interface (S12SPIV5) 12.3.2.3 SPI Baud Rate Register (SPIBR) Module Base +0x0002 SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Reset = Unimplemented or Reserved Figure 12-5. SPI Baud Rate Register (SPIBR) Read: Anytime Write: Anytime; writes to the reserved bits have no effect Table 12-6.
Page 479 Chapter 12 Serial Peripheral Interface (S12SPIV5) Table 12-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (Sheet 2 of 3) Baud Rate SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate Divisor 390.63 kbit/s 195.31 kbit/s 97.66 kbit/s 48.83 kbit/s 4.16667 Mbit/s 2.08333 Mbit/s 1.04167 Mbit/s...
Page 480 Chapter 12 Serial Peripheral Interface (S12SPIV5) Table 12-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (Sheet 3 of 3) Baud Rate SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate Divisor 27.90 kbit/s 1792 13.95 kbit/s 1.5625 Mbit/s 781.25 kbit/s 390.63 kbit/s 195.31 kbit/s 97.66 kbit/s...
Page 481 Chapter 12 Serial Peripheral Interface (S12SPIV5) Table 12-9. SPIF Interrupt Flag Clearing Sequence XFRW Bit SPIF Interrupt Flag Clearing Sequence Read SPISR with SPIF == 1 Read SPIDRL then Read SPISR with SPIF == 1 Byte Read SPIDRL Byte Read SPIDRH Byte Read SPIDRL then Word Read (SPIDRH:SPIDRL)
Page 482 Chapter 12 Serial Peripheral Interface (S12SPIV5) 12.3.2.5 SPI Data Register (SPIDR = SPIDRH:SPIDRL) Module Base +0x0004 Reset Figure 12-7. SPI Data Register High (SPIDRH) Module Base +0x0005 Reset Figure 12-8. SPI Data Register Low (SPIDRL) Read: Anytime; read data only valid when SPIF is set Write: Anytime The SPI data register is both the input and output register for SPI data.
Page 483: Functional Description
Chapter 12 Serial Peripheral Interface (S12SPIV5) Data A Received Data B Received Data C Received SPIF Serviced Receive Shift Register Data B Data A Data C SPIF Data C SPI Data Register Data B Data A = Unspecified = Reception in progress Figure 12-9.
Page 484: Master Mode
Chapter 12 Serial Peripheral Interface (S12SPIV5) The main element of the SPI system is the SPI data register. The n-bit data register in the master and the n-bit data register in the slave are linked by the MOSI and MISO pins to form a distributed 2n-bit register.
Page 485: Slave Mode
Chapter 12 Serial Peripheral Interface (S12SPIV5) drive the MOSI and SCK lines. In this case, the SPI immediately switches to slave mode, by clearing the MSTR bit and also disables the slave output buffer MISO (or SISO in bidirectional mode). So the result is that all outputs are disabled and SCK, MOSI, and MISO are inputs. If a transmission is in progress when the mode fault occurs, the transmission is aborted and the SPI is forced into idle state.
Page 486: Transmission Formats
Chapter 12 Serial Peripheral Interface (S12SPIV5) As long as no more than one slave device drives the system slave’s serial data output line, it is possible for several slaves to receive the same transmission from a master, although the master would not receive return information from all of the receiving slaves.
Page 487 Chapter 12 Serial Peripheral Interface (S12SPIV5) The CPOL clock polarity control bit specifies an active high or low clock and has no significant effect on the transmission format. The CPHA clock phase control bit selects one of two fundamentally different transmission formats. Clock phase and polarity should be identical for the master SPI device and the communicating slave device.
Page 488 Chapter 12 Serial Peripheral Interface (S12SPIV5) End of Idle State Begin of Idle State Begin Transfer 13 14 SCK Edge Number SCK (CPOL = 0) SCK (CPOL = 1) SAMPLE I MOSI/MISO CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I)
Page 489 Chapter 12 Serial Peripheral Interface (S12SPIV5) End of Idle State Begin of Idle State Begin Transfer SCK Edge Number SCK (CPOL = 0) SCK (CPOL = 1) SAMPLE I MOSI/MISO CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I) Bit 14...
Page 490 Chapter 12 Serial Peripheral Interface (S12SPIV5) When the third edge occurs, the value previously latched from the serial data input pin is shifted into the LSB or MSB of the SPI shift register, depending on LSBFE bit. After this edge, the next bit of the master data is coupled out of the serial data output pin of the master to the serial input pin on the slave.
Page 491: Spi Baud Rate Generation
Chapter 12 Serial Peripheral Interface (S12SPIV5) End of Idle State Begin of Idle State Begin Transfer SCK Edge Number SCK (CPOL = 0) SCK (CPOL = 1) SAMPLE I MOSI/MISO CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I) Minimum 1/2 SCK...
Page 492: Special Features
Chapter 12 Serial Peripheral Interface (S12SPIV5) When all bits are clear (the default condition), the SPI module clock is divided by 2. When the selection bits (SPR2–SPR0) are 001 and the preselection bits (SPPR2–SPPR0) are 000, the module clock divisor becomes 4.
Page 493: Error Conditions
Chapter 12 Serial Peripheral Interface (S12SPIV5) Table 12-11. Normal Mode and Bidirectional Mode When SPE = 1 Master Mode MSTR = 1 Slave Mode MSTR = 0 MOSI Serial Out Serial In MOSI Normal Mode SPC0 = 0 Serial Out Serial In MISO MISO...
Page 494: Low Power Mode Options
Chapter 12 Serial Peripheral Interface (S12SPIV5) the SPI system is configured as a slave, the SS pin is a dedicated input pin. Mode fault error doesn’t occur in slave mode. If a mode fault error occurs, the SPI is switched to slave mode, with the exception that the slave output buffer is disabled.
Page 495 Chapter 12 Serial Peripheral Interface (S12SPIV5) NOTE Care must be taken when expecting data from a master while the slave is in wait or stop mode. Even though the shift register will continue to operate, the rest of the SPI is shut down (i.e., a SPIF interrupt will not be generated until exiting stop or wait mode).
Page 496 Chapter 12 Serial Peripheral Interface (S12SPIV5) 12.4.7.5.2 SPIF SPIF occurs when new data has been received and copied to the SPI data register. After SPIF is set, it does not clear until it is serviced. SPIF has an automatic clearing process, which is described in Section 12.3.2.4, “SPI Status Register (SPISR)”.
Page 497: Introduction
Chapter 13 Inter-Integrated Circuit (IICV3) Block Description Table 13-1. Revision History Revision Sections Revision Date Description of Changes Number Affected V01.03 28 Jul 2006 13.7.1.7/13-521 - Update flow-chart of interrupt routine for 10-bit address V01.04 17 Nov 2006 13.3.1.2/13-501 - Revise Table1-5 V01.05 14 Aug 2007 13.3.1.1/13-501...
Page 498 Chapter 13 Inter-Integrated Circuit (IICV3) Block Description • Acknowledge bit generation/detection • Bus busy detection • General Call Address detection • Compliant to ten-bit address S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 499: Modes Of Operation
Chapter 13 Inter-Integrated Circuit (IICV3) Block Description 13.1.2 Modes of Operation The IIC functions the same in normal, special, and emulation modes. It has two low power modes: wait and stop modes. 13.1.3 Block Diagram The block diagram of the IIC module is shown in Figure 13-1.
Page 500: External Signal Description
Chapter 13 Inter-Integrated Circuit (IICV3) Block Description 13.2 External Signal Description The IICV3 module has two external pins. 13.2.1 IIC_SCL — Serial Clock Line Pin This is the bidirectional serial clock line (SCL) of the module, compatible to the IIC bus specification. 13.2.2 IIC_SDA —...
Page 501 Chapter 13 Inter-Integrated Circuit (IICV3) Block Description 13.3.1.1 IIC Address Register (IBAD) Module Base +0x0000 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 Reset = Unimplemented or Reserved Figure 13-3. IIC Bus Address Register (IBAD) Read and write anytime This register contains the address the IIC bus will respond to when addressed as a slave; note that it is not the address sent on the bus during the address transfer.
Page 502 Chapter 13 Inter-Integrated Circuit (IICV3) Block Description Table 13-4. I-Bus Tap and Prescale Values IBC2-0 SCL Tap SDA Tap (bin) (clocks) (clocks) Table 13-5. Prescale Divider Encoding IBC5-3 scl2start scl2stop scl2tap tap2tap (bin) (clocks) (clocks) (clocks) (clocks) Table 13-6. Multiplier Factor IBC7-6 RESERVED The number of clocks from the falling edge of SCL to the first tap (Tap[1]) is defined by the values shown...
Page 503 Chapter 13 Inter-Integrated Circuit (IICV3) Block Description SCL Divider SDA Hold SCL Hold(stop) SCL Hold(start) START condition STOP condition Figure 13-5. SCL Divider and SDA Hold The equation used to generate the divider values from the IBFD bits is: SCL Divider = MUL x {2 x (scl2tap + [(SCL_Tap -1) x tap2tap] + 2)} The SDA hold delay is equal to the CPU clock period multiplied by the SDA Hold value shown in Table 13-7.
Page 504 Chapter 13 Inter-Integrated Circuit (IICV3) Block Description Table 13-7. IIC Divider and Hold Values (Sheet 2 of 6) IBC[7:0] SCL Divider SDA Hold SCL Hold SCL Hold (hex) (clocks) (clocks) (start) (stop) 20/22 22/24 24/26 26/28 28/30 30/32 34/36 40/42 28/32 32/36 36/40...
Page 505 Chapter 13 Inter-Integrated Circuit (IICV3) Block Description Table 13-7. IIC Divider and Hold Values (Sheet 3 of 6) IBC[7:0] SCL Divider SDA Hold SCL Hold SCL Hold (hex) (clocks) (clocks) (start) (stop) 1024 1152 1280 1536 1920 1280 1536 1792 2048 1022 1025...
Page 506 Chapter 13 Inter-Integrated Circuit (IICV3) Block Description Table 13-7. IIC Divider and Hold Values (Sheet 4 of 6) IBC[7:0] SCL Divider SDA Hold SCL Hold SCL Hold (hex) (clocks) (clocks) (start) (stop) 1024 1152 1280 1536 1920 1280 1536 1792 2048 1020 1026...
Page 507 Chapter 13 Inter-Integrated Circuit (IICV3) Block Description Table 13-7. IIC Divider and Hold Values (Sheet 5 of 6) IBC[7:0] SCL Divider SDA Hold SCL Hold SCL Hold (hex) (clocks) (clocks) (start) (stop) 1024 1152 1280 1536 1920 1280 1536 1792 2048 1016 1028...
Page 508 Chapter 13 Inter-Integrated Circuit (IICV3) Block Description Table 13-7. IIC Divider and Hold Values (Sheet 6 of 6) IBC[7:0] SCL Divider SDA Hold SCL Hold SCL Hold (hex) (clocks) (clocks) (start) (stop) 3584 1784 1796 4096 2040 2052 4608 2296 2308 5120 2552...
Page 509 Chapter 13 Inter-Integrated Circuit (IICV3) Block Description Table 13-8. IBCR Field Descriptions Field Description I-Bus Enable — This bit controls the software reset of the entire IIC bus module. IBEN 0 The module is reset and disabled. This is the power-on reset situation. When low the interface is held in reset but registers can be accessed 1 The IIC bus module is enabled.This bit must be set before any other IBCR bits have any effect If the IIC bus module is enabled in the middle of a byte transfer the interface behaves as follows: slave mode...
Page 510 Chapter 13 Inter-Integrated Circuit (IICV3) Block Description from where was during the previous transmission. It is not possible for the IIC to wake up the CPU when its internal clocks are stopped. If it were the case that the IBSWAI bit was cleared when the WAI instruction was executed, the IIC internal clocks and interface would remain alive, continuing the operation which was currently underway.
Page 511 Chapter 13 Inter-Integrated Circuit (IICV3) Block Description Table 13-9. IBSR Field Descriptions (continued) Field Description Reserved — Bit 3 of IBSR is reserved for future use. A read operation on this bit will return 0. RESERVED Slave Read/Write — When IAAS is set this bit indicates the value of the R/W command bit of the calling address sent from the master This bit is only valid when the I-bus is in slave mode, a complete address transfer has occurred with an address match and no other transfers have been initiated.
Page 512: Functional Description
Chapter 13 Inter-Integrated Circuit (IICV3) Block Description 13.3.1.6 IIC Control Register 2(IBCR2) Module Base + 0x0005 GCEN ADTYPE ADR10 ADR9 ADR8 Reset Figure 13-9. IIC Bus Control Register 2(IBCR2) This register contains the variables used in general call and in ten-bit address. Read and write anytime Table 13-10.
Page 513 Chapter 13 Inter-Integrated Circuit (IICV3) Block Description ADR7 ADR6 ADR5 ADR4ADR3 ADR2 ADR1R/W Start Calling Address Read/ Data Byte Signal Write ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1R/W ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1R/W Start Calling Address Read/ Repeated New Calling Address Read/ Start...
Page 514 Chapter 13 Inter-Integrated Circuit (IICV3) Block Description 13.4.1.2 Slave Address Transmission The first byte of data transfer immediately after the START signal is the slave address transmitted by the master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired direction of data transfer.
Page 515 Chapter 13 Inter-Integrated Circuit (IICV3) Block Description 13.4.1.5 Repeated START Signal As shown in Figure 13-10, a repeated START signal is a START signal generated without first generating a STOP signal to terminate the communication. This is used by the master to communicate with another slave or with the same slave in different mode (transmit/receive mode) without releasing the bus.
Page 516 Chapter 13 Inter-Integrated Circuit (IICV3) Block Description 13.4.1.8 Handshaking The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces the master clock into wait states until the slave releases the SCL line.
Page 517: Operation In Run Mode
Chapter 13 Inter-Integrated Circuit (IICV3) Block Description 13.4.1.11 General Call Address To broadcast using a general call, a device must first generate the general call address($00), then after receiving acknowledge, it must transmit data. In communication, as a slave device, provided the GCEN is asserted, a device acknowledges the broadcast and receives data until the GCEN is disabled or the master device releases the bus or generates a new transfer.
Page 518: Application Information
Chapter 13 Inter-Integrated Circuit (IICV3) Block Description — — — IBAL, TCF, IAAS When either of IBAL, TCF or IAAS bits is set Interrupt bits in IBSR may cause an interrupt based on arbitration register lost, transfer complete or address detect conditions Internally there are three types of interrupts in IIC.
Page 519 Chapter 13 Inter-Integrated Circuit (IICV3) Block Description clock and the SCL period it may be necessary to wait until the IIC is busy after writing the calling address to the IBDR before proceeding with the following instructions. This is illustrated in the following example. An example of a program which generates the START signal and transmits the first byte of data (slave address) is shown below: CHFLAG...
Page 520 Chapter 13 Inter-Integrated Circuit (IICV3) Block Description MASTX TXCNT ;GET VALUE FROM THE TRANSMITING COUNTER ;END IF NO MORE DATA BRSET IBSR,#$01,END ;END IF NO ACK MOVB DATABUF,IBDR ;TRANSMIT NEXT BYTE OF DATA TXCNT ;DECREASE THE TXCNT EMASTX ;EXIT BCLR IBCR,#$20 ;GENERATE A STOP CONDITION EMASTX...
Page 521 Chapter 13 Inter-Integrated Circuit (IICV3) Block Description 13.7.1.7 Arbitration Lost If several masters try to engage the bus simultaneously, only one master wins and the others lose arbitration. The devices which lost arbitration are immediately switched to slave receive mode by the hardware.
Page 522 Chapter 13 Inter-Integrated Circuit (IICV3) Block Description Clear IBIF Master Mode Arbitration Tx/Rx Lost Last Byte Clear IBAL Transmitted Last RXAK=0 IAAS=1 IAAS=1 Byte To Be Read 10-bit Data Transfer address? End Of 2nd Last Addr Cycle TX/RX Byte To Be Read (Master Rx) 7-bit address transfer 10-bit address transfer...
Page 523 Chapter 13 Inter-Integrated Circuit (IICV3) Block Description Caution:When IIC is configured as 10-bit address,the point of the data array in interrupt routine must be reset after it’s addressed. S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 524 Chapter 13 Inter-Integrated Circuit (IICV3) Block Description S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 525: Introduction
Chapter 14 Liquid Crystal Display (LCD40F4BV3) Block Description Revision History Table 14-1. LCD40F4BV3 Revision History Version Revision Effective Author Description of Changes Number Date Date 01.00 26-Jul-00 initial LCD module spec 01.08 27-Mar-08 New specification for 9S12HY family based on 9S12H family specification 01.09 25-Apr-08 Update for 9S12HY defining last registers as unimplemented...
Page 526: Features
Chapter 14 Liquid Crystal Display (LCD40F4BV3) Block Description • LCD RAM – contains the data to be displayed on the LCD. Data can be read from or written to the display RAM at any time. • Frontplane Drivers – consists of 40 frontplane drivers. •...
Page 527 Chapter 14 Liquid Crystal Display (LCD40F4BV3) Block Description Internal Address/Data/Clocks RTCCLK Timing Prescaler Control 20 bytes Logic LCD Clock Frontplane Voltage Backplane Drivers Generator Drivers BP[3:0] FP[39:0] VLCD Figure 14-1. LCD40F4BV3 Block Diagram S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 528: External Signal Description
Chapter 14 Liquid Crystal Display (LCD40F4BV3) Block Description 14.2 External Signal Description The LCD40F4BV3 module has a total of 45 external pins. Table 14-2. Signal Properties Name Port Function Reset State 4 backplane waveforms BP[3:0] Backplane waveform signals High impedance that connect directly to the pads 40 frontplane waveforms FP[39:0] Frontplane waveform signals...
Page 529 Chapter 14 Liquid Crystal Display (LCD40F4BV3) Block Description Table 14-3. LCD40F4BV3 Memory Map Address Access Offset 0x0000 LCD Control Register 0 (LCDCR0) Read/Write 0x0001 LCD Control Register 1 (LCDCR1) Read/Write 0x0002 LCD Frontplane Enable Register 0 (LCDFPENR0) Read/Write 0x0003 LCD Frontplane Enable Register 1 (LCDFPENR1) Read/Write 0x0004 LCD Frontplane Enable Register 2 (LCDFPENR2)
Page 530: Register Descriptions
Chapter 14 Liquid Crystal Display (LCD40F4BV3) Block Description 14.3.2 Register Descriptions This section consists of register descriptions. Each description includes a standard register diagram. Details of register bit and field function follow the register diagrams, in bit order. Address Name Bit 7 Bit 6 Bit 5...
Page 531 Chapter 14 Liquid Crystal Display (LCD40F4BV3) Block Description 0x0010 LCDRAM8 FP17BP3 FP17BP2 FP17BP1 FP17BP0 FP16BP3 FP16BP2 FP16BP1 FP16BP0 0x0011 LCDRAM9 FP19BP3 FP19BP2 FP19BP1 FP19BP0 FP18BP3 FP18BP2 FP18BP1 FP18BP0 0x0012 LCDRAM10 FP21BP3 FP21BP2 FP21BP1 FP21BP0 FP20BP3 FP20BP2 FP20BP1 FP20BP0 0x0013 LCDRAM11 FP23BP3 FP23BP2 FP23BP1...
Page 532 Chapter 14 Liquid Crystal Display (LCD40F4BV3) Block Description Write: LCDEN anytime. To avoid segment flicker the clock prescaler bits, the bias select bit and the duty select bits must not be changed when the LCD is enabled. Table 14-4. LCDCR0 Field Descriptions Field Description LCD40F4BV3 Driver System Enable —...
Page 533 Chapter 14 Liquid Crystal Display (LCD40F4BV3) Block Description 14.3.2.2 LCD Control Register 1 (LCDCR1) Module Base + 0x0001 LCDSWAI LCDRSTP Reset Unimplemented or Reserved Figure 14-4. LCD Control Register 1 (LCDCR1) Read: anytime Write: anytime Table 14-5. LCDCR1 Field Descriptions Field Description LCD Stop in Wait Mode —...
Page 534 Chapter 14 Liquid Crystal Display (LCD40F4BV3) Block Description 14.3.2.3 LCD Frontplane Enable Register 0–3 (LCDFPENR0–LCDFPENR4) Module Base + 0x0002 FP7EN FP6EN FP5EN FP4EN FP3EN FP2EN FP1EN FP0EN Reset Figure 14-5. LCD Frontplane Enable Register 0 (LCDFPENR0) Module Base + 0x0003 FP15EN FP14EN FP13EN...
Page 535 Chapter 14 Liquid Crystal Display (LCD40F4BV3) Block Description Table 14-6. LCDFPENR0–LCDFPENR4 Field Descriptions Field Description 39:0 Frontplane Output Enable — The FP[39:0]EN bit enables the frontplane driver outputs. If LCDEN = 0, these FP[39:0]EN bits have no effect on the state of the I/O pins. It is recommended to set FP[39:0]EN bits before LCDEN is set. 0 Frontplane driver output disabled on FP[39:0].
Page 536 Chapter 14 Liquid Crystal Display (LCD40F4BV3) Block Description 0x0011 FP19BP3 FP19BP2 FP19BP1 FP19BP0 FP18BP3 FP18BP2 FP18BP1 FP18BP0 LCDRAM Reset 0x0012 FP21BP3 FP21BP2 FP21BP1 FP21BP0 FP20BP3 FP20BP2 FP20BP1 FP20BP0 LCDRAM Reset 0x0013 FP23BP3 FP23BP2 FP23BP1 FP23BP0 FP22BP3 FP22BP2 FP22BP1 FP22BP0 LCDRAM Reset 0x0014 FP25BP3...
Page 537: Functional Description
Chapter 14 Liquid Crystal Display (LCD40F4BV3) Block Description Table 14-7. LCD RAM Field Descriptions Field Description 39:0 LCD Segment ON — The FP[39:0]BP[3:0] bit displays (turns on) the LCD segment connected between FP[39:0] and BP[3:0]. FP[39:0] 0 LCD segment OFF BP[3:0] 1 LCD segment ON 14.4...
Page 538 Chapter 14 Liquid Crystal Display (LCD40F4BV3) Block Description Table 14-8. LCD Clock and Frame Frequency LCD Clock Source clock Prescaler Frame Frequency [Hz] LCD Clock Frequency in Divider Frequency [Hz] LCLK1 LCLK0 1/1 Duty 1/2 Duty 1/3 Duty 1/4 Duty 1000 1000 500250...
Page 539: Operation In Wait Mode
Chapter 14 Liquid Crystal Display (LCD40F4BV3) Block Description • 1/3 duty (3 backplanes), 1/3 bias (4 voltage levels) • 1/4 duty (4 backplanes), 1/3 bias (4 voltage levels) The voltage levels required for the different operating modes are generated internally based on VLCD. Changing VLCD alters the differential RMS voltage across the segments in the ON and OFF states, thereby setting the display contrast.
Page 540: Lcd Waveform Examples
Chapter 14 Liquid Crystal Display (LCD40F4BV3) Block Description 14.4.4 LCD Waveform Examples Figure 14-11 through Figure 14-15 show the timing examples of the LCD output waveforms for the available modes of operation. S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 541 Chapter 14 Liquid Crystal Display (LCD40F4BV3) Block Description 14.4.4.1 1/1 Duty Multiplexed with 1/1 Bias Mode Duty = 1/1:DUTY1 = 0, DUTY0 = 1 Bias = 1/1:BIAS = 0 or BIAS = 1 = VSSX, V = VLCD - BP1, BP2, and BP3 are not used, a maximum of 40 segments are displayed. 1 Frame VLCD VSSX...
Page 542 Chapter 14 Liquid Crystal Display (LCD40F4BV3) Block Description 14.4.4.2 1/2 Duty Multiplexed with 1/2 Bias Mode Duty = 1/2:DUTY1 = 1, DUTY0 = 0 Bias = 1/2:BIAS = 0 = VSSX, V = VLCD * 1/2, V = VLCD - BP2 and BP3 are not used, a maximum of 80 segments are displayed. 1 Frame VLCD VLCD ...
Page 543 Chapter 14 Liquid Crystal Display (LCD40F4BV3) Block Description 14.4.4.3 1/2 Duty Multiplexed with 1/3 Bias Mode Duty = 1/2:DUTY1 = 1, DUTY0 = 0 Bias = 1/3:BIAS = 1 = VSSX, V = VLCD * 1/3, V = VLCD * 2/3, V = VLCD - BP2 and BP3 are not used, a maximum of 80 segments are displayed.
Page 544 Chapter 14 Liquid Crystal Display (LCD40F4BV3) Block Description 1 Frame VLCD VLCD  2/3 VLCD  1/3 VSSX VLCD VLCD  2/3 VLCD  1/3 VSSX VLCD FPx (xx10) VLCD  2/3 VLCD  1/3 VSSX VLCD FPy (xx00) VLCD  2/3 VLCD ...
Page 545 Chapter 14 Liquid Crystal Display (LCD40F4BV3) Block Description 14.4.4.4 1/3 Duty Multiplexed with 1/3 Bias Mode Duty = 1/3:DUTY1 = 1, DUTY0 = 1 Bias = 1/3:BIAS = 0 or BIAS = 1 = VSSX, V = VLCD * 1/3, V = VLCD * 2/3, V = VLCD - BP3 is not used, a maximum of 120 segments are displayed.
Page 546: Lcd Clock Inputs & Reset Behavior
Chapter 14 Liquid Crystal Display (LCD40F4BV3) Block Description 14.4.4.5 1/4 Duty Multiplexed with 1/3 Bias Mode Duty = 1/4:DUTY1 = 0, DUTY0 = 0 Bias = 1/3:BIAS = 0 or BIAS = 1 = VSSX, V = VLCD * 1/3, V = VLCD * 2/3, V = VLCD - A maximum of 160 segments are displayed.
Page 547: Resets
Chapter 14 Liquid Crystal Display (LCD40F4BV3) Block Description 14.5 Resets The reset values of registers and signals are described in Section 14.3, “Memory Map and Register Definition”. The behavior of the LCD40F4BV3 system during reset is described in Section 14.4.1, “LCD Driver Description”.
Page 548 Chapter 14 Liquid Crystal Display (LCD40F4BV3) Block Description S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 549: Introduction
Chapter 15 Serial Communication Interface (S12SCIV6) Table 15-1. Revision History Version Revision Effective Author Description of Changes Number Date Date 05.03 12/25/2008 remove redundancy comments in Figure1-2 fix typo, SCIBDL reset value be 0x04, not 0x00 05.04 08/05/2009 fix typo, Table 15-3,SCICR1 Even parity should be PT=0 05.05...
Page 550: S12Zvh Family Reference Manual, Rev. 1.05 Freescale Semiconductor
Chapter 15 Serial Communication Interface (S12SCIV6) LIN: Local Interconnect Network LSB: Least Significant Bit MSB: Most Significant Bit NRZ: Non-Return-to-Zero RZI: Return-to-Zero-Inverted RXD: Receive Pin SCI : Serial Communication Interface TXD: Transmit Pin 15.1.2 Features The SCI includes these distinctive features: •...
Page 551: Modes Of Operation
Chapter 15 Serial Communication Interface (S12SCIV6) • Receiver framing error detection • Hardware parity checking • 1/16 bit-time noise detection 15.1.3 Modes of Operation The SCI functions the same in normal, special, and emulation modes. It has two low power modes, wait and stop modes.
Page 552: External Signal Description
Chapter 15 Serial Communication Interface (S12SCIV6) 15.2 External Signal Description The SCI module has a total of two external pins. 15.2.1 TXD — Transmit Pin The TXD pin transmits SCI (standard or infrared) data. It will idle high in either mode and is high impedance anytime the transmitter is disabled.
Page 553: Register Descriptions
Chapter 15 Serial Communication Interface (S12SCIV6) 15.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Writes to a reserved register locations do not have any effect and reads of these locations return a zero.
Page 554 Chapter 15 Serial Communication Interface (S12SCIV6) 15.3.2.1 SCI Baud Rate Registers (SCIBDH, SCIBDL) Module Base + 0x0000 SBR15 SBR14 SBR13 SBR12 SBR11 SBR10 SBR9 SBR8 Reset Figure 15-3. SCI Baud Rate Register (SCIBDH) Module Base + 0x0001 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2...
Page 555 Chapter 15 Serial Communication Interface (S12SCIV6) 15.3.2.2 SCI Control Register 1 (SCICR1) Module Base + 0x0002 LOOPS SCISWAI RSRC WAKE Reset Figure 15-5. SCI Control Register 1 (SCICR1) Read: Anytime, if AMAP = 0. Write: Anytime, if AMAP = 0. NOTE This register is only visible in the memory map if AMAP = 0 (reset condition).
Page 556 Chapter 15 Serial Communication Interface (S12SCIV6) Table 15-3. SCICR1 Field Descriptions (continued) Field Description Parity Enable Bit — PE enables the parity function. When enabled, the parity function inserts a parity bit in the most significant bit position. 0 Parity function disabled 1 Parity function enabled Parity Type Bit —...
Page 557 Chapter 15 Serial Communication Interface (S12SCIV6) 15.3.2.3 SCI Alternative Status Register 1 (SCIASR1) Module Base + 0x0000 BERRV RXEDGIF BERRIF BKDIF Reset = Unimplemented or Reserved Figure 15-6. SCI Alternative Status Register 1 (SCIASR1) Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 Table 15-5.
Page 558 Chapter 15 Serial Communication Interface (S12SCIV6) 15.3.2.4 SCI Alternative Control Register 1 (SCIACR1) Module Base + 0x0001 RXEDGIE BERRIE BKDIE Reset = Unimplemented or Reserved Figure 15-7. SCI Alternative Control Register 1 (SCIACR1) Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 Table 15-6.
Page 559 Chapter 15 Serial Communication Interface (S12SCIV6) 15.3.2.5 SCI Alternative Control Register 2 (SCIACR2) Module Base + 0x0002 IREN TNP1 TNP0 BERRM1 BERRM0 BKDFE Reset = Unimplemented or Reserved Figure 15-8. SCI Alternative Control Register 2 (SCIACR2) Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 Table 15-7.
Page 560 Chapter 15 Serial Communication Interface (S12SCIV6) 15.3.2.6 SCI Control Register 2 (SCICR2) Module Base + 0x0003 TCIE ILIE Reset Figure 15-9. SCI Control Register 2 (SCICR2) Read: Anytime Write: Anytime Table 15-10. SCICR2 Field Descriptions Field Description Transmitter Interrupt Enable Bit — TIE enables the transmit data register empty flag, TDRE, to generate interrupt requests.
Page 561 Chapter 15 Serial Communication Interface (S12SCIV6) 15.3.2.7 SCI Status Register 1 (SCISR1) The SCISR1 and SCISR2 registers provides inputs to the MCU for generation of SCI interrupts. Also, these registers can be polled by the MCU to check the status of these bits. The flag-clearing procedures require that the status register be read followed by a read or write to the SCI data register.It is permissible to execute other instructions between the two steps as long as it does not compromise the handling of I/O, but the order of operations is important for flag clearing.
Page 562 Chapter 15 Serial Communication Interface (S12SCIV6) Table 15-11. SCISR1 Field Descriptions (continued) Field Description Overrun Flag — OR is set when software fails to read the SCI data register before the receive shift register receives the next frame. The OR bit is set immediately after the stop bit has been completely received for the second frame.
Page 563 Chapter 15 Serial Communication Interface (S12SCIV6) 15.3.2.8 SCI Status Register 2 (SCISR2) Module Base + 0x0005 AMAP TXPOL RXPOL BRK13 TXDIR Reset = Unimplemented or Reserved Figure 15-11. SCI Status Register 2 (SCISR2) Read: Anytime Write: Anytime Table 15-12. SCISR2 Field Descriptions Field Description Alternative Map —...
Page 564 Chapter 15 Serial Communication Interface (S12SCIV6) 15.3.2.9 SCI Data Registers (SCIDRH, SCIDRL) Module Base + 0x0006 Reserved Reserved Reserved Reset = Unimplemented or Reserved Figure 15-12. SCI Data Registers (SCIDRH) Module Base + 0x0007 Reset Figure 15-13. SCI Data Registers (SCIDRL) Read: Anytime;...
Page 565 Chapter 15 Serial Communication Interface (S12SCIV6) When transmitting in 9-bit data format and using 8-bit write instructions, write first to SCI data register high (SCIDRH), then SCIDRL. S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 566: Functional Description
Chapter 15 Serial Communication Interface (S12SCIV6) 15.4 Functional Description This section provides a complete functional description of the SCI block, detailing the operation of the design from the end user perspective in a number of subsections. Figure 15-14 shows the structure of the SCI module. The SCI allows full duplex, asynchronous, serial communication between the CPU and remote devices, including other CPUs.
Page 567: Infrared Interface Submodule
Chapter 15 Serial Communication Interface (S12SCIV6) 15.4.1 Infrared Interface Submodule This module provides the capability of transmitting narrow pulses to an IR LED and receiving narrow pulses and transforming them to serial bits, which are sent to the SCI. The IrDA physical layer specification defines a half-duplex infrared communication link for exchange data.
Page 568: Data Format
Chapter 15 Serial Communication Interface (S12SCIV6) 15.4.3 Data Format The SCI uses the standard NRZ mark/space data format. When Infrared is enabled, the SCI uses RZI data format where zeroes are represented by light pulses and ones remain low. See Figure 15-15 below.
Page 569: Baud Rate Generation
Chapter 15 Serial Communication Interface (S12SCIV6) 1. The address bit identifies the frame as an address character. See Section 15.4.6.6, “Receiver Wakeup”. 15.4.4 Baud Rate Generation A 16-bit modulus counter in the two baud rate generator derives the baud rate for both the receiver and the transmitter.
Page 570: Transmitter
Chapter 15 Serial Communication Interface (S12SCIV6) 15.4.5 Transmitter Internal Bus Transmit baud 16 SCI Data Registers Clock generator SBR15:SBR4 SBR3:SBR0 TXPOL 11-Bit Transmit Register SCTXD LOOP To R eceiver CONTROL Parity LOOPS Generation RSRC TDRE IRQ TDRE Transmitter Control TC IRQ TCIE BERRM[1:0] SCTXD...
Page 571 Chapter 15 Serial Communication Interface (S12SCIV6) The SCI also sets a flag, the transmit data register empty flag (TDRE), every time it transfers data from the buffer (SCIDRH/L) to the transmitter shift register.The transmit driver routine may respond to this flag by writing another byte to the Transmitter buffer (SCIDRH/SCIDRL), while the shift register is still shifting out the first byte.
Page 572 Chapter 15 Serial Communication Interface (S12SCIV6) When the transmit shift register is not transmitting a frame, the TXD pin goes to the idle condition, logic 1. If at any time software clears the TE bit in SCI control register 2 (SCICR2), the transmitter enable signal goes low and the transmit signal goes idle.
Page 573 Chapter 15 Serial Communication Interface (S12SCIV6) Figure 15-17 shows two cases of break detect. In trace RXD_1 the break symbol starts with the start bit, while in RXD_2 the break starts in the middle of a transmission. If BRKDFE = 1, in RXD_1 case there will be no byte transferred to the receive buffer and the RDRF flag will not be modified.
Page 574 Chapter 15 Serial Communication Interface (S12SCIV6) 15.4.5.5 LIN Transmit Collision Detection This module allows to check for collisions on the LIN bus. LIN Physical Interface Synchronizer Stage Receive Shift Register Compare RXD Pin Bit Error LIN Bus Bus Clock Sample Point Transmit Shift Register...
Page 575: Receiver
Chapter 15 Serial Communication Interface (S12SCIV6) 15.4.6 Receiver Internal Bus SBR15:SBR4 SBR3:SBR0 SCI Data Register Receive Baud Clock Generator 11-Bit Receive Shift Register RXPOL Data Recovery SCRXD Loop From TXD Pin Control or Transmitter LOOPS RSRC WAKE Wakeup Logic Parity Checking Idle IRQ IDLE...
Page 576 Chapter 15 Serial Communication Interface (S12SCIV6) indicating that the received byte can be read. If the receive interrupt enable bit, RIE, in SCI control register 2 (SCICR2) is also set, the RDRF flag generates an RDRF interrupt request. 15.4.6.3 Data Sampling The RT clock rate.
Page 577 Chapter 15 Serial Communication Interface (S12SCIV6) To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 15-18 summarizes the results of the data bit samples. Table 15-18. Data Bit Recovery RT8, RT9, and RT10 Samples Data Bit Determination Noise Flag...
Page 578 Chapter 15 Serial Communication Interface (S12SCIV6) Figure 15-22 the verification samples RT3 and RT5 determine that the first low detected was noise and not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise flag is not set because the noise occurred before the start bit was found.
Page 579 Chapter 15 Serial Communication Interface (S12SCIV6) Figure 15-24, a large burst of noise is perceived as the beginning of a start bit, although the test sample at RT5 is high. The RT5 sample sets the noise flag. Although this is a worst-case misalignment of perceived bit time, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful.
Page 580 Chapter 15 Serial Communication Interface (S12SCIV6) Figure 15-26 shows a burst of noise near the beginning of the start bit that resets the RT clock. The sample after the reset is low but is not preceded by three high samples that would qualify as a falling edge. Depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may set the framing error flag.
Page 581 Chapter 15 Serial Communication Interface (S12SCIV6) 15.4.6.5 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data samples (RT8, RT9, and RT10) to fall outside the actual stop bit.
Page 582 Chapter 15 Serial Communication Interface (S12SCIV6) 15.4.6.5.2 Fast Data Tolerance Figure 15-29 shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10 instead of RT16 but is still sampled at RT8, RT9, and RT10. Stop Idle or Next Frame Receiver...
Page 583: Single-Wire Operation
Chapter 15 Serial Communication Interface (S12SCIV6) The transmitting device can address messages to selected receivers by including addressing information in the initial frame or frames of each message. The WAKE bit in SCI control register 1 (SCICR1) determines how the SCI is brought out of the standby state to process an incoming message.
Page 584: Loop Operation
Chapter 15 Serial Communication Interface (S12SCIV6) Transmitter Receiver Figure 15-30. Single-Wire Operation (LOOPS = 1, RSRC = 1) Enable single-wire operation by setting the LOOPS bit and the receiver source bit, RSRC, in SCI control register 1 (SCICR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Setting the RSRC bit connects the TXD pin to the receiver.
Page 585: Modes Of Operation
Chapter 15 Serial Communication Interface (S12SCIV6) 15.5.2 Modes of Operation 15.5.2.1 Run Mode Normal mode of operation. To initialize a SCI transmission, see Section 15.4.5.2, “Character Transmission”. 15.5.2.2 Wait Mode SCI operation in wait mode depends on the state of the SCISWAI bit in the SCI control register 1 (SCICR1).
Page 586 Chapter 15 Serial Communication Interface (S12SCIV6) Table 15-20. SCI Interrupt Sources RXEDGIF SCIASR1[7] RXEDGIE Active high level. Indicates that an active edge (falling for RXPOL = 0, rising for RXPOL = 1) was detected. BERRIF SCIASR1[1] BERRIE Active high level. Indicates that a mismatch between transmitted and received data in a single wire application has happened.
Page 587 Chapter 15 Serial Communication Interface (S12SCIV6) 15.5.3.1 Description of Interrupt Operation The SCI only originates interrupt requests. The following is a description of how the SCI makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt number are chip dependent.
Page 588: Recovery From Wait Mode
Chapter 15 Serial Communication Interface (S12SCIV6) 15.5.3.1.6 RXEDGIF Description The RXEDGIF interrupt is set when an active edge (falling if RXPOL = 0, rising if RXPOL = 1) on the RXD pin is detected. Clear RXEDGIF by writing a “1” to the SCIASR1 SCI alternative status register 1. 15.5.3.1.7 BERRIF Description The BERRIF interrupt is set when a mismatch between the transmitted and the received data in a single...
Page 589: Introduction
Chapter 16 Motor Controller (MC10B8CV1) Table 16-1. Revision History Version Revision Author Description of Changes Number Date V01.01 6-OCT-2009 Table 16-12 - fixed 2nd content row : MnCyP := PWM - fixed 4th content row : MnCyP := 0 16.1 Introduction The block MC10B8C is a PWM motor controller suitable to drive instruments in a cluster configuration or any other loads requiring a PWM signal.
Page 590 Chapter 16 Motor Controller (MC10B8CV1) 16.1.2.1.2 Dither Function Dither function can be selected or deselected by setting or clearing the DITH bit. This bit influences all PWM channels. For details, please refer to Section 16.4.1.3.5, “Dither Bit (DITH)”. 16.1.2.2 PWM Channel Configuration Modes The eight PWM channels can operate in three functional modes.
Page 591: Block Diagram
Chapter 16 Motor Controller (MC10B8CV1) 16.1.3 Block Diagram Control Registers Period Register FAST 11-Bit Timer/Counter DITH PWM Channel Pair PWM Channel M0C0M Duty Register 0 Comparator M0C0P M0C1M Duty Register 1 Comparator M0C1P M1C0M Duty Register 2 Comparator M1C0P M1C1M Duty Register 3 Comparator M1C1P...
Page 592: External Signal Description
Chapter 16 Motor Controller (MC10B8CV1) 16.2 External Signal Description The motor controller is associated with 16 pins. Table 16-2 lists the relationship between the PWM channels and signal pins as well as PWM channel pair (motor number), coils, and nodes they are supposed to drive if all channels are set to dual full H-bridge configuration.
Page 593: M3C0M/M3C0P/M3C1M/M3C1P — Pwm Output Pins For Motor 3
Chapter 16 Motor Controller (MC10B8CV1) to a logic high state. PWM output on M2C1M results in a positive current flow through coil 1 when M2C1P is driven to a logic high state. 16.2.4 M3C0M/M3C0P/M3C1M/M3C1P — PWM Output Pins for Motor 3 High current PWM output pins that can be used for motor drive.
Page 594 Chapter 16 Motor Controller (MC10B8CV1) Figure 16-2. MC10B8C Memory Map (continued) Offset Register Access 0x0016 Motor Controller Channel Control Register 6 (MCCC6) 0x0017 Motor Controller Channel Control Register 7 (MCCC7) 0x0018 Reserved — 0x0019 Reserved — 0x001A Reserved — 0x001B Reserved —...
Page 595: Register Descriptions
Chapter 16 Motor Controller (MC10B8CV1) Figure 16-2. MC10B8C Memory Map (continued) Offset Register Access 0x003E Reserved — 0x003F Reserved — 1. Write accesses to “Reserved” addresses have no effect. Read accesses to “Reserved” addresses provide invalid data (0x0000). 16.3.2 Register Descriptions 16.3.2.1 Motor Controller Control Register 0 This register controls the operating mode of the motor controller module.
Page 596 Chapter 16 Motor Controller (MC10B8CV1) Table 16-4. Prescaler Values MCPRE[1:0] 16.3.2.2 Motor Controller Control Register 1 This register controls the behavior of the analog section of the motor controller as well as the interrupt enables. Offset Module Base + 0x0001 RECIRC MCTOIE Reset...
Page 597 Chapter 16 Motor Controller (MC10B8CV1) 16.3.2.3 Motor Controller Period Register The period register defines PER, the number of motor controller timer counter clocks a PWM period lasts. The motor controller timer counter is clocked with the frequency f . If dither mode is enabled (DITH = 1, refer to Section 16.4.1.3.5, “Dither Bit (DITH)”), P0 is ignored and reads as a 0.
Page 598 Chapter 16 Motor Controller (MC10B8CV1) 16.3.2.4 Motor Controller Channel Control Registers Each PWM channel has one associated control register to control output delay, PWM alignment, and output mode. The registers are named MCCC0... MCCC7. In the following, MCCC0 is described as a reference for all eight registers.
Page 599 Chapter 16 Motor Controller (MC10B8CV1) Table 16-9. Channel Delay CD[1:0] n [# of PWM Clocks] NOTE The PWM motor controller will release the pins after the next PWM timer counter overflow without accommodating any channel delay if a single channel has been disabled or if the period register has been cleared or all channels have been disabled.
Page 600 Chapter 16 Motor Controller (MC10B8CV1) Offset Module Base + 0x0020 . . . 0x002F Access: User read/write Reset = Unimplemented or Reserved Figure 16-9. Motor Controller Duty Cycle Register x (MCDCx) with FAST = 1 Table 16-10. MCDCx Field Descriptions Field Description SIGN —...
Page 601: Functional Description
Chapter 16 Motor Controller (MC10B8CV1) 16.4 Functional Description 16.4.1 Modes of Operation 16.4.1.1 PWM Output Modes The motor controller is configurable between three output modes. • Dual full H-bridge mode can be used to control either a stepper motor or a 360 air core instrument. In this case two PWM channels are combined.
Page 602 Chapter 16 Motor Controller (MC10B8CV1) Table 16-11. Corresponding Registers and Pin Names for Each PWM Channel Pair (continued) Duty Cycle Channel Channel Channel Control Register Number Names Pair Number Register MCMC2 MCDC2 PWM Channel 2 M1C0M M1C0P MCMC3 MCDC3 PWM Channel 3 M1C1M M1C1P MCMC4...
Page 603 Chapter 16 Motor Controller (MC10B8CV1) MnC0P PWM Channel x MnC0M Motor n, Coil 0 Motor n, Coil 1 MnC1P PWM Channel x + 1 MnC1M Figure 16-10. Typical Dual Full H-Bridge Mode Configuration Whenever FAST = 0 only 16-bit write accesses to the duty cycle registers are allowed, 8-bit write accesses can lead to unpredictable duty cycles.
Page 604 Chapter 16 Motor Controller (MC10B8CV1) Released MnC0P PWM Channel x MnC0M PWM Output Released MnC1P PWM Channel x + 1 MnC1M PWM Output Figure 16-11. Typical Quad Half H-Bridge Mode Configuration 16.4.1.2 Relationship Between PWM Mode and PWM Channel Enable The pair of motor controller channels cannot be placed into dual full H-bridge mode unless both motor controller channels have been enabled (MCAM[1:0] not equal to 00) and dual full H-bridge mode is selected for both PWM channels (MCOM[1:0] = 11).
Page 605 Chapter 16 Motor Controller (MC10B8CV1) Motor Controller Timer Counter Clock Motor Controller Timer Counter PWM Output 1 Period 1 Period 100 Counts 100 Counts DITH = 0, MCAM[1:0] = 01, MCDCx = 15, MCPER = 100, RECIRC = 0 Right aligned (MCAM[1:0] = 10): The output will start inactive (high if RECIRC = 0 and low if RECIRC = 1) and will turn active after the number of counts specified by the difference of the contents of period register and the corresponding duty cycle register.
Page 606 Chapter 16 Motor Controller (MC10B8CV1) 16.4.1.3.2 Sign Bit (S) Assuming RECIRC = 0 (the active state of the PWM signal is low), when the S bit for the corresponding channel is cleared, MnC0P (if the PWM channel number is even, n = 0, 1, 2, 3, see Table 16-11) or MnC1P (if the PWM channel number is odd, n = 0, 1, 2, 3, see...
Page 607 Chapter 16 Motor Controller (MC10B8CV1) Static 0 PWM 1 MnC0P MnC0M Static 0 PWM 1 Figure 16-12. PWM Active Phase, RECIRC = 0, S = 0 Static 0 PWM 0 MnC0P MnC0M Static 0 PWM 0 Figure 16-13. PWM Passive Phase, RECIRC = 0, S = 0 S12ZVH Family Reference Manual, Rev.
Page 608 Chapter 16 Motor Controller (MC10B8CV1) Static 1 PWM 0 MnC0P MnC0M Static 1 PWM 0 Figure 16-14. PWM Active Phase, RECIRC = 1, S = 0 Static 1 PWM 1 MnC0P MnC0M Static 1 PWM 1 Figure 16-15. PWM Passive Phase, RECIRC = 1, S = 0 S12ZVH Family Reference Manual, Rev.
Page 609 Chapter 16 Motor Controller (MC10B8CV1) 16.4.1.3.4 Relationship Between RECIRC Bit, S Bit, MCOM Bits, PWM State, and Output Transistors Please refer to Figure 16-16 for the output transistor assignment. MnCyP MnCyM Figure 16-16. Output Transistor Assignment Table 16-13 illustrates the state of the output transistors in different states of the PWM motor controller module.
Page 610 Chapter 16 Motor Controller (MC10B8CV1) 16.4.1.3.5 Dither Bit (DITH) The purpose of the dither mode is to increase the minimum length of output pulses without decreasing the PWM resolution, in order to limit the pulse distortion introduced by the slew rate control of the outputs. If dither mode is selected the output pattern will repeat after two timer counter overflows.
Page 611 Chapter 16 Motor Controller (MC10B8CV1) value, DUTY, contained in D[10:1] in MCDCx. When a match (output compare between motor controller timer counter and DUTY) occurs, the PWM output will toggle to a logic high level and will remain at a logic high level until the motor controller timer counter overflows (reaches the value defined by P[10:1] –...
Page 612 Chapter 16 Motor Controller (MC10B8CV1) Motor Controller Timer Counter Clock Motor Controller Timer Counter PWM Output 1 Period 100 Counts 100 Counts Figure 16-19. PWM Output: DITH = 1, MCAM[1:0] = 01, MCDC = 30, MCPER = 200, RECIRC = 0 Motor Controller Timer Counter Clock...
Page 613: Pwm Duty Cycle
Chapter 16 Motor Controller (MC10B8CV1) 16.4.2 PWM Duty Cycle The PWM duty cycle for the motor controller channel x can be determined by dividing the decimal representation of bits D[10:0] in MCDCx by the decimal representation of the bits P[10:0] in MCPER and multiplying the result by 100% as shown in the equation below: DUTY -------------------- - 100%...
Page 614: Output Switching Delay
Chapter 16 Motor Controller (MC10B8CV1) The motor controller channel frequency of operation can be calculated using the following formula if DITH = 1: ------------------------------------- - Motor Channel Frequency (Hz) MCPER M 2   NOTE Both equations are only valid if MCPER is not equal to 0. M = 1 for left or right aligned mode, M = 2 for center aligned mode.
Page 615: Operation In Wait Mode
Chapter 16 Motor Controller (MC10B8CV1) 16.4.5 Operation in Wait Mode During wait mode, the operation of the motor controller pins are selectable between the following two options: 1. MCSWAI = 1: All module clocks are stopped and the associated port pins are set to their inactive state, which is defined by the state of the RECIRC bit during wait mode.
Page 616: Initialization/Application Information
Chapter 16 Motor Controller (MC10B8CV1) 16.7 Initialization/Application Information This section provides an example of how the PWM motor controller can be initialized and used by application software. The configuration parameters (e.g., timer settings, duty cycle values, etc.) are not guaranteed to be adequate for any real application. The example software is implemented in assembly language.
Page 617 Chapter 16 Motor Controller (MC10B8CV1) ;------------------------------------------------------------------------------------------ ; Motor Controller (MC10B8C) setup example ;------------------------------------------------------------------------------------------ ; Timer defines ;------------------------------------------------------------------------------------------ T_START $0040 TSCR1 T_START+$06 TFLG2 T_START+$0F ;------------------------------------------------------------------------------------------ ; Motor Controller defines ;------------------------------------------------------------------------------------------ MC_START $0200 MCCTL0 MC_START+$00 MCCTL1 MC_START+$01 MCPER_HI MC_START+$02 MCPER_LO MC_START+$03 MCCC0 MC_START+$10 MCCC1 MC_START+$11...
Page 618 Chapter 16 Motor Controller (MC10B8CV1) ;------------------------------------------------------------------------------------------ ;global motor controller init ;------------------------------------------------------------------------------------------ GLB_INIT: MOVB #$0000,MCCTL0 ; fMC = fBUS, FAST=0, DITH=0 MOVB #$0000,MCCTL1 ; RECIRC=0, MCTOIE=0 MOVW #$D0D0,MCCC0 ; dual full h-bridge mode, left aligned, ; no channel delay MOVW #$0000,MCPER_HI ;...
Page 619 Chapter 16 Motor Controller (MC10B8CV1) ;------------------------------------------------------------------------------------------ ; motor controller duty cycles ;------------------------------------------------------------------------------------------ DTYDAT DC.B $02, $FF ; MCDC1_HI, MCDC1_LO DC.B $02, $D0 ; MCDC0_HI, MCDC0_LO DC.B $02, $A0 ; MCDC1_HI, MCDC1_LO DC.B $02, $90 ; MCDC0_HI, MCDC0_LO DC.B $02, $60 ; MCDC1_HI, MCDC1_LO DC.B $02, $25 ;...
Page 620 Chapter 16 Motor Controller (MC10B8CV1) S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 621: Introduction
Chapter 17 Stepper Stall Detector (SSDV2) Block Description Table 17-1. SSDV2 Revision History Revision Sections Revision Date Description of Changes Number Affected V02.00 1st Aug 2011 -remove the SMS bit in RTZCTL register 17.1 Introduction The stepper stall detector (SSD) block provides a circuit to measure and integrate the induced voltage on the non-driven coil of a stepper motor using full steps when the gauge pointer is returning to zero (RTZ).
Page 622: Block Diagram
Chapter 17 Stepper Stall Detector (SSDV2) Block Description • 16-bit modulus down counter with interrupt 17.1.3 Block Diagram Coil COS Coil SIN VDDM VDDM VDDM VDDM COSM SINP SINM COSP VSSM VSSM VSSM VSSM reference integrator – – 16-bit accumulator VDDM register 16-bit load...
Page 623: External Signal Description
Chapter 17 Stepper Stall Detector (SSDV2) Block Description 17.2 External Signal Description Each SSD signal is the output pin of a half bridge, designed to source or sink current. The H-bridge pins drive the sine and cosine coils of a stepper motor to provide four-quadrant operation. Table 17-2.
Page 624: Memory Map And Register Definition
Chapter 17 Stepper Stall Detector (SSDV2) Block Description 17.3 Memory Map and Register Definition This section provides a detailed description of all registers of the stepper stall detector (SSD) block. 17.3.1 Module Memory Map Table 17-3 gives an overview of all registers in the SSDV2 memory map. The SSDV2 occupies eight bytes in the memory space.
Page 625 Chapter 17 Stepper Stall Detector (SSDV2) Block Description 17.3.2.1 Return-to-Zero Control Register (RTZCTL) Module Base + 0x0000 DCOIL RCIR STEP Reset = Unimplemented or Reserved Figure 17-2. Return-to-Zero Control Register (RTZCTL) Read: anytime Write: anytime Table 17-4. RTZCTL Field Descriptions Field Description Integration —...
Page 626 Chapter 17 Stepper Stall Detector (SSDV2) Block Description Table 17-5. Transistor Condition States (RTZE = 1) STEP DCOIL RCIR Table 17-6. Switch Condition States (RTZE = 1 or 0) STEP Open Open Open Open Open Open Open Open Open Open Open Open Close...
Page 627 Chapter 17 Stepper Stall Detector (SSDV2) Block Description Table 17-7. Full Step States Coil Node to Coil Node to COSINE SINE Integrator input Reference input Coil Current Coil Current (Close Switch) (Close Switch) STEP Pole Angle ITG = 1 ITG = 1 ITG = 1 ITG = 1 DCOIL = 0 DCOIL = 1 DCOIL = 0 DCOIL = 1...
Page 628 Chapter 17 Stepper Stall Detector (SSDV2) Block Description Table 17-8. MDCCTL Field Descriptions (continued) Field Description Prescaler 0 The modulus down counter clock frequency is the bus frequency divided by 64. 1 The modulus down counter clock frequency is the bus frequency divided by 512. Note: A change in the prescaler division rate will not be effective until a load of the load register into the modulus counter count register occurs.
Page 629 Chapter 17 Stepper Stall Detector (SSDV2) Block Description Table 17-9. SSDCTL Field Descriptions (continued) Field Description SSD Disabled during Wait Mode — When entering Wait Mode, this bit provides on/off control over the SSD SSDWAI allowing reduced MCU power consumption. Because the analog circuit is turned off when powered down, the sigma-delta converter requires a recovery time after exit from Wait Mode.
Page 630 Chapter 17 Stepper Stall Detector (SSDV2) Block Description Table 17-11. SSDFLG Field Descriptions Field Description Modulus Counter Underflow Interrupt Flag — This flag is set when the modulus down-counter reaches MCZIF 0x0000. If not masked (MCZIE = 1), a modulus counter underflow interrupt is pending while this flag is set. This flag is cleared by writing a ‘1’...
Page 631: Functional Description
Chapter 17 Stepper Stall Detector (SSDV2) Block Description underflow. The FLMC bit in the MDCCTL register can be used to immediately update the count register with the new value if an immediate load is desired. The modulus down counter clock frequency is the bus frequency divided by 64 or 512. 17.3.2.6 Integration Accumulator Register (ITGACC) Module Base + 0x0006...
Page 632: Return To Zero Modes
Chapter 17 Stepper Stall Detector (SSDV2) Block Description 17.4.1 Return to Zero Modes There are four return to zero modes as shown in Table 17-12. Table 17-12. Return to Zero Modes DCOIL Mode Blanking with no drive Blanking with drive Conversion Integration 17.4.1.1...
Page 633 Chapter 17 Stepper Stall Detector (SSDV2) Block Description 0 and so on. Figure 17-10 shows the current level through each coil for each full step in CCW rotation when DCOIL is set. Imax SINE COIL CURRENT Imax Recirculation Imax COSINE COIL CURRENT _ Imax Figure 17-10.
Page 634 Chapter 17 Stepper Stall Detector (SSDV2) Block Description VDDM VDDM COSP COSM SINP SINM VSSM VSSM Figure 17-12. Current Flow when STEP = 1, DCOIL = 1, ITG = 0, RCIR = 1 Figure 17-13 shows the current flow in the SIN and COS H-bridges when STEP = 2, DCOIL = 1 and ITG = 1.
Page 635 Chapter 17 Stepper Stall Detector (SSDV2) Block Description VDDM VDDM COSP COSM SINP SINM VSSM VSSM Figure 17-14. Current flow when STEP = 3, DCOIL = 1, ITG = 1 S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 636: Operation In Low Power Modes
Chapter 17 Stepper Stall Detector (SSDV2) Block Description 17.4.3 Operation in Low Power Modes The SSD block can be configured for lower MCU power consumption in three different ways. • Stop mode powers down the sigma-delta converter and halts clock to the modulus counter. Exit from Stop enables the sigma-delta converter and the clock to the modulus counter but due to the converter recovery time, the integration result should be ignored.
Page 637 Chapter 17 Stepper Stall Detector (SSDV2) Block Description Using Motor Control module, drive pointer to within 3 full steps of Advance Pointer calibrated zero position. 1. Clear (or set) RCIR; clear (or set) POL; Initialize SSD 2. Set MCZIE; clear MODMC; clear (or set) PRE; set MCEN. 3.
Page 638 Chapter 17 Stepper Stall Detector (SSDV2) Block Description S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 639: Introduction
Chapter 18 Real-Time Counter With Calendar (RTCV2) Table 18-1. Revision History Version Revision Sections Affected Description of Changes Number Date April 2011 • inital Draft March 2011 • fix typo on 18.1,18.2,18.3.4,18.5.3,18.5.6,18.6.1.1 March 2011 • V2 spec,add clock source of IRCCLK, Figure 18-1./18-641, 18.3.3/18-642,...
Page 640: Block Diagram
Chapter 18 Real-Time Counter With Calendar (RTCV2) 18.2.1.1 Wait Mode The RTC continues to run in wait mode if enabled before executing the WAIT instruction. Therefore, the RTC can be used to bring the MCU out of wait mode if the real-time interrupt is enabled. For lowest possible current consumption, the RTC should be stopped by software if not needed as an interrupt source during wait mode.
Page 641: External Signal Description
Chapter 18 Real-Time Counter With Calendar (RTCV2) RTCMOD COMPE 16-bit modulo Compensation Circuit 16-bit latch 16-bit modulo Comparator 16-bit comparator OSCCLK CLKSRC CLKSRC 16-bit counter 1/(RTCPS+1) 1/32 CALS RTCCLK IRCCLK CALCLK RTCCNT OSCCLK_32K COMPIE compensation cycle COMPF TB0IE 4 HZ TB0F 1 Hz Interrupt...
Page 642: Oscclk_32K
Chapter 18 Real-Time Counter With Calendar (RTCV2) 18.3.2 OSCCLK_32K The OSCCLK_32K is 32.768K OSC output. 18.3.3 IRCCLK The IRCCLK is 1MHz CPMU output. 18.3.4 RTCCLK The RTCCLK can run from OSCCLK or OSCCLK_32K. It depends on the CLKSRC setting . If derived from OSCCLK, it depends on the RTCPS settting also.
Page 643: Rtc Control Register 1(Rtcctl1)
Chapter 18 Real-Time Counter With Calendar (RTCV2) Table 18-2. RTC Register Summary (continued) Name 0x0006 RTCMODH RTCMODH 0x0007 RTCMODL RTCMODL RTCCNTH 0x0008 RTCCNTH RTCCNTL 0x0009 RTCCNTL 0x000A - 0x000C RESERVED 0x000D SEC5 SEC4 SEC3 SEC2 SEC1 SEC0 RTCSECR 0x000E MIN5 MIN4 MIN3 MIN2...
Page 644: Rtc Control Register 2 (Rtcctl2)
Chapter 18 Real-Time Counter With Calendar (RTCV2) Table 18-3. RTCCTL1 Field Descriptions Field Description RTC Enable — This read/write bit enables the RTC. RTCEN 0 RTC function is disabled. 1 RTC function is enabled. RTC Compensation Enable— The read/write bit enables the clock compensation mechanism for clock COMPE frequency errors.
Page 645: Rtc Control Register 4 (Rtcctl4)
Chapter 18 Real-Time Counter With Calendar (RTCV2) Table 18-5. RTCCTL3 Field Descriptions Field Description RTC Module Write Enable — These two write-only bits control the write-protect function of several RTCWE[1:0] RTC registers and bits. After a reset, write-protect is disabled, allowing full write access to RTC registers and bits.
Page 646: Rtc Status Register 1 (Rtcs1)
Chapter 18 Real-Time Counter With Calendar (RTCV2) Table 18-6. RTCCTL4 Field Descriptions Field Description Hour Interrupt Enable — This read/write bit enables hour interrupts. If HRIE is set, then an interrupt is HRIE generated when HRF is set. 0 Hour interrupt request is disabled. 1 Hour interrupt request is enabled.
Page 647: Rtc Compensation Configure Register (Rtcccr)
Chapter 18 Real-Time Counter With Calendar (RTCV2) Table 18-7. RTCS1 Field Descriptions Field Description Compensation Data Load Cycle — This status bit is set automatically when compensation circuit start load CDLC RTCMOD and RTCCCR to internal buffered register and cleared automatically when finished. If this bit is set, write to RTCMOD and RTCCCR is blocked.
Page 648: Rtc Counter Register (Rtccnt)
Chapter 18 Real-Time Counter With Calendar (RTCV2) Table 18-8. RTCCCR Field Descriptions Field Description Compensation cycle selection — When the clock compensation mechanism enabled, It will decide the compensation cycle. 00 -- 5 second compensation cycle 01 -- 15 second compensation cycle 10 -- 30 second compensation cycle 11 -- 60 second compensation cycle 16-bit Counter Matches with M+1 Modulo Value Times —...
Page 649: Rtc Modulo Register (Rtcmod)
Chapter 18 Real-Time Counter With Calendar (RTCV2) 18.4.8 RTC Modulo Register (RTCMOD) RTCMOD is the 16-bit modulo value. RTCMODH POR: RTCMODL POR: Figure 18-9. RTC Modulo Register (RTCMOD) Table 18-10. RTCMOD Field Descriptions Field Description 15:0 RTC Modulo — These sixteen read/write bits contain the modulo value used to reset the RTCCNT count to RTCMOD 0x0000.
Page 650: Rtc Minute Register (Rtcminr)
Chapter 18 Real-Time Counter With Calendar (RTCV2) The second counter rolls over to 0 after reaching 59. SEC5 SEC4 SEC3 SEC2 SEC1 SEC0 POR: Figure 18-10. Second Register (SECR) Table 18-11. SECR Field Descriptions Field Description Second Counter Value — These read/write bits contains the current value of the second. 0 to 59 is valid. SEC5~SEC0 Wirting the value other than 0 to 59 has no effect.
Page 651: Functional Description
Chapter 18 Real-Time Counter With Calendar (RTCV2) The second counter rolls over to 0 after reaching 23. POR: Figure 18-12. Hour Register (HRR) Table 18-13. HRR Field Descriptions Field Description Hour Counter Value — These read/write bits contains the current value of the hour. 0 to 23 is valid.Wirting the HR4~HR0 value other than 0 to 23 has no effect.
Page 652: Rtc Clock Compensation
Chapter 18 Real-Time Counter With Calendar (RTCV2) divider circuits generates compensation cycle periodic interrupt and 4 Hz periodic interrupt. Depend on the CCS setting, the cycle period can be 5, 15, 30, 60 seconds. The COMPIE bit in the RTC control regis- ter 4(RTCCTL4) can enable compensation cycle interrupt.
Page 653: Calendar Register And Bit Write Protection
Chapter 18 Real-Time Counter With Calendar (RTCV2) and temperature etc factors, the RTCPS is set to 15, the RTCCLK frequency will be 31187.5HZ. We set RTCMOD value to 31187 first. The fraction value will be 0.5, and we can get CCS=0, Q=3 or CCS=1, Q=8 or CCS=2, Q=15 or CCS=3, Q=30.
Page 654: Load Buffer Register
Chapter 18 Real-Time Counter With Calendar (RTCV2) After a reset, the write-protect mechanism is disabled, allowing the user set the time and date in the calen- dar registers. 18.5.6 Load buffer register Compensation circuit and modulo circiuit using buffered register, those two register are loaded from RTCCCR and RTCMOD only when compensation completed.Write to RTCMOD and RTCCCR is blocked when CDLC=1, to protect data is stable when load occurs.
Page 655: Rtc Compensation
Chapter 18 Real-Time Counter With Calendar (RTCV2) the variation in the RTC clock output and determine the correct calibration point. Refer to Device spec for more information on timer channel connection. 18.6.2 RTC compensation To reach the high precision RTC clock, the compensation need following steps. •...
Page 656 Chapter 18 Real-Time Counter With Calendar (RTCV2) S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 657: Introduction
Chapter 19 Simple Sound Generator (SSGV1) Table 19-1. Revision History Revision Sections Revision Date Description of Changes Number Affected V1.0 Apr. 20, 2011 Initial revision of Sound Generator Module. 19.1 Introduction This document describes the Simple Sound Generator module. The SSG module generates audio frequency tone with autonomous amplitude control. Refer to Figure 19-1 for the detailed block diagram of the module.
Page 658: External Signal Description
Chapter 19 Simple Sound Generator (SSGV1) SSGTONE_B SSGPS_B speaker tone counter Amplifier prescaler bus clock counter amplitude logic tone duration SSGAMP_B external circuit counter attack/decay SSGADC_B logic SSGDUR_B SSGAA_B SSGIF SSGE NOTE: XXX_B is the buffer register of relevant XXX register The external circuit diagram is just for the OMS=0 case External amplifier is required due to the limited driving capability of SGT pad Figure 19-1.
Page 659: Memory Map And Register Definition
Chapter 19 Simple Sound Generator (SSGV1) 19.2.2 Encoded amplitude output signal of SSG. 19.3 Memory Map and Register Definition 19.3.1 Module Memory Map This section describes the content of the registers in the SSG module. The base address of the SSG module is determined at the MCU level when the MCU is defined.
Page 660 Chapter 19 Simple Sound Generator (SSGV1) Register Bit 7 Bit 0 Name 0x0004 TONE9 TONE8 SSGTONEH 0x0005 TONE7 TONE6 TONE5 TONE4 TONE3 TONE2 TONE1 TONE0 SSGTONEL 0x0006 AMP10 AMP9 AMP8 SSGAMPH 0x0007 AMP7 AMP6 AMP5 AMP4 AMP3 AMP2 AMP1 AMP0 SSGAMPL 0x0008 AA10...
Page 661 Chapter 19 Simple Sound Generator (SSGV1) Register Bit 7 Bit 0 Name 0x0013 RESERVED 0x0014 RESERVED 0x0015 RESERVED 0x0016 RESERVED 0x0017 RESERVED = Unimplemented or Reserved Figure 19-2. The SSG Register Summary (Sheet 3 of 3) 19.3.2.1 SSG Control Register (SSGCR) The control register SSGCR contains bits to control module enable, SSG stop control, register data ready status and the SGT output mode selection.
Page 662 Chapter 19 Simple Sound Generator (SSGV1) Table 19-2. SSGCR Field Descriptions (continued) Field Description SSG Register Data Ready — This bit indicates whether the registers data are ready to reload into the relative buffer registers. Writing any of SSGPS/SSGTONE/SSGAMP/SSGDUR/SSGAA/SSGAT/SSGADC will clear this bit. User should write 1 to this bit if registers setting has been done.
Page 663 Chapter 19 Simple Sound Generator (SSGV1) 19.3.2.3 SSG Clock Prescaler Register (SSGPS) SSGPS is a 11 bit prescaler register. For the 32MHz input bus clock source, the frequency range of encoding amplitude waveform is from 15.625KHz to 125KHz, so the divided clock frequency is as Table 19-5.
Page 664 Chapter 19 Simple Sound Generator (SSGV1) 19.3.2.4 SSG Tone Register (SSGTONE) SSGTONE is SSG tone register. The tone frequency range is between 100Hz to 8KHz. Refer to Table 19- for the tone frequency divide ratio and possible tone frequency. Module Base + 0x0004 TONE9 TONE8 Reset...
Page 665 Chapter 19 Simple Sound Generator (SSGV1) 19.3.2.5 SSG Amplitude Register (SSGAMP) SSGAMP register contains amplitude duty. Module Base + 0x0006 AMP10 AMP9 AMP8 Reset Figure 19-9. SSG amplitude Register (SSGAMPH) Module Base + 0x0007 AMP7 AMP6 AMP5 AMP4 AMP3 AMP2 AMP1 AMP0 Reset...
Page 666 Chapter 19 Simple Sound Generator (SSGV1) Module Base + 0x0009 Reset Figure 19-12. SSG Amplitude Adjustment (SSGAAL) Read: Anytime Write: Anytime Table 19-9. SSGAA Field Descriptions Field Description 10–0 SSG Amplitude Adjustment Register Bits — AA[10:0] The bits define the amplitude adjustment value in each linear attack/decay operation. The register is only used when linear attack/decay is selected.
Page 667 Chapter 19 Simple Sound Generator (SSGV1) Table 19-10. SSGAT Field Descriptions Field Description 10–0 SSG Amplitude Threshold Register Bits — AT[10:0] When the amplitude >= SSGAT (attack) or amplitude <=SSGAT (decay), an interrupt will be triggered. 19.3.2.8 SSG Tone Duration register (SSGDUR) The SSGDUR register defines the number of tone cycle in one tone duration.
Page 668 Chapter 19 Simple Sound Generator (SSGV1) Table 19-12. SSGIE Field Descriptions Field Description SSG Ready for Next Sound Data Interrupt Enable — RNDIE Make the interrupt flag bit RNDI can be set when next sound data is ready to config registers. 0 The interrupt signal will not be set when SSGIF is set.
Page 669 Chapter 19 Simple Sound Generator (SSGV1) Module Base + 0x0010 AMPB10 AMPB9 AMPB8 Reset Figure 19-18. Buffer Register of SSGAMP (SSGAMPBH) Module Base + 0x0011 AMPB7 AMPB6 AMPB5 AMPB4 AMPB3 AMPB2 AMPB1 AMPB0 Reset Figure 19-19. Buffer Register of SSGAMP (SSGAMPBL) Read: Anytime Write: Anytime Table 19-14.
Page 670: Functional Description
Chapter 19 Simple Sound Generator (SSGV1) Table 19-15. SSGDCNT Field Descriptions Field Description 7–0 SSG Tone Duration Counter bits — DCNT[7:0] The counter register is re ad only, It contains the tone cycle number. The counter will be reset to 0 when it reaches the SSGDUR value.
Page 671: Ssg Tone Generation
Chapter 19 Simple Sound Generator (SSGV1) 19.4.2 SSG Tone Generation The tone is a low frequency square waveform. Tone generation logic consists of a tone counter triggered by prescaler signal and the tone period register SSGTONE with its buffer register. The register SSGTONE contains the coefficient value of half tone period, one tone cycle period = 2 x (SSGTONE + 1) x prescaler cycle.
Page 672 Chapter 19 Simple Sound Generator (SSGV1) • In linear attack operation SSGAMPB (SSGAMP’s buffer) will be increased by SSGAA every SSGSSGDUR + 1 tone cycle. In linear decay operation, SSGAMPB will be decreased by SSGAA every SSGDUR + 1 tone cycle. See below linear attack/decay formula. •...
Page 673 Chapter 19 Simple Sound Generator (SSGV1) Gong attack operation: SSGAMPB = SSGAMP; AMP_int = {SSGAMPB, 5’b00000}; AMP_int = AMP_int + (AMP_int >> 5); SSGAMPB = AMP_int >> 5; } While (SSGAMPB < AT_buf) where : AMP_int is a 16 bit internal register. AT_buf is the internal buffer of amplitude threshold register SSGAT.
Page 674: Ssg Start And Stop
Chapter 19 Simple Sound Generator (SSGV1) Exponential attack operation: SSGAMPB = SSGAMP; do { SSGAMPB = SSGAMPB << 1 + 1; } while (SSGAMPB < AT_buf) Where : AT_buf is the internal buffer of amplitude threshold register SSGAT. Exponential decay operation: SSGAMPB = SSGAMP;...
Page 675: Register Reload
Chapter 19 Simple Sound Generator (SSGV1) 19.4.5 Register Reload In SSG all registers except SSGCR, SSGIE and SSGIF are double buffered. the value will be reloaded from config registers to their buffers in three cases: one is when SSG startup (or restart), the other two are attack/decay mode register reload and non-attack/decay mode register reload.
Page 676: Ssg Output Control
Chapter 19 Simple Sound Generator (SSGV1) Tone duration reload point stop point reload and restart where : Assume one tone duration contains 3 tone cycle RDR is the RDR bit of SSGCR register Figure 19-24. Non-attack/decay mode Register Reload 19.4.6 SSG Output Control There are two output signals, SGA and SGT.
Page 677: Introduction
Chapter 20 ECC Generation module (SRAM_ECCV1) 20.1 Introduction The purpose of ECC logic is to detect and correct as much as possible memory data bit errors. These soft errors can occur randomly during operation, mainly generated by alpha radiation. Soft Error means, that only the information inside the memory cell is corrupt, the memory cell itself is not damaged.
Page 678 Chapter 20 ECC Generation module (SRAM_ECCV1) NOTE Register Address = Module Base Address + Address Offset, where the Module Base Address is defined at the MCU level and the Address Offset is defined at the module level. Address Offset Bit 7 Bit 0 Register Name 0x0000...
Page 679: Register Descriptions
Chapter 20 ECC Generation module (SRAM_ECCV1) 20.2.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field functions follow the register diagrams, in bit order.
Page 680 Chapter 20 ECC Generation module (SRAM_ECCV1) 20.2.2.3 ECC Interrupt Flag Register (ECCIF) Module Base + 0x0002 Access: User read/write SBEEIF Reset 1. Read: Anytime Write: Anytime, write 1 to clear Figure 20-4. ECC Interrupt Flag Register (ECCIF) Table 20-4. ECCIF Field Description Field Description Single bit ECC Error Interrupt Flag —...
Page 681 Chapter 20 ECC Generation module (SRAM_ECCV1) ECC Debug Pointer Register (ECCDPTRH, ECCDPTRM, 20.2.2.4 ECCDPTRL) Module Base + 0x0007 Access: User read/write DPTR[23:16] Reset Module Base + 0x0008 Access: User read/write DPTR[15:8] Reset Module Base + 0x0009 Access: User read/write DPTR[7:1] Reset = Unimplemented Figure 20-5.
Page 682 Chapter 20 ECC Generation module (SRAM_ECCV1) ECC Debug Data (ECCDDH, ECCDDL) 20.2.2.5 Module Base + 0x000C Access: User read/write DDATA[15:8] Reset Module Base + 0x000D Access: User read/write DDATA[7:0] Reset = Unimplemented Figure 20-6. ECC Debug Data (ECCDDH, ECCDDL) 1. Read: Anytime Write: Anytime Table 20-6.
Page 683: Functional Description
Chapter 20 ECC Generation module (SRAM_ECCV1) 20.2.2.7 ECC Debug Command (ECCDCMD) Module Base + 0x000F Access: User read/write ECCDW ECCDR ECCDRR Reset 1. Read: Anytime Write: Anytime, in special mode only Figure 20-8. ECC Debug Command (ECCDCMD) Table 20-8. ECCDCMD Field Description Field Description ECC Disable Read Repair Function—...
Page 684: Aligned 2 And 4 Byte Memory Write Access
Chapter 20 ECC Generation module (SRAM_ECCV1) Table 20-9. Memory access cycles access Memory Access type Internal operation Error indication error cycle content read data from the memory old + new data write old + new data to the memory read data from the memory 1 or 3 byte write, single corrected +...
Page 685: Memory Read Access
Chapter 20 ECC Generation module (SRAM_ECCV1) 4 byte read data from system memory 2 byte use data 2 byte use data read out data read out data and correct if and correct if single bit ECC single bit ECC error was found error was found correct read data correct read data...
Page 686: Ecc Algorithm
Chapter 20 ECC Generation module (SRAM_ECCV1) Table 20-10. SRAM_ECC Interrupt Sources Module Interrupt Sources Local Enable Single bit ECC error ECCIE[SBEEIE] 20.3.6 ECC Algorithm The table below shows the equation for each ECC bit based on the 16 bit data word. Table 20-11.
Page 687 Chapter 20 ECC Generation module (SRAM_ECCV1) access is always a 2 byte aligned memory access, so that no ECC check is performed and no single or double bit ECC error indication are activated. 20.3.7.2 ECC Debug Memory Read Access Writing one to the ECCDR bit performs a debug read access from the memory address defined by register DPTR.
Page 688 Chapter 20 ECC Generation module (SRAM_ECCV1) S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 689: Chapter 21
Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) Table 21-1. Revision History Revision Revision Sections Description of Changes Number Date Affected V02.06 18 Mar 2013 - Standardized nomenclature in references to memory sizes V02.07 24 May 2013 - Revised references to NVM Resource Area to improve readability V02.08 12 Jun 2013 - Changed MLOADU...
Page 690: Introduction
21.1 Introduction The FTMRZ128K4K module implements the following: • 128 KB of P-Flash (Program Flash) memory • 4 KB of EEPROM memory The Flash memory is ideal for single-supply applications allowing for field reprogramming without requiring external high voltage sources for program or erase operations. The Flash module includes a memory controller that executes commands to modify Flash memory contents.
Page 691: Features
Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) NVM Command Mode — An NVM mode using the CPU to setup the FCCOB register to pass parameters required for Flash command execution. Phrase — An aligned group of four 16-bit words within the P-Flash memory. Each phrase includes two sets of aligned double words with each set including 7 ECC bits for single bit fault correction and double bit fault detection within each double word.
Page 692: External Signal Description
Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) Figure 21-1. FTMRZ128K4K Block Diagram Flash Interface 16bit Command Registers Interrupt internal P-Flash Request 32Kx39 sector 0 Error Protection sector 1 Interrupt Request sector 255 Security Clock Clock Divider FCLK Memory Controller EEPROM 2Kx22 sector 0 sector 1...
Page 693: Memory Map And Registers
Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) 21.3 Memory Map and Registers This section describes the memory map and registers for the Flash module. Read data from unimplemented memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space in the Flash module will be ignored by the Flash module.
Page 694 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) memory, can be activated for protection. The Flash memory addresses covered by these protectable regions are shown in the P-Flash memory map. The higher address region is mainly targeted to hold the boot loader code since it covers the vector space. Default protection settings as well as security information that allows the MCU to restrict access to the Flash module are stored in the Flash configuration field as described in Table...
Page 695 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) P-Flash START = 0xFE_0000 Flash Protected/Unprotected Region 96 KB 0xFF_8000 0xFF_8400 0xFF_8800 Flash Protected/Unprotected Lower Region 0xFF_9000 1, 2, 4, 8 KB Protection Fixed End 0xFF_A000 Flash Protected/Unprotected Region Protection 8 KB (up to 29 KB) Movable End 0xFF_C000 Protection...
Page 696 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) Table 21-5. Program IFR Fields Size Global Address Field Description (Bytes) 0x1F_C000 – 0x1F_C007 Reserved 0x1F_C008 – 0x1F_C0B5 Reserved 0x1F_C0B6 – 0x1F_C0B7 Version ID 0x1F_C0B8 – 0x1F_C0BF Reserved Program Once Field 0x1F_C0C0 – 0x1F_C0FF Refer to Section 21.4.7.6, “Program Once Command”...
Page 697: Register Descriptions
Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) 0x1F_4000 Reserved 512 bytes 0x1F_41FF Reserved 15872 bytes 0x1F_8000 Reserved 6 KB 0x1F_97FF Reserved 10 KB 0x1F_C000 P-Flash IFR 256 bytes 0x1F_C100 Reserved 16,128 bytes Figure 21-3. Memory Controller Resource Memory Map (NVM Resources Area) 21.3.2 Register Descriptions The Flash module contains a set of 24 control and status registers located between Flash module base +...
Page 698 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) Address & Name FPOVRD WSTATACK 0x0003 FPSTAT ERSAREQ 0x0004 CCIE IGNSF WSTAT[1:0] FDFD FSFD FCNFG 0x0005 SFDIE FERCNFG MGBUSY RSVD MGSTAT1 MGSTAT0 0x0006 CCIF ACCERR FPVIOL FSTAT 0x0007 DFDF SFDIF FERSTAT RNV6 0x0008 FPOPEN FPHDIS FPHS1...
Page 699 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) Address & Name 0x0011 CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 FCCOB2LO 0x0012 CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 FCCOB3HI 0x0013 CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 FCCOB3LO 0x0014 CCOB15 CCOB14...
Page 700 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) CAUTION The FCLKDIV register should never be written while a Flash command is executing (CCIF=0). Table 21-7. FCLKDIV Field Descriptions Field Description Clock Divider Loaded FDIVLD 0 FCLKDIV register has not been written since the last reset 1 FCLKDIV register has been written since the last reset Clock Divider Locked FDIVLCK...
Page 701 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) Table 21-8. FDIV values for various BUSCLK Frequencies BUSCLK Frequency BUSCLK Frequency (MHz) (MHz) FDIV[5:0] FDIV[5:0] 18.6 19.6 0x12 44.6 45.6 0x2C 19.6 20.6 0x13 45.6 46.6 0x2D 20.6 21.6 0x14 46.6 47.6 0x2E 21.6 22.6...
Page 702 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) Table 21-9. FSEC Field Descriptions (continued) Field Description 5–2 Reserved Nonvolatile Bits — The RNV bits should remain in the erased state for future enhancements. RNV[5:2] 1–0 Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 21-11.
Page 703 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) Table 21-12. FCCOBIX Field Descriptions Field Description 2–0 Common Command Register Index— The CCOBIX bits are used to indi c ate how many words of the FCCOB CCOBIX[1:0] register array are being read or written to. See Section 21.3.2.13, “Flash Common Command Object Registers (FCCOB)“,”...
Page 704 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) Offset Module Base + 0x0004 ERSAREQ CCIE IGNSF WSTAT[1:0] FDFD FSFD Reset = Unimplemented or Reserved Figure 21-9. Flash Configuration Register (FCNFG) CCIE, IGNSF, WSTAT, FDFD, and FSFD bits are readable and writable, ERSAREQ bit is read only, and remaining bits read 0 and are not writable.
Page 705 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) Table 21-14. FCNFG Field Descriptions (continued) Field Description Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array FDFD read operations. The FDFD bit is cleared by writing a 0 to FDFD. 0 Flash array read operations will set the DFDF flag in the FERSTAT register only if a double bit fault is detected 1 Any Flash array read operation will force the DFDF flag in the FERSTAT register to be set (see Section...
Page 706 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) Table 21-16. FERCNFG Field Descriptions Field Description Single Bit Fault Detect Interrupt Enable — The SFDIE bit controls interrupt generation when a single bit fault SFDIE is detected during a Flash block read operation. 0 SFDIF interrupt disabled whenever the SFDIF flag is set (see Section 21.3.2.8)
Page 707 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) Table 21-17. FSTAT Field Descriptions (continued) Field Description Reserved Bit — This bit is reserved and always reads 0 RSVD 1–0 Memory Controller Command Completion Status Flag — One or more MGSTAT flag bits are set if an error MGSTAT[1:0] is detected during execution of a Flash command or during the Flash reset sequence.
Page 708 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) 21.3.2.9 P-Flash Protection Register (FPROT) The FPROT register defines which P-Flash sectors are protected against program and erase operations. Offset Module Base + 0x0008 RNV6 FPOPEN FPHDIS FPHS[1:0] FPLDIS FPLS[1:0] Reset = Unimplemented or Reserved Figure 21-13.
Page 709 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) Table 21-19. FPROT Field Descriptions (continued) Field Description Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a FPLDIS protected/unprotected area in a specific region of the P-Flash memory beginning with global address 0xFF_8000.
Page 710 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) FPHDIS = 1 FPHDIS = 1 FPHDIS = 0 FPHDIS = 0 FPLDIS = 1 FPLDIS = 0 FPLDIS = 1 FPLDIS = 0 Scenario FLASH START 0xFF_8000 0xFF_FFFF Scenario FLASH START 0xFF_8000 0xFF_FFFF Protected region with size Unprotected region...
Page 711 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) 21.3.2.9.1 P-Flash Protection Restrictions In Normal Single Chip Mode the general guideline is that P-Flash protection can only be added and not removed. Table 21-23 specifies all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored.
Page 712 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) P-Flash memory (see Table 21-4) as indicated by reset condition F in Table 21-25. To change the EEPROM protection that will be loaded during the reset sequence, the P-Flash sector containing the EEPROM protection byte must be unprotected, then the EEPROM protection byte must be programmed. If a double bit fault is detected while reading the P-Flash phrase containing the EEPROM protection byte during the reset sequence, the DPOPEN bit will be cleared and DPS bits will be set to leave the EEPROM memory fully protected.
Page 713 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) Offset Module Base + 0x000A NV[7:0] Reset = Unimplemented or Reserved Figure 21-16. Flash Option Register (FOPT) 1. Loaded from Flash configuration field, during reset sequence. All bits in the FOPT register are readable but are not writable. During the reset sequence, the FOPT register is loaded from the Flash nonvolatile byte in the Flash configuration field at global address 0xFF_FE0E located in P-Flash memory (see Table...
Page 714 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) Offset Module Base + 0x000C CCOB[15:8] Reset Figure 21-18. Flash Common Command Object 0 High Register (FCCOB0HI) Offset Module Base + 0x000D CCOB[7:0] Reset Figure 21-19. Flash Common Command Object 0 Low Register (FCCOB0LO) Offset Module Base + 0x000E CCOB[15:8] Reset...
Page 715 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) Offset Module Base + 0x0011 CCOB[7:0] Reset Figure 21-23. Flash Common Command Object 2 Low Register (FCCOB2LO) Offset Module Base + 0x0012 CCOB[15:8] Reset Figure 21-24. Flash Common Command Object 3 High Register (FCCOB3HI) Offset Module Base + 0x0013 CCOB[7:0] Reset...
Page 716 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) Offset Module Base + 0x0016 CCOB[15:8] Reset Figure 21-28. Flash Common Command Object 5 High Register (FCCOB5HI) Offset Module Base + 0x0017 CCOB[7:0] Reset Figure 21-29. Flash Common Command Object 5 Low Register (FCCOB5LO) 21.3.2.13.1 FCCOB - NVM Command Mode NVM command mode uses the FCCOB registers to provide a command code and its relevant parameters to the Memory Controller.
Page 717: Functional Description
Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) Table 21-27. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] Register Byte FCCOB Parameter Fields (NVM Command Mode) Data 1 [15:8] FCCOB3 Data 1 [7:0] Data 2 [15:8] FCCOB4 Data 2 [7:0] Data 3 [15:8] FCCOB5 Data 3 [7:0] 21.4...
Page 718: Internal Nvm Resource
Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) To guarantee the proper read timing from the Flash array, the FTMRZ128K4K FMU will control (i.e. pause) the S12Z core accesses, considering that the MCU can be configured to fetch data at a faster frequency than the Flash block can support.
Page 719 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) The next sections describe: • How to write the FCLKDIV register that is used to generate a time base (FCLK) derived from BUSCLK for Flash program and erase command operations • The command write sequence used to set Flash command parameters and launch execution •...
Page 720 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) START Read: FCLKDIV register Clock Divider FDIV CCIF Read: FSTAT register Value Check Correct? Set? Note: FCLKDIV must be set after each reset FCCOB Availability Check Read: FSTAT register Write: FCLKDIV register CCIF Set? Results from previous Command ACCERR/...
Page 721 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) 21.4.5.3 Valid Flash Module Commands Table 21-29 present the valid Flash commands, as enabled by the combination of the functional MCU mode (Normal SingleChip NS, Special Singlechip SS) with the MCU security state (Unsecured, Secured). Table 21-29.
Page 722 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) 21.4.5.4 P-Flash Commands Table 21-30 summarizes the valid P-Flash commands along with the effects of the commands on the P- Flash block and other resources within the Flash module. Table 21-30. P-Flash Commands FCMD Command Function on P-Flash Memory...
Page 723: Allowed Simultaneous P-Flash And Eeprom Operations
Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) Table 21-31. EEPROM Commands FCMD Command Function on EEPROM Memory Erase Verify All Verify that all EEPROM (and P-Flash) blocks are erased. 0x01 Blocks 0x02 Erase Verify Block Verify that the EEPROM block is erased. Erase all EEPROM (and P-Flash) blocks.
Page 724: Flash Command Description
Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) Table 21-32. Allowed P-Flash and EEPROM Simultaneous Operations EEPROM Margin Sector Mass Program Flash Read Program Read Erase Erase Read Margin Read Program Sector Erase Mass Erase 1. Strictly speaking, only one read of either the P-Flash or EEPROM can occur at any given instant, but the memory controller will transparently arbitrate P- Flash and EEPROM accesses giving uninterrupted read access whenever possible.
Page 725 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) Table 21-33. Erase Verify All Blocks Command FCCOB Requirements Register FCCOB Parameters FCCOB0 0x01 Not required Upon clearing CCIF to launch the Erase Verify All Blocks command, the Memory Controller will verify that the entire Flash memory space is erased. The CCIF flag will set after the Erase Verify All Blocks operation has completed.
Page 726 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) 21.4.7.3 Erase Verify P-Flash Section Command The Erase Verify P-Flash Section command will verify that a section of code in the P-Flash memory is erased. The Erase Verify P-Flash Section command defines the starting point of the code to be verified and the number of phrases.
Page 727 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) Table 21-39. Read Once Command FCCOB Requirements Register FCCOB Parameters FCCOB3 Read Once word 1 value FCCOB4 Read Once word 2 value FCCOB5 Read Once word 3 value Upon clearing CCIF to launch the Read Once command, a Read Once phrase is fetched and stored in the FCCOB indexed register.
Page 728 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) Upon clearing CCIF to launch the Program P-Flash command, the Memory Controller will program the data words to the supplied global address and will then proceed to verify the data words read back as expected.
Page 729 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) Table 21-44. Program Once Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch Set if command not available in current mode (see Table 21-29) ACCERR Set if an invalid phrase index is supplied Set if the requested phrase has already been programmed FSTAT FPVIOL...
Page 730 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) The erase-all function requires the clock divider register FCLKDIV (see Section 21.3.2.1) to be loaded before invoking this function using soc_erase_all_req input pin. Please refer to the Reference Manual for information about the default value of FCLKDIV in case direct writes to register FCLKDIV are not allowed by the time this feature is invoked.
Page 731 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) Table 21-49. Erase Flash Block Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch Set if command not available in current mode (see Table 21-29) ACCERR Set if an invalid global address [23:0] is supplied Set if the supplied P-Flash address is not phrase-aligned or if the EEPROM FSTAT...
Page 732 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) 21.4.7.10 Unsecure Flash Command The Unsecure Flash command will erase the entire P-Flash and EEPROM memory space and, if the erase is successful, will release security. Table 21-52. Unsecure Flash Command FCCOB Requirements Register FCCOB Parameters FCCOB0...
Page 733 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) Upon clearing CCIF to launch the Verify Backdoor Access Key command, the Memory Controller will check the FSEC KEYEN bits to verify that this command is enabled. If not enabled, the Memory Controller sets the ACCERR bit in the FSTAT register and terminates. If the command is enabled, the Memory Controller compares the key provided in FCCOB to the backdoor comparison key in the Flash configuration field with Key 0 compared to 0xFF_FE00, etc.
Page 734 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) Table 21-57. Valid Set User Margin Level Settings FCCOB2 Level Description 0x0000 Return to Normal Level 0x0001 User Margin-1 Level 0x0002 User Margin-0 Level 1. Read margin to the erased state 2. Read margin to the programmed state Table 21-58.
Page 735 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) NOTE When the EEPROM block is targeted, the EEPROM field margin levels are applied only to the EEPROM reads. However, when the P-Flash block is targeted, the P-Flash field margin levels are applied to both P-Flash and EEPROM reads.
Page 736 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) 21.4.7.14 Erase Verify EEPROM Section Command The Erase Verify EEPROM Section command will verify that a section of code in the EEPROM is erased. The Erase Verify EEPROM Section command defines the starting point of the data to be verified and the number of words.
Page 737 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) Table 21-64. Program EEPROM Command FCCOB Requirements Register FCCOB Parameters Global address [23:16] to FCCOB0 0x11 identify the EEPROM block FCCOB1 Global address [15:0] of word to be programmed FCCOB2 Word 0 program value FCCOB3 Word 1 program value, if desired FCCOB4...
Page 738 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) Upon clearing CCIF to launch the Erase EEPROM Sector command, the Memory Controller will erase the selected Flash sector and verify that it is erased. The CCIF flag will set after the Erase EEPROM Sector operation has completed.
Page 739 Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) Table 21-69. Protection Override selection description Protection Update Protection register selection Selection code [1:0] Update EEPROM protection bit 1 0 - keep unchanged (do not update) 1 - update EEPROM protection with new DFPROT value loaded on FCCOB If the comparison key successfully matches the key programmed in the Flash Configuration Field the Protection Override command will preserve the current values of registers FPROT and DFPROT stored in an internal area and will override these registers as selected by the Protection Update Selection field with...
Page 740: Interrupts
Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) 21.4.8 Interrupts The Flash module can generate an interrupt when a Flash command operation has completed or when a Flash command operation has detected an ECC fault. Table 21-71. Flash Interrupt Sources Global (CCR) Interrupt Source Interrupt Flag Local Enable...
Page 741: Stop Mode
Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) 21.4.10 Stop Mode If a Flash command is active (CCIF = 0) when the MCU requests stop mode, the current Flash operation will be completed before the MCU is allowed to enter stop mode. 21.5 Security The Flash module provides security information to the MCU.
Page 742: Unsecuring The Mcu In Special Single Chip Mode Using Bdm
Chapter 21 128 KB Flash Module (S12ZFTMRZ128K4KV2) to re-enable the Verify Backdoor Access Key command. The security as defined in the Flash security byte (0xFF_FE0F) is not changed by using the Verify Backdoor Access Key command sequence. The backdoor keys stored in addresses 0xFF_FE00-0xFF_FE07 are unaffected by the Verify Backdoor Access Key command sequence.
Page 743: Introduction
Chapter 22 CAN Physical Layer (S12CANPHYV2) Table 22-1. Revision History Table Revision Sections Revision Date Description of Changes Number Affected V02.00 05 Nov 2012 • Added CPTXD-dominant timeout feature V02.01 10 Jul 2013 • Minor orthographical corrections V02.02 10 Jul 2013 •...
Page 744: S12Zvh Family Reference Manual, Rev. 1.05 Freescale Semiconductor
Chapter 22 CAN Physical Layer (S12CANPHYV2) 22.1.2 Modes of Operation The following modes can be taken by the CAN Physical Layer (refer to 22.5.2 for details): 1. Shutdown mode In shutdown mode the CAN Physical Layer is fully de-biased including the wake-up receiver. 2.
Page 745: External Signal Description
Chapter 22 CAN Physical Layer (S12CANPHYV2) VDDC CHOCIF Time CPTXD CHVHIF CHVH Status Change CHVLIF CHVL Status Change Precision CANH Receiver Normal/Shutdown/ SPLIT Standby mode intern. CPRXD 2.5V point high-z CANL Standby Mode Wake-up Receiver CLVLIF CLVL Status Change CLVHIF Status CLVH Change...
Page 746: Canh — Can Bus High Pin
Chapter 22 CAN Physical Layer (S12CANPHYV2) 22.2.1 CANH — CAN Bus High Pin The CANH signal either connects directly to CAN bus high line or through an optional external common mode choke. 22.2.2 CANL — CAN Bus Low Pin The CANL signal either connects directly to CAN bus low line or through an optional external common mode choke.
Page 747: Memory Map And Register Definition
Chapter 22 CAN Physical Layer (S12CANPHYV2) 22.4 Memory Map and Register Definition 22.4.1 This section provides a detailed description of all registers accessible in the CAN Physical Module Memory Map Layer. A summary of the registers associated with the CAN Physical Layer sub-block is shown in Table 22-3.
Page 748: Register Descriptions
Chapter 22 CAN Physical Layer (S12CANPHYV2) 22.4.2 Register Descriptions This section describes all CAN Physical Layer registers and their individual bits. 22.4.2.1 Port CP Data Register (CPDR) Module Base + 0x0000 Access: User read/write CPDR7 CPDR0 CPDR1 Reset Figure 22-2. Port CP Data Register (CPDR) 1.
Page 749 Chapter 22 CAN Physical Layer (S12CANPHYV2) 22.4.2.2 CAN Physical Layer Control Register (CPCR) Module Base + 0x0001 Access: User read/write WUPE SLR2 SLR1 SLR0 Reset Figure 22-3. CAN Physical Layer Control Register (CPCR) 1. Read: Anytime Write: Anytime except CPE which is set once Table 22-5.
Page 750 Chapter 22 CAN Physical Layer (S12CANPHYV2) 22.4.2.3 Reserved Register Module Base + 0x0002 Access: User read/write Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reset Figure 22-4. Reserved Register 1. Read: Anytime Write: Only in special mode NOTE This reserved register is designed for factory test purposes only and is not intended for general user access.
Page 751 Chapter 22 CAN Physical Layer (S12CANPHYV2) Table 22-6. CPSR Register Field Descriptions Field Description CANL Voltage Failure Low Status Bit CPCLVL This bit reflects the CANL voltage failure low monitor status. 0 Condition V V CANL 1 Condition V  V CANL CPTXD-Dominant Timeout Status Bit CPDT...
Page 752 Chapter 22 CAN Physical Layer (S12CANPHYV2) 22.4.2.5 Reserved Register Module Base + 0x0004 Access: User read/write Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reset Figure 22-6. Reserved Register 1. Read: Anytime Write: Only in special mode NOTE This reserved register is designed for factory test purposes only and is not intended for general user access.
Page 753 Chapter 22 CAN Physical Layer (S12CANPHYV2) Table 22-7. CPIE Register Field Descriptions Field Description CAN Physical Layer Voltage-Failure Interrupt Enable CPVFIE If enabled, the CAN Physical Layer generates an interrupt if any of the CAN Physical Layer voltage failure interrupt flags assert. 0 Voltage failure interrupt is disabled 1 Voltage failure interrupt is enabled CPTXD-Dominant Timeout Interrupt Enable...
Page 754 Chapter 22 CAN Physical Layer (S12CANPHYV2) Table 22-8. CPIF Register Field Descriptions Field Description CANL Voltage Failure High Interrupt Flag CLVHIF This flag is set to 1 when the CPCLVH bit in the CAN Physical Layer Status Register (CPSR) changes. 0 No change in CPCLVH 1 CPCLVH has changed CANL Voltage Failure Low Interrupt Flag...
Page 755: Functional Description
Chapter 22 CAN Physical Layer (S12CANPHYV2) 22.5 Functional Description 22.5.1 General The CAN Physical Layer provides an interface for the SoC integrated MSCAN controller. 22.5.2 Modes Figure 22-10 shows the possible mode transitions depending on control bit CPE, device reduced performance mode (“RPM”;...
Page 756 Chapter 22 CAN Physical Layer (S12CANPHYV2) to VSSC via high-ohmic input resistors of the receiver. The SPLIT pin as well as the internal mid-point reference are set to high-impedance. Shutdown mode cannot be re-entered until reset. 22.5.2.2 Normal Mode In normal mode the full transceiver functionality is available. In this mode, the CAN bus is controlled by the CPTXD input and the CAN bus state (recessive, dominant) is reported on the CPRXD output.
Page 757: Interrupts
Chapter 22 CAN Physical Layer (S12CANPHYV2) 22.5.2.5 Standby Mode with Wake-Up Feature Standby is a reduced current consumption mode and is entered during RPM following a stop mode request. The transceiver and bus error diagnostics are disabled. The CPTXD-dominant timeout counter is stopped. CANH and CANL lines are pulled to VSSC via high-ohmic input resistors of the receiver.
Page 758: Initialization/Application Information
Chapter 22 CAN Physical Layer (S12CANPHYV2) The flags are used as interrupt sources of which either of the four can generate a CPI interrupt if the common enable bit CPVFIE in CAN Physical Layer Interrupt Enable Register (CPIE) is set. 22.5.3.2 CPTXD-Dominant Timeout Interrupt For network lock-up protection of the CAN bus, the CAN physical layer features a permanent CPTXD-...
Page 759: Wake-Up Mechanism
Chapter 22 CAN Physical Layer (S12CANPHYV2) 22.6.2 Wake-up Mechanism In standby mode the CAN Physical Layer passes the bus state to its CPRXD output without any signal filtering if the wake-up receiver is enabled. In order to wake-up from standby mode upon CAN bus events the implemented MSCAN module wake-up feature with glitch filtering is used if set up accordingly.
Page 760 Chapter 22 CAN Physical Layer (S12CANPHYV2) S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 761: Introduction
Chapter 23 Supply Voltage Sensor - (BATSV2) Table 23-1. Revision History Table Rev. No. Data Sections Substantial Change(s) (Item No.) Affected V01.00 15 Dec 2010 Initial Version V02.00 16 Mar 2011 23.3.2.1 - added BVLS[1] to support four voltage level 23.4.2.1 - moved BVHS to register bit 6 23.1...
Page 762: Block Diagram
Chapter 23 Supply Voltage Sensor - (BATSV2) During stop mode operation the path from the VSUP pin through the resistor chain to ground is opened and the low voltage sense features are disabled. The content of the configuration register is unchanged. 23.1.3 Block Diagram Figure 23-1...
Page 763: Vsup — Voltage Supply Pin
Chapter 23 Supply Voltage Sensor - (BATSV2) comparator via an analog multiplexer. The pin itself is protected against reverse battery connections. To protect the pin from external fast transients an external resistor (R ) is needed for protection. VSENSE_R 23.2.2 VSUP —...
Page 764: Register Descriptions
Chapter 23 Supply Voltage Sensor - (BATSV2) NOTE Register Address = Module Base Address + Address Offset, where the Module Base Address is defined at the MCU level and the Address Offset is defined at the module level. Address Offset Bit 7 Bit 0 Register Name...
Page 765 Chapter 23 Supply Voltage Sensor - (BATSV2) 23.3.2.1 BATS Module Enable Register (BATE) Module Base + 0x0000 Access: User read/write BVHS BVLS[1:0] BSUAE BSUSE BSEAE BSESE Reset = Unimplemented Figure 23-3. BATS Module Enable Register (BATE) 1. Read: Anytime Write: Anytime Table 23-2.
Page 766 Chapter 23 Supply Voltage Sensor - (BATSV2) When opening the resistors path to ground by changing BSESE, BSEAE or BSUSE, BSUAE then for a time T + two bus cycles the measured EN_UNC value is invalid. This is to let internal nodes be charged to correct value. BVHIE, BVLIE might be cleared for this time period to avoid false interrupts.
Page 767 Chapter 23 Supply Voltage Sensor - (BATSV2) BATS Module Status Register (BATSR 23.3.2.2 Module Base + 0x0001 Access: User read only BVHC BVLC Reset = Unimplemented Figure 23-4. BATS Module Status Register (BATSR) 1. Read: Anytime Write: Never Table 23-3. BATSR - Register Field Descriptions Field Description BATS Voltage Sense High Condition Bit —...
Page 768 Chapter 23 Supply Voltage Sensor - (BATSV2) BATS Interrupt Enable Register (BATIE) 23.3.2.3 Module Base + 0x0002 Access: User read/write BVHIE BVLIE Reset = Unimplemented Figure 23-6. BATS Interrupt Enable Register (BATIE) 1. Read: Anytime Write: Anytime Table 23-4. BATIE Register Field Descriptions Field Description BATS Interrupt Enable High —...
Page 769: Functional Description
Chapter 23 Supply Voltage Sensor - (BATSV2) Table 23-5. BATIF Register Field Descriptions Field Description BATS Interrupt Flag High Detect — The flag is set to 1 when BVHC status bit changes. BVHIF 0 No change of the BVHC status bit since the last clearing of the flag. 1 BVHC status bit has changed since the last clearing of the flag.
Page 770: Interrupts
Chapter 23 Supply Voltage Sensor - (BATSV2) 23.4.2 Interrupts This section describes the interrupt generated by the BATS module. The interrupt is only available in CPU run mode. Entering and exiting CPU stop mode has no effect on the interrupt flags. To make sure the interrupt generation works properly the bus clock frequency must be higher than the Voltage Warning Low Pass Filter frequency (f VWLP_filter...
Page 771 Chapter 23 Supply Voltage Sensor - (BATSV2) Interrupt flag BVLIF can only be cleared by writing a 1. If the interrupt is enabled by bit BVLIE the module requests an interrupt to MCU (BATI). 23.4.2.2 BATS Voltage High Condition Interrupt (BVHI) To use the Voltage High Interrupt the Level Sensing must be enabled (BSESE =1 or BSUSE).
Page 772 Chapter 23 Supply Voltage Sensor - (BATSV2) S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 773: A.1 General
Appendix A MCU Electrical Specifications General This supplement contains the most accurate electrical information for the MC9S12ZVH-Family available at the time of publication. This introduction is intended to give an overview on several common topics like power supply, current injection etc. S12ZVH Family Reference Manual, Rev.
Page 774: A.1.1 Pins
Appendix A MCU Electrical Specifications Table A-1. Power Supplies Mnemonic Nominal Voltage Description VSS1 Ground pin for 2.8V core supply voltage generated by on chip voltage regulator VDDF 2.8V 2.8V core supply voltage generated by on chip voltage regulator VSS2 Ground pin for 1.8V core supply voltage generated by on chip voltage regulator VDD18 1.8V...
Page 775: A.1.2 Current Injection
Appendix A MCU Electrical Specifications A.1.1.3 Main Oscillator If the designated PE0 (EXTAL) and PE1 (XTAL) pins are configured for external oscillator operation then these pins have a nominal voltage of 1.8V. A.1.1.4 TEST This pin is used for production testing only. The TEST pin must be tied to ground in all applications. A.1.2 Current Injection Power supply must maintain regulation within operating VDDX or V...
Page 776: A.1.3 Absolute Maximum Ratings
Appendix A MCU Electrical Specifications power; e.g., if no system clock is present, or if the clock rate is very low which would reduce overall power consumption. Figure A-1. Current Injection on GPIO Port if V > V VSUP Voltage Regulator Pad Driver VDDX Load...
Page 777: A.1.4 Esd Protection And Latch-Up Immunity
Appendix A MCU Electrical Specifications Table A-2. Absolute Maximum Ratings Base connection of bipolar for CANPHY0 supply -0.3 BCTLC Voltage difference V to V and V  –0.1 VDDXM Voltage difference V to V and V  –0.3 VSSXM Digital I/O input voltage –0.3 EXTAL, XTAL –0.3...
Page 778: A.1.5 Operating Conditions
Appendix A MCU Electrical Specifications Table A-3. ESD and Latch-up Test Conditions Model Spec Description Symbol Value Unit Minimum Input Voltage Limit -2.5 Latch-up for 5V GPIO’s Maximum Input Voltage Limit +7.5 Latch-up for Minimum Input Voltage Limit BCTL/BCTLC/V SENSE/CANH/ Maximum Input Voltage Limit CANL/SPLIT Table A-4.
Page 779: A.1.6 Power Dissipation And Thermal Characteristics
Appendix A MCU Electrical Specifications Table A-5. Operating Conditions Rating Symbol Unit Bus frequency — Footnote Bus frequency without flash wait states — — WSTAT C Operating junction temperature range –40 — C Operating ambient temperature range –40 — V Operating junction temperature range –40 —...
Page 780 Appendix A MCU Electrical Specifications The total power dissipation P can be calculated from the equation below. Table A-6 below lists the power dissipation components . Table A-6 gives an overview of the supply currents. VSUP BCTL CANPHY0 BCTLC GPIO Table A-6.
Page 781 Appendix A MCU Electrical Specifications Table A-7. Thermal Package Characteristics Rating Symbol Unit LQFP 100 Thermal resistance 100LQFP, single sided PCB  — — C/W Thermal resistance 100LQFP, double sided PCB  — — C/W with 2 internal planes Junction to Board 100LQFP ...
Page 782: A.1.7 I/O Characteristics
Appendix A MCU Electrical Specifications A.1.7 I/O Characteristics This section describes the characteristics of I/O pins Table A-8. 5-V I/O Characteristics Conditions are 4.5 V < V < 5.5 V junction temperature from –40C to +150C, unless otherwise noted I/O Characteristics for all GPIO pins (defined in A.1.1.1/A-774). Rating Symbol Unit...
Page 783 Appendix A MCU Electrical Specifications Table A-8. 5-V I/O Characteristics Conditions are 4.5 V < V < 5.5 V junction temperature from –40C to +150C, unless otherwise noted I/O Characteristics for all GPIO pins (defined in A.1.1.1/A-774). Port U, V Output Rise Time =5V, 10% to 90% of V Cload 47pF connected to GND, slew disabled —...
Page 784: A.1.8 Supply Currents
Appendix A MCU Electrical Specifications A.1.8 Supply Currents This section describes the current consumption characteristics of the device as well as the conditions for the measurements. A.1.8.1 Measurement Conditions Current is measured on VSUP. VDDX is connected to VDDA. It does not include the current to drive external loads.
Page 785 Appendix A MCU Electrical Specifications Table A-12. Peripheral Configurations for Run & Wait Current Measurement Peripheral Configuration SCI0/SCI1 Continuously transmit data (0x55) at speed of 19200 baud SPI0 Configured to master mode, continuously transmit data (0x55) at 1Mbit/s MSCAN0 Configured to loop-back mode using a bit rate of 500Kbits/s Configured to toggle its pins at the rate of 40kHz ADC0 The peripheral is configured to operate at its maximum specified...
Page 786: A.1.9 Adc Conversion Result Reference
Appendix A MCU Electrical Specifications Table A-14. Stop Current Characteristics Conditions are: V =12V Rating Symbol Unit Stop Current all modules off = -40C A SUPS = 25C A SUPS = 150C A SUPS Stop Current with CANPHY0 in standby = 25C A SUPS...
Page 787: B.1 Adc Operating Characteristics
Appendix B ADC Electricals Appendix B ADC Electricals This section describes the characteristics of the analog-to-digital converter. ADC Operating Characteristics The Table B-1 shows conditions under which the ADC operates. The following constraints exist to obtain full-scale, full range results: VSSA VRLV VRHVDDA...
Page 788 Appendix B ADC Electricals B.1.1.1 Port AD Output Drivers Switching PortAD output drivers switching can adversely affect the ADC accuracy whilst converting the analog voltage on other PortAD pins because the output drivers are supplied from the VDDA/VSSA ADC supply pins.
Page 789: B.1.2 Adc Accuracy
Appendix B ADC Electricals B.1.2 ADC Accuracy Table B-3. specifies the ADC conversion performance excluding any errors due to current injection, input capacitance and source resistance. B.1.2.1 ADC Accuracy Definitions For the following definitions see also <Cross Refs>Figure B-1. Differential non-linearity (DNL) is defined as the difference between two adjacent switching steps. –...
Page 790 Appendix B ADC Electricals 10-Bit Absolute Error Boundary Vi-1 $3FF 8-Bit Absolute Error Boundary $3FE $3FD $3FC $3FB $3FA $3F9 $3F8 $3F7 $3F6 $3F5 $3F4 $3F3 Ideal Transfer Curve 10-Bit Transfer Curve 8-Bit Transfer Curve 95 100 105 110 115 120 5000 + Figure B-1.
Page 791 Appendix B ADC Electricals Table B-3. ADC Conversion Performance 5V range Supply voltage 4.5 V < V < 5.5 V, 4.5V < V < 5.5 V. ( V ). f = 8.0 MHz ADCCLK The values are tested to be valid with no PortAD output drivers switching simultaneous with conversions. Rating Symbol Unit...
Page 792 Appendix B ADC Electricals S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 793: C.1 Reset, Oscillator And Pll
Appendix C PLL Electrical Specifications Reset, Oscillator and PLL C.1.1 Phase Locked Loop C.1.1.1 Jitter Information With each transition of the feedback clock, the deviation from the reference clock is measured and the input voltage to the VCO is adjusted accordingly.The adjustment is done continuously with no abrupt changes in the VCOCLK frequency.
Page 794 Appendix C PLL Electrical Specifications   ------------------------------------------------- -   N POSTDIV J(N) Figure C-2. Maximum Bus Clock Jitter Approximation (N = number of Bus Cycles) NOTE On timers and serial modules a prescaler will eliminate the effect of the jitter to a large extent.
Page 795: Appendix D
Appendix D IRC Electrical Specifications Table D-1. IRC electrical characteristics Rating Symbol Unit Junction Temperature - 40 to 150 Celsius 0.987 1.013 IRC1M_TRIM Internal Reference Frequency, factory trimmed S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 796: Appendix D
Appendix D IRC Electrical Specifications S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 797: E.1 Lcd Driver
Appendix E LCD Electrical Specifications LCD Driver Table E-1. LCD40F4B Driver Electrical Characteristics Characteristic Symbol Min. Typ. Max. Unit LCD Output Impedance(BP[3:0],FP[39:0]) k for outputs to charge to higher voltage level or to BP/FP LCD Output Current (BP[3:0],FP[39:0]) A for outputs to discharge to lower voltage level ex- BP/FP cept GND 1) Outputs measured one at a time, low impedance voltage source connected to the VLCD pin.
Page 798 Appendix E LCD Electrical Specifications characteristic is shown in Figure E-3.. The resistive output characteristic is also valid if an output is forced to GND or VLCD. resistive constant current 2/3VLCD 1/2VLCD 1/3VLCD Figure E-2. V transients (not to scale) 1/3, 1/2 or 2/3 VLCD BP/FP...
Page 799: F.1 Mscan Electrical Characteristics
Appendix F MSCAN Electrical Specifications MSCAN Electrical Characteristics Table F-1. MSCAN Wake-up Pulse Characteristics Conditions are shown in unless otherwise noted Table F-1. Rating Symbol Unit MSCAN wakeup dominant pulse filtered — — s MSCAN wakeup dominant pulse pass — —...
Page 800 Appendix F MSCAN Electrical Specifications S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 801: G.1 Nvm Timing Parameters
Appendix G NVM Electrical Parameters Appendix G NVM Electrical Parameters NVM Timing Parameters The time base for all NVM program or erase operations is derived from the bus clock using the FCLKDIV register. The frequency of this derived clock must be set within the limits specified as f .
Page 802: G.2 Nvm Reliability Parameters
Appendix G NVM Electrical Parameters Table G-1. NVM Timing Characteristics NVMBUS NVMOP Rating Symbol Unit cycles cycles Bus frequency — — NVMBUS NVM Operating frequency — 1.05 NVMOP Erase All Blocks 100066 33968 96.66 101.42 159.05 ERSALL Unsecure Flash 100066 34046 96.66 101.43...
Page 803: G.3 Nvm Factory Shipping Condition
Appendix G NVM Electrical Parameters Table G-2. NVM Reliability Characteristics Rating Symbol Unit Data retention at an average junction temperature of T = 85C — Years Javg NVMRET after up to 10,000 program/erase cycles Program Flash number of program/erase cycles 100K —...
Page 804 Appendix G NVM Electrical Parameters S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 805: H.1 Maximum Ratings
Appendix H BATS Electrical Specifications Appendix H BATS Electrical Specifications This section describe the electrical characteristics of the Supply Voltage Sense module. Maximum Ratings Table H-1. Maximum ratings of the Supply Voltage Sense - (BATS). Characteristics noted under conditions 5.5V  VSUP  18 V, -40°C  T ...
Page 806: H.2 Static Electrical Characteristics
Appendix H BATS Electrical Specifications Static Electrical Characteristics Table H-2. Static Electrical Characteristics - Supply Voltage Sense - (BATS). Characteristics noted under conditions 5.5V  VSUP  18 V, -40°C  T  150°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at T = 25°C under nominal conditions unless otherwise noted.
Page 807: H.3 Dynamic Electrical Characteristics
Appendix H BATS Electrical Specifications Table H-2. Static Electrical Characteristics - Supply Voltage Sense - (BATS). Characteristics noted under conditions 5.5V  VSUP  18 V, -40°C  T  150°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at T = 25°C under nominal conditions unless otherwise noted.
Page 808 Appendix H BATS Electrical Specifications S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 809 Appendix I VREG Electrical Specifications Table I-1. Voltage Regulator Electrical Characteristics C <= TJ <= 150C unless noted otherwise, VDDA, VDDM and VDDX must be shorted on the application board. Characteristic Symbol Typical Unit Input Voltages — 40 Output Voltage VDDX Full Performance Mode V >...
Page 810 Appendix I VREG Electrical Specifications Table I-1. Voltage Regulator Electrical Characteristics C <= TJ <= 150C unless noted otherwise, VDDA, VDDM and VDDX must be shorted on the application board. Characteristic Symbol Typical Unit Base Current For External PNP(VDDC) — —...
Page 811 Appendix J S12CANPHY Electrical Specifications Maximum Ratings Table J-1. Maximum Ratings Characteristics noted under conditions 5.5V <= VSUP <= 18 V, 4.75V <= VDDC <= 5.25V , -40°C < Tj < 150°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at T = 25°C under nominal conditions unless otherwise noted.
Page 812 Appendix J S12CANPHY Electrical Specifications Table J-2. Static Electrical Characteristics Characteristics noted under conditions 5.5V <= VSUP <= 18 V, 4.75V <= VDDC <= 5.25V >, -40°C < Tj < 150°C> unless otherwise noted. Typical values noted reflect the approximate parameter mean at T = 25°C under nominal conditions unless otherwise noted.
Page 813 Appendix J S12CANPHY Electrical Specifications Table J-2. Static Electrical Characteristics Characteristics noted under conditions 5.5V <= VSUP <= 18 V, 4.75V <= VDDC <= 5.25V >, -40°C < Tj < 150°C> unless otherwise noted. Typical values noted reflect the approximate parameter mean at T = 25°C under nominal conditions unless otherwise noted.
Page 814 Appendix J S12CANPHY Electrical Specifications Dynamic Electrical Characteristics Table J-3. Dynamic Electrical Characteristics Characteristics noted under conditions 5.5V <= VSUP <= 18 V, 4.75V <= VDDC <= 5.25V >, -40°C < Tj < 150°C> unless otherwise noted. Typical values noted reflect the approximate parameter mean at T = 25°C under nominal conditions unless otherwise noted.
Page 815 Appendix J S12CANPHY Electrical Specifications Table J-3. Dynamic Electrical Characteristics Characteristics noted under conditions 5.5V <= VSUP <= 18 V, 4.75V <= VDDC <= 5.25V >, -40°C < Tj < 150°C> unless otherwise noted. Typical values noted reflect the approximate parameter mean at T = 25°C under nominal conditions unless otherwise noted.
Page 816 Appendix J S12CANPHY Electrical Specifications S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 817 Appendix K Electrical Characteristics for the Oscillator (OSCLCPcr) OSCLCP Electrical characteristics Table K-1. XOSCLCP Characteristics Conditions are shown in unless otherwise noted Table K-1. Rating Symbol Unit Nominal crystal or resonator frequency Startup Current A Oscillator start-up time (4MHz) — UPOSC Oscillator start-up time (8MHz) —...
Page 818 Appendix K Electrical Characteristics for the Oscillator (OSCLCPcr) S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 819 Appendix L OSC32K Electrical Specifications Appendix L OSC32K Electrical Specifications DC Electrical Specifications Table L-1. OSC32K DC Electrical Specifications Characteristic Symbol OSC32K Supply Current V =5.0 A DDOSC — —  Allowed Impedence on 32K_EXTAL/XTAL pins lk_ext 32K_EXTAL Load Capacitance —...
Page 820 Appendix L OSC32K Electrical Specifications S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 821 Appendix M SPI Electrical Specifications Appendix M SPI Electrical Specifications This section provides electrical parametrics and ratings for the SPI. In Table M-1. the measurement conditions are listed. Table M-1. Measurement Conditions Description Value Unit Drive mode full drive mode —...
Page 822 Appendix M SPI Electrical Specifications (OUTPUT) (CPOL  0) (OUTPUT) (CPOL  1) (OUTPUT) MISO MSB IN BIT 6 . . . 1 LSB IN (INPUT) MOSI MASTER MSB OUT BIT 6 . . . 1 MASTER LSB OUT (OUTPUT) 1.
Page 823 Appendix M SPI Electrical Specifications [MHz] Figure M-3. Derating of maximum f to f ratio in Master Mode In Master Mode the allowed maximum f to f ratio (= minimum Baud Rate Divisor, pls. see SPI Block Guide) derates with increasing f , please see Figure M-3..
Page 824 Appendix M SPI Electrical Specifications (INPUT) (CPOL  0) (INPUT) (CPOL  1) (INPUT) MISO BIT 6 . . . 1 SLAVE LSB OUT SLAVE MSB (OUTPUT) note note MOSI MSB IN BIT 6 . . . 1 LSB IN (INPUT) NOTE: Not defined! Figure M-4.
Page 825 Appendix M SPI Electrical Specifications In Table M-3. the timing characteristics for slave mode are listed. Table M-3. SPI Slave Mode Timing Characteristics Characteristic Symbol Unit SCK Frequency — 14 eriod —  Enable Lead Time — — lead Enable Lag Time —...
Page 826 Appendix M SPI Electrical Specifications S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 827 Appendix N Ordering Information Appendix N Ordering Information The following figure provides an ordering partnumber example for the devices covered by this data book. There are two options when ordering a device. Customers must choose between ordering either the mask- specific partnumber or the generic / mask-independent partnumber.
Page 828 Appendix N Ordering Information S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 829 Appendix O Package Information Appendix O Package Information S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 830 Appendix O Package Information 144 LQFP S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 831 Appendix O Package Information S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 832 Appendix O Package Information S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 833 Appendix O Package Information 100 LQFP S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 834 Appendix O Package Information S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 835 Appendix O Package Information S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 836 Appendix O Package Information S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 837 Appendix P Detailed Register Address Map Appendix P Detailed Register Address Map Table P-1. Revision History Version Revision Description of Changes Number Date Rev 0.01 22-June-2011 Initial Version Rev 0.07 17-Feb-2012 Fix typos Rev 0.08 17-Oct-2012 Update for DBG/RTC/FTMRZ/CPMU etc register for 1N65E device correct PARTID description Rev 0.09 21-Nov-2012...
Page 838 Appendix P Detailed Register Address Map 0x0010–0x001F Interrupt Control module(INT) 0x0012- Reserved 0x0015 0x0016 INT_XGPRIO R XILVL[2:0] 0x0017 INT_CFADDR R INT_CFADDR[6:3] 0x0018 INT_CFDATA0 R RQST PRIOLVL[2:0] 0x0019 INT_CFDATA1 R RQST PRIOLVL[2:0] 0x001A INT_CFDATA2 R RQST PRIOLVL[2:0] 0x001B INT_CFDATA3 R RQST PRIOLVL[2:0] 0x001C INT_CFDATA4 R RQST...
Page 839 Appendix P Detailed Register Address Map 0x0070–0x00FF Memory Map Control Module(MMC) 0x0081 MMCECL ACC[3:0] ERR[3:0] 0x0082 MMCCCRH CPUU 0x0083 MMCCCRL CPUX CPUI 0x0084 Reserved 0x0085 MMCPCH CPUPC[23:16] 0x0086 MMCPCM CPUPC[15:8] 0x0087 MMCPCL CPUPC[7:0] 0x0088- Reserved 0x00FF 0x0100–0x017F Debug Module (DBG V1) Address Name Bit 7...
Page 840 Appendix P Detailed Register Address Map 0x0100–0x017F Debug Module (DBG V1) 0x0108 DBGSCR2 C3SC1 C3SC0 C2SC1 C2SC0 C1SC1 C1SC0 C0SC1 C0SC0 0x0109 DBGSCR3 C3SC1 C3SC0 C2SC1 C2SC0 C1SC1 C1SC0 C0SC1 C0SC0 R PTBOVF TRIGF EEVF 0x010A DBGEFR PTACT SSF2 SSF1 SSF0 0x010B DBGSR...
Page 841 Appendix P Detailed Register Address Map 0x0100–0x017F Debug Module (DBG V1) 0x0121- Reserved 0x0124 0x0125 DBGBAH DBGBA[23:16] 0x0126 DBGBAM DBGBA[15:8] 0x0127 DBGBAL DBGBA[7:0] 0x0128- Reserved 0x012F 0x0130 DBGCCTL INST reserved COMPE 0x0131- Reserved 0x0134 0x0135 DBGCAH DBGCA[23:16] 0x0136 DBGCAM DBGCA[15:8] 0x0137 DBGCAL DBGCA[7:0]...
Page 842 Appendix P Detailed Register Address Map 0x0100–0x017F Debug Module (DBG V1) 0x0141- Reserved 0x0144 0x0145 DBGDAH DBGDA[23:16] 0x0146 DBGDAM DBGDA[15:8] 0x0147 DBGDAL DBGDA[7:0] 0x0148- Reserved 0x017F 0x0180–0x01FF Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0...
Page 843 Appendix P Detailed Register Address Map 0x0200–0x037F Port Integration Module(PIM) Reserved 0x020F Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x0210– Reserved 0x021F 0x0220 PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 0x0221 PTB3 PTB2 PTB1 PTB0 PTIA7 PTIA6 PTIA5 PTIA4 PTIA3 PTIA2...
Page 844 Appendix P Detailed Register Address Map 0x0200–0x037F Port Integration Module(PIM) PTID7 PTID6 PTID5 PTID4 PTID3 PTID2 PTID1 PTID0 0x0243 PTID 0x0244 DDRC DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 0x0245 DDRD DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 0x0246 PERC PERC7...
Page 845 Appendix P Detailed Register Address Map 0x0200–0x037F Port Integration Module(PIM) 0x026A– Reserved 0x027F 0x0280 Reserved 0x0281 PTADL PTADL7 PTADL6 PTADL5 PTADL4 PTADL3 PTADL2 PTADL1 PTADL0 0x0282 Reserved R PTIADL7 PTIADL6 PTIADL5 PTIADL4 PTIADL3 PTIADL2 PTIADL1 PTIADL0 0x0283 PTIADL 0x0284 Reserved 0x0285 DDRADL DDRADL7 DDRADL6 DDRADL5 DDRADL4 DDRADL3 DDRADL2 DDRADL1 DDRADL0...
Page 846 Appendix P Detailed Register Address Map 0x0200–0x037F Port Integration Module(PIM) 0x029A– Reserved 0x02BF 0x02C0 PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 0x02C1 PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0 PTIT 0x02C2 DDRT DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 0x02C3...
Page 847 Appendix P Detailed Register Address Map 0x0200–0x037F Port Integration Module(PIM) 0x02D8– Reserved 0x02DE 0x02DF WOMS WOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0 0x02E0– Reserved 0x02EF 0x02F0 PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0...
Page 848 Appendix P Detailed Register Address Map 0x0200–0x037F Port Integration Module(PIM) 0x0322 DDRG DDRG7 DDRG6 DDRG5 DDRG4 DDRG3 DDRG2 DDRG1 DDRG0 0x0323 PERG PERG7 PERG6 PERG5 PERG4 PERG3 PERG2 PERG1 PERG0 0x0324 PPSG PPSG7 PPSG6 PPSG5 PPSG4 PPSG3 PPSG2 PPSG1 PPSG0 0x0325–...
Page 849 Appendix P Detailed Register Address Map 0x0200–0x037F Port Integration Module(PIM) 0x036E SRRV SRRV7 SRRV6 SRRV5 SRRV4 SRRV3 SRRV2 SRRV1 SRRV0 0x036F Reserved 0x0370– Reserved 0x037F 0x0380–0x039F Flash Module(FTMRZ) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0...
Page 850 Appendix P Detailed Register Address Map 0x0380–0x039F Flash Module(FTMRZ) 0x038E FCCOB1HI CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 0x038F FCCOB1LO CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 0x0390 FCCOB2HI CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 0x0391 FCCOB2LO CCOB7 CCOB6...
Page 851 Appendix P Detailed Register Address Map 0x03C0–0x03CF SRAM ECC Generator(SRAM_ECC) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved 0x03C3- 0x03C6 ECCDPTRH 0x03C7 DPTR[23:16] ECCDPTRM R 0x03C8 DPTR[15:8] ECCDPTRL 0x03C9 DPTR[7:1] Reserved 0x03CA-...
Page 852 Appendix P Detailed Register Address Map 0x0400–0x042F Timer Module (TIM1) 0x0404 TIM1TCNTH TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8 0x0405 TIM1TCNTL TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 0x0406 TIM1TSCR1 TSWAI TSFRZ TFFCA PRNT 0x0407 TIM1TTOV TOV7 TOV6 TOV5 TOV4 TOV3...
Page 853 Appendix P Detailed Register Address Map 0x0400–0x042F Timer Module (TIM1) 0x0424- Reserved 0x042B 0x042C TIM1OCPD OCPD7 OCPD6 OCPD5 OCPD4 OCPD3 OCPD2 OCPD1 OCPD0 0x042D Reserved 0x042E TIM1PTPSR PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 0x042F Reserved 0x0430–0x047F Reserved Address Name Bit 7 Bit 6...
Page 854 Appendix P Detailed Register Address Map 0x0480–0x04A7 Pulse-Width-Modulator (PWM) 0x0489 PWMSCLB Bit 7 5 4 3 0x048A - Reserved 0x048B Bit 7 0x048C PWMCNT0 Bit 7 0x048D PWMCNT1 Bit 7 0x048E PWMCNT2 Bit 7 0x048F PWMCNT3 Bit 7 0x0490 PWMCNT4 Bit 7 0x0491 PWMCNT5...
Page 855 Appendix P Detailed Register Address Map 0x0480–0x04A7 Pulse-Width-Modulator (PWM) 0x049C PWMDTY0 Bit 7 5 4 3 0x049D PWMDTY1 Bit 7 5 4 3 0x049E PWMDTY2 Bit 7 5 4 3 0x049F PWMDTY3 Bit 7 5 4 3 0x04A0 PWMDTY4 Bit 7 5 4 3 0x04A1 PWMDTY5...
Page 856 Appendix P Detailed Register Address Map 0x05C0–0x05EF Timer Module (TIM0) 0x05C5 TIM0TCNTL TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 0x05C6 TIM0TSCR1 TSWAI TSFRZ TFFCA PRNT 0x05C7 TIM0TTOV TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0 0x05C8 TIM0TCTL1 0x05C9 TIM0TCTL2 0x05CA TIM0TCTL3 EDG7B...
Page 857 Appendix P Detailed Register Address Map 0x05C0–0x05EF Timer Module (TIM0) 0x05ED Reserved 0x05EE TIM0PTPSR PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 0x05EF Reserved 0x05F0–0x05FF Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x05F0-...
Page 858 Appendix P Detailed Register Address Map 0x0600–0x063F Analog to Digital Converter (ADC) ADC0CO- 0x060B CON_IE[7:1] EOL_IE NIE_1 ADC0CO- 0x060C CON_IF[15:8] NIF_0 ADC0CO- 0x060D CON_IF[7:1] EOL_IF NIF_1 R CSL_IMD RVL_IMD 0x060E ADC0IMDRI_0 RIDX_IMD 0x060F ADC0IMDRI_1 R CSL_EOL RVL_EOL 0x0610 ADC0EOLRI 0x0611 Reserved 0x0612 Reserved...
Page 859 Appendix P Detailed Register Address Map 0x0600–0x063F Analog to Digital Converter (ADC) 0x061D ADC0CBP_0 CMD_PTR[23:16] 0x061E ADC0CBP_1 CMD_PTR[15:8] 0x061F ADC0CBP_2 CMD_PTR[7:2] RES_IDX[5:0] 0x0620 ADC0RIDX 0x0621 ADC0RBP_0 RES_PTR[19:16] 0x0622 ADC0RBP_1 RES_PTR[15:8] 0x0623 ADC0RBP_2 RES_PTR[7:2] CMDRES_OFF0[6:0] 0x0624 ADC0CROFF0 0x0625 CMDRES_OFF1[6:0] ADC0CROFF1 0x0626 Reserved Reserved 0x0627...
Page 860 Appendix P Detailed Register Address Map 0x06C0–0x06DF Clock and Power Management (CPMU_UHV) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CPMU 0x06C0 RESERVED00 CPMU 0x06C1 RESERVED01 CPMU 0x06C2 RESERVED02 0x06C3 CPMURFLG PORF LVRF...
Page 861 Appendix P Detailed Register Address Map 0x06C0–0x06DF Clock and Power Management (CPMU_UHV) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LVDS CPMU 0x06D1 LVIE LVIF LVCTL CPMU 0x06D2 APICLK APIES APIEA APIFE APIE...
Page 862 Appendix P Detailed Register Address Map 0x06E0–0x06EF Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x06E0- Reserved 0x06EF 0x06F0–0x06F7 Supply Voltage Sensor (BATS) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3...
Page 863 Appendix P Detailed Register Address Map 0x0700–0x0707 Serial Communication Interface (SCI0) 0x0702 SCI0ACR2 IREN TNP1 TNP0 BERRM1 BERRM0 BKDFE 0x0703 SCI0CR2 TCIE ILIE TDRE RDRF IDLE 0x0704 SCI0SR1 0x0705 SCI0SR2 AMAP TXPOL RXPOL BRK13 TXDIR 0x0706 SCI0DRH 0x0707 SCI0DRL 1 These registers are accessible if the AMAP bit in the SCI0SR2 register is set to zero. 2 These registers are accessible if the AMAP bit in the SCI0SR2 register is set to one.
Page 864 Appendix P Detailed Register Address Map 0x0710–0x0717 Serial Communication Interface (SCI1) TDRE RDRF IDLE 0x0714 SCI1SR1 0x0715 SCI1SR2 AMAP TXPOL RXPOL BRK13 TXDIR 0x0716 SCI1DRH 0x0717 SCI1DRL 1 These registers are accessible if the AMAP bit in the SCI1SR2 register is set to zero. 2 These registers are accessible if the AMAP bit in the SCI1SR2 register is set to one.
Page 865 Appendix P Detailed Register Address Map 0x0788–0x07BF Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0788- Reserved 0x07BF 0x07C0–0x07C7 Inter IC Bus (IIC0) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3...
Page 866 Appendix P Detailed Register Address Map 0x0800–0x083F CAN Controller (MSCAN0) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RXACT SYNCH 0x0800 CAN0CTL0 RXFRM CSWAI TIME WUPE SLPRQ INITRQ SLPAK INITAK 0x0801 CAN0CTL1 CANE...
Page 867 Appendix P Detailed Register Address Map 0x0800–0x083F CAN Controller (MSCAN0) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0814- CAN0IDMRx 0x0817 0x0818- CAN0IDAR4–7 0x081B 0x081C- CAN0IDMR4– 0x081F 0x0820- CAN0RXFG See 11.3.3” 0x082F 0x0830- CAN0TXFG...
Page 868 Appendix P Detailed Register Address Map 0x0998–0x9FF Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0998- Reserved 0x09FF 0x0A00–0x0A1F Liquid Crystal Display (LCD) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3...
Page 869 Appendix P Detailed Register Address Map 0x0A00–0x0A1F Liquid Crystal Display (LCD) 0x0A0E LCDRAM6 FP13BP3 FP13BP2 FP13BP1 FP13BP0 FP12BP3 FP12BP2 FP12BP1 FP12BP0 0x0A0F LCDRAM7 FP15BP3 FP15BP2 FP15BP1 FP15BP0 FP14BP3 FP14BP2 FP14BP1 FP14BP0 0x0A10 LCDRAM8 FP17BP3 FP17BP2 FP17BP1 FP17BP0 FP16BP3 FP16BP2 FP16BP1 FP16BP0 0x0A11 LCDRAM9...
Page 870 Appendix P Detailed Register Address Map 0x0A40–0x0A7F Motor Control (MC) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0A40 MCCTL0 MCPRE1 MCPRE0 MCSWAI FAST DITH MCTOIF 0x0A41 MCCTL1 RECIRC MCTOIE 0x0A42 MCPERH 0x0A43...
Page 871 Appendix P Detailed Register Address Map 0x0A40–0x0A7F Motor Control (MC) 0x0A64 MCDC2H 0x0A65 MCDC2L 0x0A66 MCDC3H 0x0A67 MCDC3L 0x0A68 MCDC4H 0x0A69 MCDC4L 0x0A6A MCDC5H 0x0A6B MCDC5L 0x0A6C MCDC6H 0x0A6D MCDC6L 0x0A6E MCDC7H 0x0A6F MCDC7L 0x0A70– Reserved 0x0A7F 0x0A80–0x0A87 Stepper Stall Detector (SSD0) Address Name Bit 7...
Page 872 Appendix P Detailed Register Address Map 0x0A80–0x0A87 Stepper Stall Detector (SSD0) 0x0A84 MDC0CNTH MDCCNT[15:8] 0x0A85 MDC0CNTL MDCCNT[7:0] ITGACC[15:8] 0x0A86 ITG0ACCH ITGACC[7:0] 0x0A87 ITG0ACCL 0x0A88–0x0A8F Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0A88- Reserved...
Page 873 Appendix P Detailed Register Address Map 0x0A98–0x0A9F Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0A98- Reserved 0x0A9F 0x0AA0–0x0AA7 Stepper Stall Detector (SSD2) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3...
Page 874 Appendix P Detailed Register Address Map 0x0AB0–0x0AB7 Stepper Stall Detector (SSD3) 0x0AB2 SSD3CTL RTZE SDCPU SSDWAI FTST ACLKS 0x0AB3 SSD3FLG MCZIF AOVIF 0x0AB4 MDC3CNTH MDCCNT[15:8] 0x0AB5 MDC3CNTL MDCCNT[7:0] ITGACC[15:8] 0x0AB6 ITG3ACCH ITGACC[7:0] 0x0AB7 ITG3ACCL 0x0AB8–0x0ADF Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4...
Page 875 Appendix P Detailed Register Address Map 0x0AE0–0x0AEF Real Time Clock (RTC) RTCCNTH 0x0AE8 RTCCNTH RTCCNTL RTCCNTL 0x0AE9 0x0AEA– Reserved 0x0AEC RTCSEC 0x0AED SEC5 SEC4 SEC3 SEC2 SEC1 SEC0 RTCMIN 0x0AEE MIN5 MIN4 MIN3 MIN2 MIN1 MIN0 RTCHR 0x0AEF 0x0AF0–0x0AFF Reserved Address Name Bit 7...
Page 876 Appendix P Detailed Register Address Map 0x0B00–0x0B17 Simple Sound Generator(SSG0) 0x0B08 AA10 SSG0AAH 0x0B09 SSG0AAL 0x0B0A AT10 SSG0ATH 0x0B0B SSG0ATL 0x0B0C DUR7 DUR6 DUR5 DUR4 DUR3 DUR2 DUR1 DUR0 SSG0DUR RNDIE 0x0B0D SSG0IE 0xC0E RNDI SSG0IF 0x0B0F RESERVED AMPB10 AMPB9 AMPB8 0x0B10 SSG0AMPBH...
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