Related Manuals for NXP Semiconductors K22F series
Summary of Contents for NXP Semiconductors K22F series
- Page 1 K22F Sub-Family Reference Manual Supports: MK22FN512VDC12, MK22FN512VLL12, MK22FN512VLH12, MK22FN512VMP12, MK22FN512VFX12, MK22FN512CAP12R, MK22FN512CBP12R, MK22FN256CAP12R Document Number: K22P121M120SF7RM Rev. 4, 08/2016...
- Page 2 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 3: Table Of Contents
Analog modules............................53 2.2.7 Timer modules............................. 53 2.2.8 Communication interfaces........................... 54 2.2.9 Human-machine interfaces.......................... 55 Orderable part numbers..............................55 Chapter 3 Chip Configuration Introduction...................................57 Core modules................................57 3.2.1 ARM Cortex-M4 Core Configuration......................57 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 4 3.5.2 Flash Memory Controller Configuration..................... 87 3.5.3 SRAM Configuration........................... 87 3.5.4 System Register File Configuration......................89 3.5.5 VBAT Register File Configuration......................90 3.5.6 EzPort Configuration........................... 91 3.5.7 FlexBus Configuration..........................92 Security..................................95 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 5 3.9.6 I2S configuration............................134 3.10 Human-machine interfaces............................137 3.10.1 GPIO configuration............................137 Chapter 4 Memory Map Introduction...................................139 System memory map..............................139 4.2.1 Aliased bit-band regions..........................141 4.2.2 Flash Access Control Introduction.......................142 Flash Memory Map...............................142 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 6 PORT digital filter clocking.........................162 5.7.6 LPTMR clocking............................162 5.7.7 RTC_CLKOUT and CLKOUT32K clocking....................163 5.7.8 USB FS OTG Controller clocking....................... 164 5.7.9 UART clocking............................165 5.7.10 LPUART0 clocking............................. 165 5.7.11 I2S/SAI clocking............................166 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 7 7.2.5 Clock Gating..............................185 Power Modes Description.............................185 Entering and exiting power modes..........................187 Power mode transitions..............................188 Power modes shutdown sequencing..........................189 Flash Program Restrictions............................190 Module Operation in Low Power Modes........................190 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 8 Debug Resets................................208 AHB-AP..................................209 ITM....................................209 Core Trace Connectivity............................... 210 9.10 TPIU....................................210 9.11 DWT..................................... 210 9.12 Debug in Low Power Modes............................211 9.12.1 Debug Module State in Low Power Modes....................211 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 9 Port Control and Interrupts (PORT) 11.1 Introduction...................................239 11.2 Overview..................................239 11.2.1 Features................................ 239 11.2.2 Modes of operation............................240 11.3 External signal description............................241 11.4 Detailed signal description............................241 11.5 Memory map and register definition..........................241 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 10 System Clock Gating Control Register 4 (SIM_SCGC4)................277 12.2.10 System Clock Gating Control Register 5 (SIM_SCGC5)................279 12.2.11 System Clock Gating Control Register 6 (SIM_SCGC6)................281 12.2.12 System Clock Gating Control Register 7 (SIM_SCGC7)................284 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 11 I2C Peripheral.............................. 327 13.4.2 SPI Peripheral.............................. 329 13.4.3 UART Peripheral............................331 13.4.4 USB peripheral.............................334 13.5 Get/SetProperty Command Properties..........................336 13.5.1 Property Definitions............................. 338 13.6 Kinetis Flashloader Status Error Codes........................339 Chapter 14 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 12 Power mode entry/exit sequencing......................362 15.4.3 Run modes..............................364 15.4.4 Wait modes..............................366 15.4.5 Stop modes..............................366 15.4.6 Debug in low power modes......................... 369 Chapter 16 Power Management Controller (PMC) 16.1 Introduction...................................371 16.2 Features..................................371 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 13 LLWU Flag 2 register (LLWU_F2)......................391 17.3.8 LLWU Flag 3 register (LLWU_F3)......................392 17.3.9 LLWU Pin Filter 1 register (LLWU_FILT1)....................394 17.3.10 LLWU Pin Filter 2 register (LLWU_FILT2)....................395 17.4 Functional description..............................396 17.4.1 LLS mode..............................397 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 14 General operation............................408 19.3.2 Arbitration..............................409 19.4 Initialization/application information........................... 410 Chapter 20 Peripheral Bridge (AIPS-Lite) 20.1 Introduction...................................411 20.1.1 Features................................ 411 20.1.2 General operation............................411 20.2 Memory map/register definition........................... 412 20.3 Functional description..............................412 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 15 Block parts..............................426 22.1.3 Features................................ 427 22.2 Modes of operation............................... 428 22.3 Memory map/register definition........................... 429 22.3.1 TCD memory............................... 429 22.3.2 TCD initialization............................429 22.3.3 TCD structure...............................429 22.3.4 Reserved memory and bit fields........................430 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 16 TCD Last Source Address Adjustment (DMA_TCDn_SLAST)..............474 22.3.29 TCD Destination Address (DMA_TCDn_DADDR)................... 475 22.3.30 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)..............475 22.3.31 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCDn_CITER_ELINKYES)......................476 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 17 Lockstep............................... 507 Chapter 23 External Watchdog Monitor (EWM) 23.1 Introduction...................................509 23.1.1 Features................................ 509 23.1.2 Modes of Operation............................. 510 23.1.3 Block Diagram............................. 511 23.2 EWM Signal Descriptions............................512 23.3 Memory Map/Register Definition..........................512 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 18 Watchdog disabled mode of operation......................524 24.3.6 Debug modes of operation........................... 524 24.4 Testing the watchdog..............................525 24.4.1 Quick test..............................526 24.4.2 Byte test................................526 24.5 Backup reset generator..............................527 24.6 Generated resets and interrupts.............................528 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 19 Memory Map/Register Definition..........................543 25.3.1 MCG Control 1 Register (MCG_C1)......................544 25.3.2 MCG Control 2 Register (MCG_C2)......................545 25.3.3 MCG Control 3 Register (MCG_C3)......................546 25.3.4 MCG Control 4 Register (MCG_C4)......................547 25.3.5 MCG Control 5 Register (MCG_C5)......................548 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 20 MCG mode switching..........................567 Chapter 26 Oscillator (OSC) 26.1 Introduction...................................577 26.2 Features and Modes..............................577 26.3 Block Diagram................................578 26.4 OSC Signal Descriptions.............................. 578 26.5 External Crystal / Resonator Connections........................579 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 21 External Crystal Connections............................591 27.4 Memory Map/Register Descriptions..........................591 27.5 Functional Description..............................591 27.6 Reset Overview................................592 27.7 Interrupts..................................592 Chapter 28 Flash Memory Controller (FMC) 28.1 Introduction...................................593 28.1.1 Overview..............................593 28.1.2 Features................................ 593 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 22 Configuration options..........................615 28.5.3 Speculative reads............................615 28.5.4 Flash Access Control (FAC) Function......................616 28.6 Initialization and application information........................627 Chapter 29 Flash Memory Module (FTFA) 29.1 Introduction...................................629 29.1.1 Features................................ 630 29.1.2 Block Diagram............................. 630 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 23 Chapter 30 EzPort 30.1 Overview..................................681 30.1.1 Block diagram.............................. 681 30.1.2 Features................................ 682 30.1.3 Modes of operation............................682 30.2 External signal descriptions............................683 30.2.1 EzPort Clock (EZP_CK)..........................683 30.2.2 EzPort Chip Select (EZP_CS)........................684 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 24 Bit ordering..............................705 31.4.6 Data transfer signals.............................705 31.4.7 Signal transitions............................705 31.4.8 Data-byte alignment and physical connections....................705 31.4.9 Address/data bus multiplexing........................707 31.4.10 Data transfer states............................708 31.4.11 FlexBus Timing Examples...........................709 31.4.12 Burst cycles..............................728 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 25 33.1 Introduction...................................751 33.1.1 Overview..............................751 33.2 Modes of operation............................... 752 33.2.1 Entering Normal mode..........................752 33.2.2 Entering Sleep mode............................ 752 33.3 Memory map and register definition..........................753 33.3.1 RNGA Control Register (RNG_CR)......................753 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 26 Status and Control Register 2 (ADCx_SC2)....................777 34.3.7 Status and Control Register 3 (ADCx_SC3)....................779 34.3.8 ADC Offset Correction Register (ADCx_OFS)...................780 34.3.9 ADC Plus-Side Gain Register (ADCx_PG)....................781 34.3.10 ADC Minus-Side Gain Register (ADCx_MG).................... 781 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 27 MCU wait mode operation...........................805 34.4.10 MCU Normal Stop mode operation......................805 34.4.11 MCU Low-Power Stop mode operation...................... 806 34.5 Initialization information.............................. 807 34.5.1 ADC module initialization example......................807 34.6 Application information..............................809 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 28 Low-pass filter............................. 839 35.4 CMP interrupts................................841 35.5 DMA support................................841 35.6 CMP Asynchronous DMA support..........................842 35.7 Digital-to-analog converter............................843 35.8 DAC functional description............................843 35.8.1 Voltage reference source select........................843 35.9 DAC resets..................................844 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 29 37.1.2 Features................................ 858 37.1.3 Modes of Operation............................. 859 37.1.4 VREF Signal Descriptions........................... 859 37.2 Memory Map and Register Definition..........................860 37.2.1 VREF Trim Register (VREF_TRM)......................860 37.2.2 VREF Status and Control Register (VREF_SC)..................861 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 30 38.3.9 DAC Interval Trigger n Control register (PDBx_DACINTCn)..............880 38.3.10 DAC Interval n register (PDBx_DACINTn)....................881 38.3.11 Pulse-Out n Enable register (PDBx_POEN)....................882 38.3.12 Pulse-Out n Delay register (PDBx_POnDLY).....................882 38.4 Functional description..............................883 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 31 Channel (n) Value (FTMx_CnV)......................... 909 39.3.8 Counter Initial Value (FTMx_CNTIN)......................909 39.3.9 Capture And Compare Status (FTMx_STATUS)..................910 39.3.10 Features Mode Selection (FTMx_MODE)....................912 39.3.11 Synchronization (FTMx_SYNC)......................... 914 39.3.12 Initial State For Channels Output (FTMx_OUTINIT).................916 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 32 Edge-Aligned PWM (EPWM) mode......................959 39.4.7 Center-Aligned PWM (CPWM) mode......................961 39.4.8 Combine mode............................. 963 39.4.9 Complementary mode..........................970 39.4.10 Registers updated from write buffers......................971 39.4.11 PWM synchronization..........................973 39.4.12 Inverting............................... 989 39.4.13 Software output control..........................990 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 33 Initialization Procedure..............................1026 Chapter 40 Periodic Interrupt Timer (PIT) 40.1 Introduction...................................1029 40.1.1 Block diagram.............................. 1029 40.1.2 Features................................ 1030 40.2 Signal description................................1030 40.3 Memory map/register description..........................1031 40.3.1 PIT Module Control Register (PIT_MCR)....................1031 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 34 Low Power Timer Counter Register (LPTMRx_CNR)................1046 41.4 Functional description..............................1047 41.4.1 LPTMR power and reset..........................1047 41.4.2 LPTMR clocking............................1047 41.4.3 LPTMR prescaler/glitch filter........................1047 41.4.4 LPTMR compare............................1049 41.4.5 LPTMR counter............................1049 41.4.6 LPTMR hardware trigger..........................1050 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 35 Time counter..............................1065 42.3.3 Compensation...............................1066 42.3.4 Time alarm..............................1066 42.3.5 Update mode..............................1067 42.3.6 Register lock..............................1067 42.3.7 Access control.............................. 1067 42.3.8 Interrupt................................1067 Chapter 43 Universal Serial Bus Full Speed OTG Controller (USBFSOTG) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 36 Interrupt Status register (USBx_ISTAT)..................... 1090 43.4.10 Interrupt Enable register (USBx_INTEN)....................1091 43.4.11 Error Interrupt Status register (USBx_ERRSTAT)..................1093 43.4.12 Error Interrupt Enable register (USBx_ERREN)..................1094 43.4.13 Status register (USBx_STAT)........................1095 43.4.14 Control register (USBx_CTL)........................1096 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 37 OTG dual role A device operation....................... 1114 43.7.2 OTG dual role B device operation....................... 1115 43.8 Device mode IRC48 operation............................1117 Chapter 44 USB Voltage Regulator (VREG) 44.1 Introduction...................................1119 44.1.1 Overview..............................1119 44.1.2 Features................................ 1120 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 38 PUSH TX FIFO Register In Master Mode (SPIx_PUSHR)................ 1147 45.3.8 PUSH TX FIFO Register In Slave Mode (SPIx_PUSHR_SLAVE)............1149 45.3.9 POP RX FIFO Register (SPIx_POPR)......................1149 45.3.10 Transmit FIFO Registers (SPIx_TXFRn)....................1150 45.3.11 Receive FIFO Registers (SPIx_RXFRn)......................1150 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 39 I2C Address Register 1 (I2Cx_A1)......................1185 46.3.2 I2C Frequency Divider register (I2Cx_F)....................1185 46.3.3 I2C Control Register 1 (I2Cx_C1)....................... 1186 46.3.4 I2C Status register (I2Cx_S)........................1188 46.3.5 I2C Data I/O register (I2Cx_D)........................1190 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 40 Detailed signal descriptions......................... 1218 47.3 Memory map and registers............................1219 47.3.1 UART Baud Rate Registers: High (UARTx_BDH)..................1224 47.3.2 UART Baud Rate Registers: Low (UARTx_BDL)..................1225 47.3.3 UART Control Register 1 (UARTx_C1)..................... 1226 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 41 UART 7816 Error Threshold Register (UARTx_ET7816)................1253 47.3.30 UART 7816 Transmit Length Register (UARTx_TL7816)................ 1254 47.3.31 UART 7816 ATR Duration Timer Register A (UARTx_AP7816A_T0)............1254 47.3.32 UART 7816 ATR Duration Timer Register B (UARTx_AP7816B_T0)............ 1255 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 42 Overrun (OR) flag implications........................1297 47.8.5 Overrun NACK considerations........................1298 47.8.6 Match address registers..........................1299 47.8.7 Modem feature............................. 1299 47.8.8 IrDA minimum pulse width......................... 1300 47.8.9 Clearing 7816 wait timer (WT, BWT, CWT) interrupts................1300 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 43 Interrupts and status flags..........................1335 Chapter 49 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI) 49.1 Introduction...................................1337 49.1.1 Features................................ 1337 49.1.2 Block diagram.............................. 1337 49.1.3 Modes of operation............................1338 49.2 External signals................................1339 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 44 49.4.1 SAI clocking..............................1364 49.4.2 SAI resets..............................1366 49.4.3 Synchronous modes............................. 1367 49.4.4 Frame sync configuration..........................1367 49.4.5 Data FIFO..............................1368 49.4.6 Word mask register............................1371 49.4.7 Interrupts and DMA requests........................1371 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 45 Modes of operation............................1384 51.2 External signal description............................1386 51.2.1 TCK—Test clock input..........................1386 51.2.2 TDI—Test data input........................... 1386 51.2.3 TDO—Test data output..........................1386 51.2.4 TMS—Test mode select..........................1386 51.3 Register description..............................1387 51.3.1 Instruction register............................1387 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 46 Functional description..............................1389 51.4.1 JTAGC reset configuration.......................... 1389 51.4.2 IEEE 1149.1-2001 (JTAG) Test Access Port....................1389 51.4.3 TAP controller state machine........................1389 51.4.4 JTAGC block instructions..........................1391 51.4.5 Boundary scan..............................1394 51.5 Initialization/Application information.......................... 1394 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 47: About This Document
Hexadecimal number. For example, the hexadecimal equivalent of the number 60 is written 3Ch. In some cases, hexadecimal numbers are shown with the prefix 0x. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 48: Typographic Notation
Write 1 to clear: Refers to a register bitfield that must be written as 1 to be "cleared." K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 49: Introduction
• External memory or peripheral bus interface: FlexBus • Serial programming interface: EzPort Clocks • Multiple clock generation options available from internally- and externally- generated clocks Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 50: Arm® Cortex®-M4 Core Modules
The address is fetched via the instruction port allowing parallel register stacking and look-up. The first sixteen entries are allocated to ARM internal sources with the others mapping to MCU-defined interrupts. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 51: System Modules
The WDOG monitors internal system operation and forces a reset in case of failure. It can run from an independent 1 KHz low power oscillator with a programmable refresh window to detect deviations in program flow or system frequency. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 52: Memories And Memory Interfaces
The RTC oscillator has an independent power supply and supports a 32 kHz crystal oscillator to feed the RTC clock. Optionally, the RTC oscillator can replace the system oscillator as the main oscillator source. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 53: Security And Integrity Modules
• Positive transition of trigger event signal initiates the counter • Supports two triggered delay output signals, each with an independently- controlled delay from the trigger event Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 54: Communication Interfaces
• 32-bit seconds counter with 32-bit Alarm • 16-bit Prescaler with compensation that can correct errors between 0.12 ppm and 3906 ppm 2.2.8 Communication interfaces The following communication interfaces are available on this device: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 55: Human-Machine Interfaces
128 KB MK22FN512VLL12 120 MHz LQFP 512 KB 128 KB MK22FN512VLH12 120 MHz LQFP 512 KB 128 KB MK22FN512VMP12 120 MHz MAPBGA 512 KB 128 KB Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 56 MK22FN512VFX12 120 MHz 512 KB 128 KB MK22FN512CAP12R 120 MHz WLCSP 512 KB 128 KB MK22FN512CBP12R 120 MHz WLCSP 512 KB 128 KB MK22FN256CAP12R 120 MHz WLCSP 256 KB 128 KB K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 57: Chip Configuration
3.2.1 ARM Cortex-M4 Core Configuration This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at arm.com. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 58 Data code (DCODE) bus System bus The system bus is connected to a separate master port on the crossbar. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 59: Nested Vectored Interrupt Controller (Nvic) Configuration
3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at arm.com. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 60 The pin the NMI signal is multiplexed on, must be configured for the NMI function to generate the non-maskable interrupt request. 3.2.2.3 Interrupt channel assignments The interrupt source assignments are defined in the following table. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 61 DMA channel 7 transfer complete 0x0000_0060 DMA channel 8 transfer complete 0x0000_0064 DMA channel 9 transfer complete 0x0000_0068 DMA channel 10 transfer complete 0x0000_006C DMA channel 11 transfer complete Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 62 0x0000_00CC UART2 Single interrupt vector for UART status sources 0x0000_00D0 UART2 Single interrupt vector for UART error sources 0x0000_00D4 — — 0x0000_00D8 — — Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 63 — 0x0000_0150 — — 0x0000_0154 — — 0x0000_0158 — — 0x0000_015C FTM3 Single interrupt vector for all sources 0x0000_0160 DAC1 — 0x0000_0164 ADC1 — 1. Indicates the NVIC's interrupt source number. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 64 NVICIPR14 bitfield range is 20-23 Therefore, the following bitfield locations are used to configure the LPTMR interrupts: • NVICISER1[26] • NVICICER1[26] • NVICISPR1[26] • NVICICPR1[26] • NVICIABR1[26] • NVICIPR14[23:20] K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 65: Asynchronous Wake-Up Interrupt Controller (Awic) Configuration
Pin interrupts Port Control Module - Any enabled pin interrupt is capable of waking the system ADCx The ADC is functional when using internal clock source Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 66: Fpu Configuration
Full description ARM Cortex-M4 Technical Reference Manual System memory map System memory map Clocking Clock Distribution Power Management Power Management Transfers ARM Cortex M4 core ARM Cortex-M4 core Private Peripheral Bus (PPB) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 67: System Modules
(SIM) Figure 3-6. SIM configuration Table 3-10. Reference links to related information Topic Related module Reference Full description System memory map System memory map Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 68: System Mode Controller (Smc) Configuration
Reference Full description System Mode Controller (SMC) System memory map System memory map Power management Power management Power management controller (PMC) Low-Leakage Wakeup LLWU Unit (LLWU) Reset Control Module Reset (RCM) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 69: Pmc Configuration
Full description LLWU System memory map System memory map Clocking Clock distribution Power management Power management chapter Power Management Power Management Controller (PMC) Controller (PMC) Mode Controller Wake-up requests LLWU wake-up sources K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 70 2. Requires the peripheral and the peripheral interrupt to be enabled. The LLWU's WUME bit enables the internal module flag as a wakeup input. After wakeup, the flags are cleared based on the peripheral clearing mechanism. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 71: Mcm Configuration
Private Peripheral Bus (PPB) 3.3.6 Crossbar-Light Switch Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 72 Crossbar switch master USB FS/LS USB FS/LS Crossbar switch slave Flash Flash Crossbar switch slave Peripheral bridges Peripheral bridge Crossbar switch slave GPIO controller GPIO controller Crossbar switch slave FlexBus/ FlexBus K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 73: Peripheral Bridge Configuration
3.3.7 Peripheral Bridge Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 74: Dma Request Multiplexer Configuration
3.3.8 DMA request multiplexer configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 75 Source module Source description Async DMA number capable — Channel disabled Reserved Not used UART0 Receive UART0 Transmit UART1 Receive UART1 Transmit UART2 Receive UART2 Transmit Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 76 Channel 4 FTM3 Channel 5 FTM3 Channel 6 FTM3 Channel 7 ADC0 — ADC1 — CMP0 — CMP1 — Reserved — DAC0 — DAC1 — Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 77: Dma Controller Configuration
PIT/DMA Periodic Trigger Assignments 3.3.9 DMA Controller Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 78: External Watchdog Monitor (Ewm) Configuration
3.3.10 External Watchdog Monitor (EWM) Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 79 3.3.10.2 EWM low-power modes This table shows the EWM low-power modes and the corresponding chip low-power modes. Table 3-23. EWM low-power modes Module mode Chip mode Wait Wait, VLPW Stop Stop, VLPS, LLS K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 80: Watchdog Configuration
This table shows the WDOG module clocks and the corresponding chip clocks. Table 3-25. WDOG clock connections Module clock Chip clock LPO Oscillator 1 kHz LPO Clock Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 81: Clock Modules
3.4 Clock modules 3.4.1 MCG Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 82 RTC 32kHz oscillator output. RTC clock is derived from external crystal circuit associated with RTC. OSCCLK1 - Oscillator IRC48MCLK. Derived from internal 48 MHz oscillator. Reserved — Clock Distribution for more details on these clocks. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 83: Osc Configuration
MCG chapters for more details. 3.4.3 RTC OSC configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 84: Memories And Memory Interfaces
Table 3-31. Reference links to related information Topic Related module Reference Full description Flash memory System memory map System memory map Clocking Clock Distribution Transfers Flash memory Flash memory controller controller Register access Peripheral bridge Peripheral bridge K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 85 The on-chip Flash is implemented in a portion of the allocated Flash range to form a contiguous block in the memory map beginning at address 0x0000_0000. See Flash Memory Sizes for details of supported ranges. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 86 See the EzPort chapter for more details. 3.5.1.8 FTF_FOPT Register The flash memory's FTF_FOPT register allows the user to customize the operation of the MCU at boot time. See FOPT boot options for details of its definition. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 87: Flash Memory Controller Configuration
See Crossbar-Light Switch Configuration for details on the master port assignments. 3.5.3 SRAM Configuration This section summarizes how the module has been configured in the chip. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 88 The amount of SRAM for the devices covered in this document is shown in the following table. Device SRAM_L size SRAM_U size Total SRAM (KB) Address Range (KB) (KB) MK22FN512VDC12 0x1FFF_0000-0x2000_FFFF MK22FN512VLL12 0x1FFF_0000-0x2000_FFFF MK22FN512VLH12 0x1FFF_0000-0x2000_FFFF Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 89: System Register File Configuration
Figure 3-23. System Register file configuration Table 3-34. Reference links to related information Topic Related module Reference Full description Register file Register file System memory map System memory map Clocking Clock distribution Power management Power management K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 90: Vbat Register File Configuration
This device includes a 32-byte register file that is powered in all power modes and is powered by VBAT. The VBAT Register file is made up of eight 4-byte registers RFVBAT_REGn, where n ranges from 0 to 7. It is only reset during VBAT power-on reset. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 91: Ezport Configuration
The FOPT register is loaded from the flash option byte. If the flash option byte is modified the new value takes effect for any subsequent resets, until the value is changed again. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 92: Flexbus Configuration
The multiplexing of the FlexBus address and data signals is controlled by the port control module. However, the multiplexing of some of the FlexBus control signals are controlled by the port control and FlexBus modules. The port control module registers control K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 93 FlexBus or another module signals are available on the external pin, while the FlexBus's CSPMCR register configures which FlexBus signals are available from the modules. The control signals are grouped as illustrated: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 94 Group1 FB_TS Reserved FB_CS4 FB_TSIZ0 Group2 FB_BE_31_24 External Reserved Pins FB_CS5 FB_TSIZ1 Group3 FB_BE_23_16 Reserved FB_TBST FB_CS2 Group4 FB_BE_15_8 Reserved FB_TA FB_CS3 Group5 FB_BE_7_0 Reserved Figure 3-27. FlexBus control signal multiplexing K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 95: Security
FlexBus chapter. 3.6 Security 3.6.1 CRC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 96: Rng Configuration
(RNG) Figure 3-29. RNG configuration Table 3-39. Reference links to related information Topic Related module Reference Full description System memory map System memory map Clocking Clock distribution Power management Power management K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 97: Analog
The number of ADC channels present on the device is determined by the pinout of the specific device package. For details regarding the number of ADC channel available on a particular package, refer to the signal multiplexing chapter of this MCU. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 98 Reserved 01011 AD11 Reserved Reserved 01100 AD12 Reserved ADC0_SE12 01101 AD13 Reserved ADC0_SE13 01110 AD14 Reserved ADC0_SE14 01111 AD15 Reserved ADC0_SE15 10000 AD16 Reserved ADC0_SE16 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 99 Reserved ADC1_SE6a 00111 AD7a Reserved ADC1_SE7a 00100 AD4b Reserved ADC1_SE4b 00101 AD5b Reserved ADC1_SE5b 00110 AD6b Reserved ADC1_SE6b 00111 AD7b Reserved ADC1_SE7b 01000 Reserved ADC1_SE8 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 100 The following figure shows the assignment of ADCx_SEn channels a and b through a MUX selection to ADC. To select between alternate set of channels, refer to ADCx_CFG2[MUXSEL] bit settings for more details. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 101 There are other pins on this device that have a similar interleave configuration, including the plus side of differential pair pins available (for example ADC0_DP0 and ADC1_DP3). Refer to the Signal Multiplexing and Pin Assignments table for this device. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 102 Selected source 0000 PDB external trigger pin input (PDB0_EXTRG) 0001 CMP0 output 0010 CMP1 output 0011 Reserved 0100 PIT trigger 0 0101 PIT trigger 1 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 103 1. For ADC operation in Compute only, PSTOP1, Stop and VLPS, ADACK and the alternate clock sources are allowed clock sources. Note however that ALTCLK2 is force disabled and therefore not available in VLPS. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 104: Cmp Configuration
System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.7.2.1 CMP input connections The following table shows the fixed internal connections to the CMP. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 105 LPTMR configuration. In Time Counter mode with prescaler enabled, the delay is 1/2 Prescaler output period. In Time Counter mode with prescaler bypassed, the delay is 1/2 Prescaler clock period. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 106: 12-Bit Dac Configuration
The DAC includes a FIFO for DMA support. 3.7.3.2 12-bit DAC Output The output of the DAC can be placed on an external pin or set as one of the inputs to the analog comparator or ADC. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 107: Vref Configuration
Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.7.4.1 VREF Overview This device includes a voltage reference (VREF) to supply an accurate 1.2 V voltage output. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 108: Timers
Table 3-50. Reference links to related information Topic Related module Reference Full description System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 109 FTM external trigger register (EXTTRIG) 1011 FTM3 initialization trigger and channel triggers, as programmed in the FTM external trigger register (EXTTRIG) 1100 RTC Alarm 1101 RTC Seconds 1110 LPTMR Output 1111 Software Trigger K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 110 The application code can set the PDBx_CHnC1[BB] bits to configure the PDB pre- triggers as a single chain or several chains. 3.8.1.4 PDB Interval Trigger Connections to DAC In this MCU, PDB interval trigger connections to DAC are implemented as follows. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 111: Flextimer Configuration
31:2 - Reserved 3.8.2 FlexTimer Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 112 FTM1 Quadrature decoder or general purpose FTM2 Quadrature decoder or general purpose FTM3 3-phase motor + 2 general purpose or stepper motor 1. Only channels 0 and 1 are available. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 113 • FTM2 FAULT1 = CMP1 output • FTM3 FAULT0 = FTM3_FLT0 pin or CMP0 output 3.8.2.6 FTM Hardware Triggers The FTM synchronization hardware triggers are connected in the chip as follows: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 114 When the USB start of frame pulse option is selected as an FTM channel input capture, disable the USB SOF token interrupt in the USB Interrupt Enable register (INTEN[SOFTOKEN]) to avoid USB enumeration conflicts. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 115 FTM1_CH1. The diagram below shows the implementation for FTM0. FTM3 has similar implementation controlled by SIM_SOPT8[FTM3CHySRC] on each of its 8 channels with modulation possible via FTM2_CH1. See SIM Block Guide for further information. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 116 This chip provides the optional FTM global time base feature (see Global time base (GTB)). FTM0 provides the only source for the FTM global time base. The other FTM modules can share the time base as shown in the following figure: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 117: Pit Configuration
“debug halt mode". 3.8.3 PIT Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 118: Low-Power Timer Configuration
SIM_SOPT7[ADCxTRGSEL] fields. For more details, refer to SIM chapter. 3.8.4 Low-power timer configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 119 LPO — 1 kHz clock (not available in VLLS0 mode) ERCLK32K — secondary external reference clock OSCERCLK_UNDIV — Undivided external reference clock (not available in VLLS0 mode) Clock Distribution for more details on these clocks. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 120: Rtc Configuration
Figure 3-44. RTC configuration Table 3-59. Reference links to related information Topic Related module Reference Full description System memory map System memory map Clocking Clock Distribution Power management Power management K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 121: Communication Interfaces
• Status detection and wakeup functions for USB data pins, VBUS pin, and OTG ID pin. • IRC48 with clock recovery block to eliminate the 48MHz crystal. This is available for USB device mode only. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 122 • In LLS/VLLS, if the GPIO pins chosen to detect VBUS and OTG ID are selected from those pins which are inputs to the LLWU, transitions on them can generate a wakeup. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 123 VDD. The USB regulator must be enabled by default to power the MCU. When connected to a USB host, the input source of this regulator is switched to the USB bus supply from the Li-ion battery. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 124 VDD. The USB regulator must be enabled by default to power the MCU, then to power USB transceiver or external sensor. To PMC and Pads VOUT33 Cstab Chip TYPE A VREGIN VBUS Regulator USB0_DP XCVR USB0_DM Controller Figure 3-49. USB regulator bus supply K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 125 3.9.1.5 USB Voltage Regulator Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 126: Spi Configuration
Peripheral bridge Register access Module signals Signal multiplexing Figure 3-52. SPI configuration Table 3-62. Reference links to related information Topic Related module Reference Full description Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 127 CTAR0 is used, and a subset of its bitfields sets the slave transfer attributes. 3.9.2.4 TX FIFO size Table 3-63. SPI transmit FIFO size SPI Module Transmit FIFO size SPI0 SPI1 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 128 Here are the steps to use a GPIO to create a wakeup upon reception of SPI data in slave mode: 1. Point the GPIO interrupt vector to the desired interrupt handler. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 129 8-bit/16-bit write to the transmit word into a 32-bit write that pushes both the command word and transmit word into the TX FIFO (PUSH TX FIFO Register In Master Mode) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 130: I2C Configuration
Signal Multiplexing 3.9.3.1 I2C Instantiation Information This device has two I C modules. The I2C module includes SMBus support and DMA support. It also has optional address match wakeup in Stop/VLPS mode. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 131: Uart Configuration
1. Standard features of all UARTs: • RS-485 support • Hardware flow control (RTS/CTS) • 9-bit UART to support address mark with parity • MSB/LSB configuration on data K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 132 The error interrupt combines the following interrupt sources: Source UART 0 UART 1 UART 2 Receiver overrun Noise flag Framing error Parity error Transmitter buffer overflow Receiver buffer overflow Receiver buffer underflow Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 133: Lpuart Configuration
Table 3-69. Reference links to related information Topic Related module Reference Full description LPUART0 LPUART System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 134: I2S Configuration
Port control Signal Multiplexing 3.9.6.1 Instantiation information This device contains one I S module. As configured on the device, module features include: • TX data lines: 1 • RX data lines: 1 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 135 The following table shows the input clock selection options on this device. Table 3-71. I2S0 MCLK input clock selection MCR[MICS] Clock Selection System clock OSC0ERCLK Not supported MCGPLLCLK, MCGFLLCLK, or IRC48MCLK K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 136 Audio Master Clock that remains operating in Stop mode. The SAI transmitter and/or receiver can generate an asynchronous interrupt to wake the CPU from Stop mode. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 137: Human-Machine Interfaces
3.10 Human-machine interfaces 3.10.1 GPIO configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 138 PTD7, PTC3, and PTC4. All other GPIO support normal drive option only. PTA4 includes a passive input filter that is enabled or disabled by PORTA_PCR4[PFE] control. This reset default is to have this function disabled. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 139: Memory Map
RAM and peripheral address spaces. This functionality maps each 32-bit word of the aliased address space to a unique bit in the underlying RAM or peripheral address space to support single-bit insert and extract operations from the processor. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 140 1. EzPort master port is statically muxed with DMA master port. Access rights to AIPS-Lite peripheral bridge and general purpose input/output (GPIO) module address space is limited to the core, DMA and EzPort. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 141: Aliased Bit-Band Regions
• a value of 0x0000_0000 to indicate the target bit is clear • a value of 0x0000_0001 to indicate the target bit is set Bit-band region Alias bit-band region Figure 4-1. Alias bit-band mapping K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 142: Flash Access Control Introduction
4.3 Flash Memory Map The flash memory and the flash registers are located at different base addresses as shown in the following figure. The base address for each is specified in System memory map. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 143: Alternate Non-Volatile Irc User Trim Description
The on-chip RAM is split in two regions: SRAM_L and SRAM_U. The RAM is implemented such that the SRAM_L and SRAM_U ranges form a contiguous block in the memory map. See SRAM Configuration for details. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 144: Peripheral Bridge (Aips-Lite) Memory Map
ACTLR[DISDEFWBUF]. However, disabling buffered writes is likely to degrade system performance much more than simply performing the required memory serialization for the situations that truly require it. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 145 0x4001_B000 — 0x4001_C000 — 0x4001_D000 — 0x4001_E000 — 0x4001_F000 Flash memory controller 0x4002_0000 Flash memory 0x4002_1000 DMA channel mutiplexer 0x4002_2000 — 0x4002_3000 — 0x4002_4000 — Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 146 — 0x4004_7000 SIM low-power logic 0x4004_8000 System integration module (SIM) 0x4004_9000 Port A multiplexing control 0x4004_A000 Port B multiplexing control 0x4004_B000 Port C multiplexing control Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 147 0x4006_9000 — 0x4006_A000 UART 0 0x4006_B000 UART 1 0x4006_C000 UART 2 0x4006_D000 — 0x4006_E000 — 0x4006_F000 — 0x4007_0000 — 0x4007_1000 — 0x4007_2000 USB OTG FS/LS Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 148: Private Peripheral Bus (Ppb) Memory Map
System Control Space (SCS) (for NVIC and FPU) 0xE000_F000–0xE003_FFFF Reserved 0xE004_0000–0xE004_0FFF Trace Port Interface Unit (TPIU) 0xE004_1000–0xE004_1FFF Reserved 0xE004_2000–0xE004_2FFF Reserved 0xE004_3000–0xE004_3FFF Reserved 0xE004_4000–0xE007_FFFF Reserved 0xE008_0000–0xE008_0FFF Miscellaneous Control Module (MCM) 0xE008_1000–0xE008_1FFF Reserved Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 149 Chapter 4 Memory Map Table 4-3. PPB memory map (continued) System 32-bit Address Range Resource 0xE008_2000–0xE00F_EFFF Reserved 0xE00F_F000–0xE00F_FFFF ROM Table - allows auto-detection of debug components K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 150 Private Peripheral Bus (PPB) memory map K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 151: Clock Distribution
SIM module. Reference those sections for detailed register and bit descriptions. 5.3 High-Level device clocking diagram The following system oscillator, MCG, and module registers control the multiplexers, dividers, and clock gates shown in the below figure: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 152: Clock Definitions
CG — Clock gate Note: See subsequent sections for details on where these clocks are used. Figure 5-1. Clocking diagram 5.4 Clock definitions The following table describes the clocks in the previous block diagram. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 153: Device Clock Summary
MCGOUTCLK Up to 120 MHz Up to 120 MHz Up to 4 MHz In all stop modes except for partial Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 154 30-40 kHz, or 30-40 kHz (low- range crystal) or Stop mode and 3-32 MHz (crystal) 3-32 MHz (crystal) OSC_CR[EREFST Up to 16 MHz EN] cleared (high-range crystal) Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 155 Up to 120 MHz Up to 4 MHz System clock or Trace is disabled MCGOUTCLK LPUART0 clock Up to 100 MHz Up to 100MHz Up to 16MHz MCGFLLCLK or LPUART0 is disabled IRC48MCLK or K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 156: Internal Clocking Requirements
The following are a few of the more common clock configurations for this device: Option 1: Clock Frequency Core clock 50 MHz System clock 50 MHz Bus clock 50 MHz FlexBus clock 25 MHz Flash clock 25 MHz Option 2: Run K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 157: Clock Divider Values After Reset
5.5.2 VLPR mode clocking The clock dividers cannot be changed while in VLPR mode. They must be programmed prior to entering VLPR mode to guarantee: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 158: Clock Gating
System clock — — cJTAG, JTAGC — — JTAG_CLK System modules System clock — — DMA Mux Bus clock — — Port control Bus clock — Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 159 Communication interfaces USB FS OTG System clock USB FS clock — DSPI Bus clock — DSPI_SCK Bus clock — I2C_SCL UART0, UART1 System clock — — Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 160: Pmc 1-Khz Lpo Clock
MCG_C7[OSCSEL]=10) and either MCG is configured in an external clocking mode (PBE, BLPE, PEE, FBE or FEE) or MCG_C5[PLLCLKEN0] = 1. • SIM Control register selects IRC48 MHz clock — enabled when SIM_SOPT2[PLLFLLSEL]=11 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 161: Wdog Clocking
The WDOG may be clocked from two clock sources as shown in the following figure. WDOG clock Bus clock WDOG_STCTRLH[CLKSRC] Figure 5-2. WDOG clock generation 5.7.4 Debug trace clock The debug trace clock source can be clocked as shown in the following figure. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 162: Port Digital Filter Clocking
The prescaler and glitch filters in each of the LPTMRx modules can be clocked as shown in the following figure. NOTE The chosen clock must remain enabled if the LPTMRx is to continue operating in all required low-power modes. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 163: Rtc_Clkout And Clkout32K Clocking
The CLKOUT32K function is available in all modes of operation. In VLLS0 mode only the RTC oscillator is available. PTE0 is available in all packages for this device. PTE26 is not available in 64-pin packages for this device. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 164: Usb Fs Otg Controller Clocking
For the USB FS OTG controller to operate, the minimum system clock frequency is 20 MHz. The USB OTG controller also requires a 48 MHz clock. The clock source options are shown below. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 165: Uart Clocking
The LPUART0 module has a selectable clock as shown in the following figure. NOTE The chosen clock must remain enabled if the LPUART0 is to continue operating in all required low-power modes. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 166: I2S/Sai Clocking
The transmitter and receiver can independently select between the bus clock and the audio master clock to generate the bit clock. The MCLK and BCLK source options appear in the following figure. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 167 OSCERCLK Clock MCLK System Clock Divider BCLK Divider Bus Clock BCLK_IN [MSEL] [DIV] [BCD] SIM_SOPT2[PLLFLLSEL] I2Sx_MCR[MOE] I2Sx_MDR[FRACT,DIVIDE] I2Sx_MCR[MICS] MCLK_IN MCLK_OUT Direction Control Pad Interface Logic Figure 5-9. I S/SAI clock generation K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 168 Module clocks K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 169: Reset And Boot
The MCU exits reset in functional mode that is controlled by EZP_CS pin to select between the single chip (default) or serial flash programming (EzPort) modes. See Boot options for more details. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 170: Reset
During and following a reset, the JTAG pins have their associated input pins configured • TDI in pull-up (PU) • TCK in pull-down (PD) • TMS in PU and associated output pin configured as: • TDO with no pull-down or pull-up K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 171 The LVD can be configured to generate a reset upon detection of a low voltage condition by setting the PMC's LVDSC1[LVDRE] bit to 1. The low voltage detection threshold is determined by the PMC's LVDSC1[LVDV] field. After an LVD reset has occurred, the K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 172 , as controlled by the C2[RANGE] field loc_low loc_high in the MCG module, the MCU resets. The RCM's SRS0[LOC] bit is set to indicate this reset source. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 173 The LOCKUP gives immediate indication of seriously errant kernel software. This is the result of the core being locked because of an unrecoverable exception following the activation of the processor’s built in system state protection hardware. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 174: Mcu Resets
The POR Only reset asserts on the POR reset source only. It resets the PMC and System Register File. The POR Only reset also causes all other reset types (except VBAT POR) to occur. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 175: Reset Pin
Chip Reset asserts on all reset sources and only negates after flash initialization has completed and the RESET_b pin has also negated. It resets the remaining modules (the modules not reset by other reset types). K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 176: Debug Resets
Use the CDBGRSTREQ bit within the SWJ-DP CTRL/STAT register to reset the debug modules. However, as explained below, using the CDBGRSTREQ bit does not reset all debug-related registers. CDBGRSTREQ resets the debug-related registers within the following modules: • SWJ-DP • AHB-AP K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 177: Boot
EzPort chip select (EZP_CS) Description Serial flash programming mode (EzPort) Single chip (default) 1. CDBGRSTREQ does not affect AHB resources so that debug resources on the private peripheral bus are available during System Reset. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 178: Fopt Boot Options
POR, VLLSx recoveries and reset sequencing and after reset exit. The recovery times are also extended if the FAST_INIT option is not selected. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 179: Boot Sequence
Once the RESET pin is detected high, the Core clock is enabled and the system is released from reset. EzPort mode is selected instead of the normal CPU execution if EZP_CS is low when the internal K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 180 NMI interrupt. The processor executes an Exception Entry and reads the NMI interrupt handler address from vector-table offset 8. The CPU begins execution at the NMI interrupt handler. Subsequent system resets follow this same reset flow. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 181: Power Management
If configured, a DMA request (using the asynchronous DMA wakeup) can also be used to exit Partial Stop for the duration of a DMA transfer before the device is transitioned back into PSTOP2. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 182: Dma Wakeup
Stop mode and then requesting bus slaves to enter Stop mode. In STOP and VLPS modes, MCG and PMC would then also enter their appropriate modes. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 183: Compute Operation
VLPS mode. The MCG, PMC, SRAM and Flash read port are not affected by Compute Operation, although the Flash register interface is disabled. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 184: Peripheral Doze
• The CPU is in Stop mode, including the entry sequence and for the duration of a DMA wakeup. • The CPU is in Compute Operation, including the entry sequence and for the duration of a DMA wakeup. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 185: Clock Gating
Stop mode entry is not supported directly from HSRUN and requires transition to Run prior to an attempt to enter a stop mode. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 186 Most peripherals are disabled (with clocks stopped), but LLWU, Sleep Deep Wakeup Reset Low Leakage LPTimer, RTC, CMP, DAC can be used. NVIC is disabled; LLWU is Stop3) used to wake up. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 187: Entering And Exiting Power Modes
Recovery from VLLSx is through the wake-up Reset event. The chip wake-ups from VLLSx by means of reset, an enabled pin or enabled module. See the table "LLWU inputs" in the LLWU configuration section for a list of the sources. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 188: Power Mode Transitions
VLPR and VLPW are limited in frequency. The LLS and VLLSx mode(s) are the lowest power stop modes based on amount of logic or memory that is required to be retained by the application. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 189: Power Modes Shutdown Sequencing
• System level wait and VLPW modes equate to: SLEEPING & SLEEPDEEP • All other low power modes equate to: SLEEPING & SLEEPDEEP When entering the non-wait modes, the chip performs the following sequence: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 190: Flash Program Restrictions
• static = Module register states and associated memories are retained. • powered = Memory is powered to retain contents. • low power = Memory is powered to retain contents in a lower power state K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 191 4 MHz max 4 MHz max OFF in CPO Bus clock 4 MHz max 4 MHz max OFF in CPO 50 MHz max in PSTOP2 from Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 192 FF in PSTOP2 in CPO Async operation FF with external static with external clock Async operation clock in CPO Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 193 It only requires the function controlling the pin (GPIO or peripheral) to be configured as an input to allow a transition to occur to the LLWU. 2. Since LPO clock source is disabled, filters will be bypassed during VLLS0 3. The SMC_STOPCTRL[PORPO] bit in the SMC module controls this option. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 194 VLLSx only supports low speed external pin to pin or external pin to DAC compares. Windowed, sampled & filtered modes of operation are not available while in stop, VLPS, LLSx, or VLLSx modes. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 195: Security
Further information regarding the flash security options and enabling/disabling flash security is available in the Flash Memory Module. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 196: Security Interactions With Other Modules
Erase in Progress bit in the MDM-AP Control register to trigger a mass erase (Erase All Blocks) command. A mass erase via the debugger is allowed even when some memory locations are protected. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 197 Chapter 8 Security When mass erase is disabled, mass erase via the debugger is blocked. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 198 Security Interactions with other Modules K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 199: Debug
• Serial Wire Debug (SWD) • ARM Real-Time Trace Interface(1-pin asynchronous mode only) The basic Cortex-M4 debug architecture is very flexible. The following diagram shows the topology of the core debug architecture and its components. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 200 The FPB unit contains two literal comparators for matching against literal loads from Code space, and remapping to a corresponding area in System space. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 201: References
• ARM Debug Interface v5.1 • ARM CoreSight Architecture Specification 9.2 The Debug Port The configuration of the cJTAG module, JTAG controller, and debug port is illustrated in the following figure: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 202: Jtag-To-Swd Change Sequence
3. Send more than 50 TCK cycles with TMS (SWDIO) =1 NOTE See the ARM documentation for the CoreSight DAP Lite for restrictions. 9.2.2 JTAG-to-cJTAG change sequence 1. Reset the debug port K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 203: Debug Port Pin Descriptions
TAPs (TDO) are muxed based on the IR code which is selected. This design is fully JTAG compliant and appears to the JTAG chain as a single TAP. At power on reset, ARM's IDCODE (IR=4'b1110) is selected. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 204: Ir Codes
JTAG, cJTAG, or SWD. The MDM-AP is accessible as Debug Access Port 1 with the available registers shown in the table below. Table 9-4. MDM-AP Register Summary Address Register Description Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 205: Mdm-Ap Control Register
Bus Matrix SELECT[7:4] = 0xF selects the bank with IDR A[3:2] = 2’b11 selects the IDR Register See Control and Status Register (IDR register reads 0x001C_0000) Descriptions Figure 9-3. MDM AP Addressing K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 206 This bit is used by the debugger to clear the sticky LLS and VLLSx mode entry status bits. This bit is asserted and cleared by the debugger. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 207: Mdm-Ap Status Register
ARM Core enters Deep Sleep. 0 Low Power Stop Mode is not enabled 1 Low Power Stop Mode is enabled Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 208: Debug Resets
• Debug reset (CDBGRSTREQ bit within the SWJ-DP CTRL/STAT register) in the TCLK domain that allows the debugger to reset the debug logic. • TRST asserted via the cJTAG escape command. • System POR reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 209: Ahb-Ap
The four sources in decreasing order of priority are: 1. Software trace -- Software can write directly to ITM stimulus registers. This emits packets. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 210: Core Trace Connectivity
• The DWT contains counters for: • Clock cycles (CYCCNT) • Folded instructions • Load store unit (LSU) operations • Sleep cycles • CPI (all instruction cycles except for the first cycle) • Interrupt overhead K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 211: Debug In Low Power Modes
HW, the MDM-AP Control register can be configured hold the system in reset on recovery so that the debugger can regain control and reconfigure debug logic prior to the system exiting reset and resuming operation. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 212: Debug & Security
When mass erase is disabled (FSEC[MEEN]= 10), the debugger does not have the capability of performing a mass erase operation via writes to MDM-AP Control Register. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 213: Signal Multiplexing And Signal Descriptions
Figure 10-1. Signal multiplexing integration Table 10-1. Reference links to related information Topic Related module Reference Full description Port control Port control System memory map System memory map Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 214: Port Control And Interrupt Module Features
Disabled Disabled at reset Drive strength PTB0/PTB1 only PTC3/PTC4 only PTD4/PTD5/PTD6/ enable control PTD7 only Drive strength Disabled Disabled Disabled Disabled Disabled enable at reset Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 215: Clock Gating
The Port Control Module is responsible for selecting which ALT functionality is available on each pin. NOTE The MK22FN512VFX12 (88QFN) does not support the FlexBus function. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 216 ADC0_ ADC0_ ADC0_ ADC0_ ADC0_ DP0/ DP0/ DP0/ ADC1_ ADC1_ ADC1_ ADC0_ ADC0_ ADC0_ DM0/ DM0/ DM0/ ADC1_ ADC1_ ADC1_ — — ADC1_ ADC1_ ADC1_ DP0/ DP0/ DP0/ ADC0_ ADC0_ ADC0_ K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 217 EXTAL32 EXTAL32 EXTAL32 VBAT VBAT VBAT — — — — PTE24 ADC0_ ADC0_ PTE24 I2C0_SCL EWM_ SE17 SE17 OUT_b — — — — PTE25 ADC0_ ADC0_ PTE25 I2C0_SDA EWM_IN SE18 SE18 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 218 SPI0_SIN UART0_ I2S0_ SE17 SE17 RTS_b MCLK L10 VDD K10 VSS L11 PTA18 EXTAL0 EXTAL0 PTA18 FTM0_ FTM_ FLT2 CLKIN0 K11 PTA19 XTAL0 XTAL0 PTA19 FTM1_ FTM_ LPTMR0_ FLT0 CLKIN1 ALT1 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 219 — — — — PTB22 DISABLE PTB22 FB_AD29 — — — — PTB23 DISABLE PTB23 SPI0_ FB_AD28 PCS5 PTC0 ADC0_ ADC0_ PTC0 SPI0_ PDB0_ USB_ FB_AD14 SE14 SE14 PCS4 EXTRG SOF_OUT K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 220 DISABLE PTC15 FB_AD24 — — — — — — — — — — — — PTC16 DISABLE PTC16 LPUART0 FB_CS5_ FB_TSIZ1/ FB_BE23_ BLS15_8_ — — PTC17 DISABLE PTC17 LPUART0 FB_CS4_ FB_TSIZ0/ K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 221 — — — PTD10 DISABLE PTD10 LPUART0 FB_A18 _RTS_b — — — — — PTD11 DISABLE PTD11 LPUART0 FB_A19 _CTS_b — — — — — PTD12 DISABLE PTD12 FTM3_ FB_A20 FLT0 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 222: K22 Pinouts
The following figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 223 USB0_DM PTC0 VOUT33 PTB19 VREGIN PTB18 ADC0_DP0/ADC1_DP3 PTB17 ADC0_DM0/ADC1_DM3 PTB16 ADC1_DP0/ADC0_DP3 PTB3 ADC1_DM0/ADC0_DM3 PTB2 VDDA PTB1 VREFH PTB0/LLWU_P5 VREFL RESET_b VSSA PTA19 Figure 10-2. K22F 64 LQFP pinout diagram (top view) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 224 RTC_ RESET_b PTA17 PTA15 PTA14 XTAL32 VDDA VREFH LLWU_P3 WAKEUP_B PTA13/ PTA19 PTA18 PTA16 PTA5 PTA12 VBAT EXTAL32 VSSA VREFL LLWU_P4 Figure 10-3. K22F 80 WLCSP pinout diagram (transparent top view) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 225 PTA4/ PTA13/ VREFL VREFH PTA19 ADC1_DP3 ADC0_DP3 LLWU_P3 LLWU_P4 VREF_OUT/ DAC0_OUT/ CMP1_IN5/ XTAL32 EXTAL32 VBAT PTA12 PTA18 CMP1_IN3/ CMP0_IN5/ ADC0_SE23 ADC1_SE18 Figure 10-4. K22F 64 MAPBGA pinout diagram (transparent top view) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 226 Figure 10-5. K22F 88 QFN pinout diagram (transparent top view) NOTE For more information about QFN package use, see Electrical Connection Recommendations for the Exposed Pad on QFN and DFN Packages K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 227 PTB16 ADC0_DP1 ADC0_DM1 ADC1_DP1/ADC0_DP2 ADC1_DM1/ADC0_DM2 PTB11 PTB10 ADC0_DP0/ADC1_DP3 ADC0_DM0/ADC1_DM3 PTB9 PTB3 ADC1_DP0/ADC0_DP3 PTB2 ADC1_DM0/ADC0_DM3 PTB1 VDDA PTB0/LLWU_P5 VREFH RESET_b VREFL PTA19 VSSA Figure 10-6. K22F 100 LQFP pinout diagram (top view) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 228: Module Signal Description Tables
10.4 Module Signal Description Tables The following sections correlate the chip-level signal name with the signal name used in the module's chapter. They also briefly describe the signal function and direction. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 229: Core Modules
EWM_in EWM input for safety status of external safety circuits. The polarity of EWM_in is programmable using the EWM_CTRL[ASSIN] bit. The default polarity is active-low. EWM_OUT EWM_out EWM reset out signal K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 230: Clock Modules
For example, in 16-bit mode, the lower address is driven on FB_AD15–FB_AD0, and in 8-bit mode, the lower address is driven on FB_AD23–FB_AD0. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 231 2h (FB_TSIZ1–FB_TSIZ0 = 10b), and the final 8 bits are transferred at offset 4h (FB_TSIZ1–FB_TSIZ0 = 01b). For aligned transfers larger than the port size, FB_TSIZ1– FB_TSIZ0 behave as follows: Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 232 16 bytes (FB_TSIZ1–FB_TSIZ0 = 11b), and the address is misaligned within the 16-byte boundary, the external memory or peripheral must be able to wrap around the address. 1. FB_AD[23:21] not available on 100-LQFP devices. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 233: Analog
CMP0_IN[5:0] IN[5:0] Analog voltage inputs CMP0_OUT CMPO Comparator output Table 10-14. CMP 1 Signal Descriptions Chip signal name Module signal Description name CMP1_IN[5:0] IN[5:0] Analog voltage inputs CMP1_OUT CMPO Comparator output K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 234: Timer Modules
Fault input (j), where j can be 3-0 FTM1_QD_PHA Quadrature decoder phase A input. Input pin associated with quadrature decoder phase A. FTM1_QD_PHB Quadrature decoder phase B input. Input pin associated with quadrature decoder phase B. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 235 Table 10-24. RTC Signal Descriptions Chip signal name Module signal Description name VBAT — Backup battery supply for RTC and VBAT register file RTC_CLKOUT RTC_CLKOUT 1 Hz square-wave output or OSCERCLK K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 236: Communication Interfaces
Chip signal name Module signal Description name SPI1_PCS0 PCS0/SS Peripheral Chip Select 0 (O) SPI1_PCS[3:1] PCS[1:3] Peripheral Chip Selects 1–3 SPI1_SIN Serial Data In SPI1_SOUT SOUT Serial Data Out SPI1_SCK Serial Clock (O) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 237 Request to send UART1_TX Transmit data UART1_RX Receive data Table 10-34. UART 2 Signal Descriptions Chip signal name Module signal Description name UART2_CTS Clear to send Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 238: Human-Machine Interfaces (Hmi)
PORTC31–PORTC0 General-purpose input/output PTD[31:0] PORTD31–PORTD0 General-purpose input/output PTE[31:0] PORTE31–PORTE0 General-purpose input/output 1. The available GPIO pins depends on the specific package. See the signal multiplexing section for which exact GPIO signals are available. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 239: Port Control And Interrupts (Port)
• Support for interrupt or DMA request configured per pin • Asynchronous wake-up in low-power modes • Pin interrupt is functional in all digital pin muxing modes • Digital input filter on selected pins K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 240: Modes Of Operation
In Stop mode, the PORT can be configured to exit the Low-Power mode via an asynchronous wake-up signal if an enabled interrupt is detected. In Stop mode, the digital input filters are bypassed unless they are configured to run from the LPO clock source. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 241: External Signal Description
11.5 Memory map and register definition Any read or write access to the PORT memory space that is outside the valid memory map results in a bus error. All register accesses complete with zero wait states. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 242 (always 0000_0000h 11.5.2/251 reads 0) 4004_9084 Global Pin Control High Register (PORTA_GPCHR) (always 0000_0000h 11.5.3/251 reads 0) 4004_90A0 Interrupt Status Flag Register (PORTA_ISFR) 0000_0000h 11.5.4/252 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 243 Pin Control Register n (PORTB_PCR30) See section 11.5.1/248 4004_A07C Pin Control Register n (PORTB_PCR31) See section 11.5.1/248 4004_A080 Global Pin Control Low Register (PORTB_GPCLR) (always 0000_0000h 11.5.2/251 reads 0) Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 244 Pin Control Register n (PORTC_PCR28) See section 11.5.1/248 4004_B074 Pin Control Register n (PORTC_PCR29) See section 11.5.1/248 4004_B078 Pin Control Register n (PORTC_PCR30) See section 11.5.1/248 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 245 4004_C064 Pin Control Register n (PORTD_PCR25) See section 11.5.1/248 4004_C068 Pin Control Register n (PORTD_PCR26) See section 11.5.1/248 4004_C06C Pin Control Register n (PORTD_PCR27) See section 11.5.1/248 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 246 4004_D058 Pin Control Register n (PORTE_PCR22) See section 11.5.1/248 4004_D05C Pin Control Register n (PORTE_PCR23) See section 11.5.1/248 4004_D060 Pin Control Register n (PORTE_PCR24) See section 11.5.1/248 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 247 4004_D0A0 Interrupt Status Flag Register (PORTE_ISFR) 0000_0000h 11.5.4/252 4004_D0C0 Digital Filter Enable Register (PORTE_DFER) 0000_0000h 11.5.5/252 4004_D0C4 Digital Filter Clock Register (PORTE_DFCR) 0000_0000h 11.5.6/253 4004_D0C8 Digital Filter Width Register (PORTE_DFWR) 0000_0000h 11.5.7/253 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 248: Pin Control Register N (Portx_Pcrn)
This read-only field is reserved and always has the value 0. Interrupt Status Flag The pin interrupt configuration is valid in all digital pin muxing modes. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 249 Alternative 1 (GPIO). 0010 Alternative 2 (chip-specific). 0011 Alternative 3 (chip-specific). 0100 Alternative 4 (chip-specific). 0101 Alternative 5 (chip-specific). 0110 Alternative 6 (chip-specific). 0111 Alternative 7 (chip-specific). Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 250 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 251: Global Pin Control Low Register (Portx_Gpclr)
Corresponding Pin Control Register is updated with the value in GPWD. GPWD Global Pin Write Data Write value that is written to all Pin Control Registers bits [15:0] that are selected by GPWE. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 252: Interrupt Status Flag Register (Portx_Isfr)
Chapter of Signal Multiplexing and Signal Descriptions for the pins that support digital filter. The digital filter configuration is valid in all digital pin muxing modes. Address: Base address + C0h offset Reset PORTx_DFER field descriptions Field Description Digital Filter Enable K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 253: Digital Filter Clock Register (Portx_Dfcr)
11.5.7 Digital Filter Width Register (PORTx_DFWR) This register is read only for ports that do not support a digital filter. The digital filter configuration is valid in all digital pin muxing modes. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 254: Functional Description
Pin Control register. For example, if an I C function is enabled on a pin, that does not override the pullup or open drain configuration for that pin. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 255: Global Pin Control
The global pin control registers are write-only registers, that always read as 0. 11.6.3 External interrupts The external interrupt capability of the PORT module is available in all digital pin muxing modes provided the PORT module is enabled. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 256: Digital Filter
If the digital filters for a port are configured to use the bus clock, then the digital filters are bypassed for the duration of Stop mode. While the digital filters K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 257 The maximum latency through a digital filter equals three filter clock cycles plus the filter width configuration register. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 258 Functional description K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 259: System Integration Module (Sim)
• USB clock selection and divide values • Flash and system RAM size configuration • USB regulator configuration • FlexTimer external clock, hardware trigger, and fault source selection • UART0 and UART1 receive/transmit source selection/configuration K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 260: Memory Map And Register Definition
See section 12.2.17/290 4004_8058 Unique Identification Register Mid-High (SIM_UIDMH) See section 12.2.18/290 4004_805C Unique Identification Register Mid Low (SIM_UIDML) See section 12.2.19/291 4004_8060 Unique Identification Register Low (SIM_UIDL) See section 12.2.20/291 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 261: System Options Register 1 (Sim_Sopt1)
USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS modes. USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 262 1011 256 KB 1101 512 KB 1111 1024 KB 11–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Reserved This field is reserved. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 263: Sopt1 Configuration Register (Sim_Sopt1Cfg)
Writing one to the URWE bit allows the SOPT1 USBREGEN bit to be written. This register bit clears after a write to USBREGEN. SOPT1 USBREGEN cannot be written. SOPT1 USBREGEN can be written. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 264: System Options Register 2 (Sim_Sopt2)
This read-only field is reserved and always has the value 0. 27–26 LPUART clock source select LPUARTSRC Selects the clock source for the LPUART transmit and receive clock. Clock disabled Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 265 Off-chip instruction accesses are disallowed. Data accesses are allowed. Off-chip instruction accesses and data accesses are allowed. 7–5 CLKOUT select CLKOUTSEL Selects the clock to output on the CLKOUT pin. FlexBus CLKOUT Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 266: System Options Register 4 (Sim_Sopt4)
FlexTimer 3 Hardware Trigger 1 Source Select FTM3TRG1SRC Selects the source of FTM3 hardware trigger 1. Reserved FTM2 channel match drives FTM3 hardware trigger 1 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 267 NOTE: The selected pin must also be configured for the FTM external clock function through the appropriate pin control register in the port control module. FTM_CLK0 pin FTM_CLK1 pin Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 268 FTM2_FLT0 pin CMP0 out 7–5 This field is reserved. Reserved This read-only field is reserved and always has the value 0. FTM1 Fault 0 Select FTM1FLT0 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 269: System Options Register 5 (Sim_Sopt5)
Description 31–20 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 19–18 LPUART0 receive data source select LPUART0RXSRC Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 270 UART 0 transmit data source select Selects the source for the UART 0 transmit data. UART0_TX pin UART0_TX pin modulated with FTM1 channel 0 output UART0_TX pin modulated with FTM2 channel 0 output Reserved K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 271: System Options Register 7 (Sim_Sopt7)
PDB external trigger pin input (PDB0_EXTRG) 0001 High speed comparator 0 output 0010 High speed comparator 1 output 0011 Reserved 0100 PIT trigger 0 0101 PIT trigger 1 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 272 PIT trigger 2 0111 PIT trigger 3 1000 FTM0 trigger 1001 FTM1 trigger 1010 FTM2 trigger 1011 FTM3 trigger 1100 RTC alarm 1101 RTC seconds 1110 Low-power timer (LPTMR) trigger 1111 Reserved K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 273: System Options Register 8 (Sim_Sopt8)
FTM3_CH2 pin is output of FTM3 channel 2 output FTM3_CH2 pin is output of FTM3 channel 2 output modulated by FTM2 channel 1 output. FTM3 channel 1 output source FTM3OCH1SRC Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 274 Write 1 to assert the TRIG0 input to FTM3, software must clear this bit to allow other trigger sources to assert. FTM2 Hardware Trigger 0 Software Synchronization FTM2SYNCBIT Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 275: System Device Identification Register (Sim_Sdid)
K7x Family 1000 K8x Family 27–24 Kinetis Sub-Family ID SUBFAMID Specifies the Kinetis sub-family of the device. 0000 Kx0 Subfamily 0001 Kx1 Subfamily (tamper detect) Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 276 Specifies the pincount of the device. 0000 Reserved 0001 Reserved 0010 32-pin 0011 Reserved 0100 48-pin 0101 64-pin 0110 80-pin 0111 81-pin or 121-pin 1000 100-pin 1001 121-pin 1010 144-pin Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 277: System Clock Gating Control Register 4 (Sim_Scgc4)
This bit controls the clock gate to the comparator module. Clock disabled Clock enabled USB Clock Gate Control USBOTG This bit controls the clock gate to the USB module. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 278 This read-only field is reserved and always has the value 0. EWM Clock Gate Control This bit controls the clock gate to the EWM module. Clock disabled Clock enabled Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 279: System Clock Gating Control Register 5 (Sim_Scgc5)
This bit controls the clock gate to the Port D module. Clock disabled Clock enabled Port C Clock Gate Control PORTC This bit controls the clock gate to the Port C module. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 280 This read-only field is reserved and always has the value 1. Low Power Timer Access Control LPTMR This bit controls software access to the Low Power Timer module. Access disabled Access enabled K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 281: System Clock Gating Control Register 6 (Sim_Scgc6)
This bit controls the clock gate to the ADC0 module. Clock disabled Clock enabled FTM2 Clock Gate Control FTM2 This bit controls the clock gate to the FTM2 module. Clock disabled Clock enabled Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 282 This read-only field is reserved and always has the value 0. SPI1 Clock Gate Control SPI1 This bit controls the clock gate to the SPI1 module. Clock disabled Clock enabled Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 283 This bit controls the clock gate to the flash memory. Flash reads are still supported while the flash memory is clock gated, but entry into low power modes and HSRUN mode is blocked. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 284: System Clock Gating Control Register 7 (Sim_Scgc7)
This bit controls the clock gate to the DMA module. Clock disabled Clock enabled FlexBus Clock Gate Control FLEXBUS This bit controls the clock gate to the FlexBus module. Clock disabled Clock enabled K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 285: System Clock Divider Register 1 (Sim_Clkdiv1)
This field sets the divide value for the bus clock from MCGOUTCLK. At the end of reset, it is loaded with either 0000 or 0111 depending on FTF_FOPT[LPBOOT]. The bus clock frequency must be an integer divide of the core/system clock frequency. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 286 0001 or 1111 depending on FTF_FOPT[LPBOOT]. The flash clock frequency must be an integer divide of the system clock frequency. 0000 Divide-by-1. 0001 Divide-by-2. 0010 Divide-by-3. 0011 Divide-by-4. 0100 Divide-by-5. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 287: System Clock Divider Register 2 (Sim_Clkdiv2)
This field sets the fraction multiply value for the fractional clock divider when the MCGFLLCLK, or MCGPLLCLK, or IRC48M clock is the USB clock source (SOPT2[USBSRC] = 1). Divider output clock = Divider input clock × [ (USBFRAC+1) / (USBDIV+1) ] K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 288: Flash Configuration Register 1 (Sim_Fcfg1)
256 KB of program flash memory 1011 512 KB of program flash memory 1101 1024 KB of program flash memory 1111 512 KB of program flash memory Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 289: Flash Configuration Register 2 (Sim_Fcfg2)
This bit should not be changed during VLP modes. Relocate the interrupt vectors out of Flash memory before disabling the Flash. Flash is enabled Flash is disabled 12.2.16 Flash Configuration Register 2 (SIM_FCFG2) Address: 4004_7000h base + 1050h offset = 4004_8050h MAXADDR0 MAXADDR1 Reset Reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 290: Unique Identification Register High (Sim_Uidh)
0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* Reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 291: Unique Identification Register Mid Low (Sim_Uidml)
0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* Reset SIM_UIDL field descriptions Field Description Unique Identification Unique identification for the device. 12.3 Functional description For more information about the functions of SIM, see the Introduction section. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 292 Functional description K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 293: Kinetis Flashloader
After a device reset, the flashloader_loader program starts its execution first. The flashloader_loader program copies the contents of flashloader image from the flash to the on-chip RAM; the device then switches execution to the flashloader program to execute from RAM. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 294 Not supported ReadMemory Read data from memory Not supported GetProperty Get the current value of a property Supported Reset Reset the chip Supported SetProperty Attempt to modify a writable property Supported K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 295: Functional Description
3. The flashloader waits for communication to begin on a peripheral. • There is no timeout for the active peripheral detection process. • If communication is detected, then all inactive peripherals are shut down, and the command phase is entered. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 296: Clock Configuration
The core runs on the default reset clock (20.9 MHz). After exiting the flashloader, the core sets the clock configuration back to the reset state (and enables the internal 48 MHz reference clock for the USB module). K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 297: Flashloader Protocol
The protocol for a command with no data phase contains: • Command packet (from host) • Generic response command packet (to host) Target Host Command Process command Response Figure 13-2. Command with No Data Phase K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 298 • Generic response command packet (to host) Target Host Command Process command Initial Response Data packet Process data Final data packet Process data Final Response Figure 13-3. Command with incoming data phase K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 299 The protocol for a command with an outgoing data phase contains: • Command packet (from host) • ReadMemory Response command packet (to host) (kCommandFlag_HasDataPhase set) • Outgoing data packets (to host) • Generic response command packet (to host) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 300 • If the ReadMemory Response command packet prior to the start of the data phase does not contain the kCommandFlag_HasDataPhase flag, then the data phase is aborted. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 301: Flashloader Packet Types
A Ping packet must be sent before any other communications. In response to a Ping packet, the target sends a Ping Response packet. Table 13-3. Ping Packet Format Byte # Value Name 0x5A start byte 0xA6 ping K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 302 Table 13-4. Ping Response Packet Format Byte # Value Parameter 0x5A start byte 0xA7 Ping response code Protocol bugfix Protocol minor Protocol major Protocol name = 'P' (0x50) Options low Options high CRC16 low CRC16 high K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 303 Data phase is being aborted. 0xA4 kFramingPacketType_Command The framing packet contains a command packet payload. 0xA5 kFramingPacketType_Data The framing packet contains a data packet payload. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 304 Table 13-10. Commands that are supported Command Name 0x01 FlashEraseAll 0x02 FlashEraseRegion 0x03 ReadMemory 0x04 WriteMemory Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 305 ParameterCount: The number of parameters included in the command packet. Parameters: The parameters are word-length (32 bits). With the default maximum packet size of 32 bytes, a command packet can contain up to 7 parameters. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 306 Flashloader Status Error Codes, lists the status codes returned to the host by the Kinetis Flashloader. 4 - 7 Command tag The Command tag parameter identifies the response to the command sent by the host. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 307 0. The parameter count is set to 2 plus the number of words requested to be read in the FlashReadOnceCommand. Table 13-15. FlashReadOnceResponse Parameters Byte # Value Parameter 0 – 3 Status Code Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 308: Flashloader Command Api
The Call command will execute a function that is written in memory at the address sent in the command. The address needs to be a valid memory location residing in accessible flash (internal or external) or in RAM. The command supports the passing of one 32-bit K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 309 Properties are the defined units of data that can be accessed with the GetProperty or SetProperty commands. Properties may be read-only or read-write. All read-write properties are 32-bit integers, so they can easily be carried in a command parameter. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 310 0xA4, kFramingPacketType_Command length 0x08 0x00 crc16 0x73 0xD4 Command packet commandTag 0x07 – GetProperty flags 0x00 reserved 0x00 parameterCount 0x01 propertyTag 0x00000001 - CurrentVersion The GetProperty command has no data phase. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 311 The property tag and the new value to set are the 2 parameters required for the SetProperty command. Table 13-21. Parameters for SetProperty Command Byte # Command 0 - 3 Property tag 4 - 7 Property value K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 312 The SetProperty command has no data phase. Response: The target (Kinetis Flashloader) will return a GenericResponse packet with one of following status codes: Table 13-23. SetProperty Response Status Codes Status Code kStatus_Success kStatus_ReadOnly kStatus_UnknownProperty kStatus_InvalidArgument K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 313 0xC4 0x2E Command packet commandTag 0x01 - FlashEraseAll flags 0x00 reserved 0x00 parameterCount 0x00 MemoryID • If MemoryID = 0x00h, then internal flash. • If MemoryID = 0x01h, then QSPI0 memory. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 314 Process command Generic Response: 0x5a a4 0c 00 ba 55 a0 00 00 02 00 00 00 00 02 00 00 00 ACK: 0x5a a1 Figure 13-10. Protocol Sequence for FlashEraseRegion Command K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 315 WriteMemory command. The difference between FillMemory and WriteMemory is that a data pattern is included in FillMemory command parameter, and there is no data phase for the FillMemory command, while WriteMemory does have a data phase. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 316 Process command Generic Response: 0x5a a4 0c 00 97 04 a0 00 00 02 00 00 00 00 05 00 00 00 ACK: 0x5a a1 Figure 13-11. Protocol Sequence for FillMemory Command K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 317 Table 13-30. Parameters for FlashProgramOnce Command Byte # Command 0 - 3 Index of program once field 4 - 7 Byte count (must be evenly divisible by 4) 8 - 11 Data 12 - 16 Data K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 318 13.3.6.8 FlashReadOnce command The FlashReadOnce command returns the contents of the program once field by given index and byte count. The FlashReadOnce command uses 2 parameters: index and byteCount. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 319 0x00 parameterCount 0x02 index 0x0000_0000 byteCount 0x0000_0004 Table 13-34. FlashReadOnce Response Format (Example) FlashReadOnce Parameter Value Response Framing packet start byte 0x5A packetType 0xA4 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 320 0 - 3 start address Start address of specific non-volatile memory to be read 4 - 7 byteCount Byte count to be read 8 - 11 option 0: IFR 1: Flash firmware ID K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 321 Value Framing packet start byte 0x5A packetType 0xA4 length 0x10 0x00 0xB3 0xCC Command packet commandTag 0x10 – FlashReadResource flags 0x00 reserved 0x00 parameterCount 0x03 startAddress 0x0000_0000 byteCount 0x0000_0008 option 0x0000_0001 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 322 The start address and number of bytes are the 2 parameters required for WriteMemory command. Table 13-38. Parameters for WriteMemory Command Byte # Command 0 - 3 Start address 4 - 7 Byte count K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 323 Framing packet start byte 0x5A packetType 0xA4, kFramingPacketType_Command length 0x0C 0x00 crc16 0x06 0x5A Command packet commandTag 0x04 - writeMemory flags 0x00 reserved 0x00 parameterCount 0x02 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 324 Table 13-40. Parameters for read memory command Byte Parameter Description Start address Start address of memory to read from Byte count Number of bytes to read and return to caller K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 325 Parameter Value Framing packet Start byte 0x5A0xA4, packetType kFramingPacketType_Command length 0x0C 0x00 crc16 0x1D 0x23 Command packet commandTag 0x03 - readMemory flags 0x00 reserved 0x00 parameterCount 0x02 startAddress 0x20000400 byteCount 0x00000064 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 326 GenericResponse packet with a status code either set to kStatus_Success or an appropriate error status code. 13.3.6.13 Reset command The Reset command will result in flashloader resetting the chip. The Reset command requires no parameters. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 327: Peripherals Supported
Response: The target (Kinetis Flashloader) will return a GenericResponse packet with status code set to kStatus_Success, before resetting the chip. 13.4 Peripherals Supported This section describes the peripherals supported by the Kinetis Flashloader. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 328: I2C Peripheral
Read leftover bytes Read 1 byte of ping response packet from target Read 1 byte 0x5A 0x7A Report Error received? received? from target Figure 13-18. Host reads ping response from target via I2C K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 329: Spi Peripheral
Figure 13-20. Host reads response from target via I2C 13.4.2 SPI Peripheral The Kinetis Flashloader supports loading data into flash via the SPI peripheral, where the SPI peripheral serves as a SPI slave. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 330 1 byte of ping response from target Send 0x00 to 0x5A 0xA7 Report Error shift out 1 byte received? received? from target Figure 13-21. Host reads ping packet from target via SPI K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 331: Uart Peripheral
(2 bytes) Figure 13-23. Host reads response from target via SPI 13.4.3 UART Peripheral The Kinetis Flashloader integrates an autobaud detection algorithm for the UART peripheral, thereby providing flexible baud rate choices. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 332 • How the host detects an ACK from the target • How the host detects a ping response from the target • How the host detects a command response from the target K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 333 Wait for 1 byte of ping response from target packet 0x5A 0xA7 Wait for 1 byte Report Error received? received? from target Figure 13-25. Host reads a ping response from target via UART K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 334: Usb Peripheral
48-MHz IRC. The flashloader also enables the USB clock recovery feature (by setting USBx_CLK_RECOVER_CTRL[CLOCK_RECOVER_EN] to 1 and USB_CLK_RECOVER_IRC_EN[IRC_EN] to 1). 13.4.4.2 Device descriptor The Kinetis flashloader configures the default USB VID/PID/Strings as below: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 335 • VID = 0x15A2 • PID = 0x0073 Default Strings: • Manufacturer [1] = "Freescale Semiconductor Inc." (Note that Freescale Semiconductor is now NXP Semiconductors.) • Product [2] = "Kinetis Bootloader" 13.4.4.3 Endpoints The HID peripheral uses 3 endpoints: • Control (0) •...
-
Page 336: Get/Setproperty Command Properties
Current flashloader version. AvailablePeripherals The set of peripherals supported on this chip. FlashStartAddress Start address of program flash. FlashSizeInBytes Size in bytes of program flash. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 337 0 - FAC not supported 1 - FAC supported FlashAcessSegmentSize The size in bytes of 1 segment of flash FlashAcessSegmentCount FAC segment count (The count of flash access segments within the flash model.) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 338: Property Definitions
1. 1 is subtracted from the command tag because the lowest command tag value is 0x01. To get the bit mask for a given command, use this expression: mask = 1 << (tag - 1) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 339: Kinetis Flashloader Status Error Codes
The key provided does not match the programmed flash key. kStatus_FlashRegionExecuteOnly The area of flash is protected as execute only. kStatus_I2C_SlaveTxUnderrun I2C Slave TX Underrun error. kStatus_I2C_SlaveRxOverrun I2C Slave RX Overrun error. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 340 10403 CRC check is invalid, because the BCA is invalid or the CRC parameters are unset (all 0xFF bytes). kStatus_AppCrcCheckOutOfRange 10404 CRC check is valid but addresses are out of range. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 341: Reset Control Module (Rcm)
14.2.1/342 4007_F001 System Reset Status Register 1 (RCM_SRS1) 14.2.2/343 4007_F004 Reset Pin Filter Control register (RCM_RPFC) 14.2.3/345 4007_F005 Reset Pin Filter Width register (RCM_RPFW) 14.2.4/346 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 342: System Reset Status Register 0 (Rcm_Srs0)
Indicates a reset has been caused by an active-low level on the external RESET pin. Reset not caused by external reset pin Reset caused by external reset pin Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 343: System Reset Status Register 1 (Rcm_Srs1)
The reset state of these bits depends on what caused the MCU to reset. NOTE The reset value of this register depends on the reset source: • POR (including LVD) — 0x00 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 344 Indicates a reset has been caused by the ARM core indication of a LOCKUP event. Reset not caused by core LOCKUP event Reset caused by core LOCKUP event Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 345: Reset Pin Filter Control Register (Rcm_Rpfc)
Selects how the reset pin filter is enabled in run and wait modes. All filtering disabled Bus clock filter enabled for normal operation LPO clock filter enabled for normal operation Reserved K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 346: Reset Pin Filter Width Register (Rcm_Rpfw)
Bus clock filter count is 22 10110 Bus clock filter count is 23 10111 Bus clock filter count is 24 11000 Bus clock filter count is 25 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 347: Mode Register (Rcm_Mr)
Reflects the state of the EZP_MS pin during the last Chip Reset Pin deasserted (logic 1) Pin asserted (logic 0) This field is reserved. Reserved This read-only field is reserved and always has the value 0. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 348: Sticky System Reset Status Register 0 (Rcm_Ssrs0)
Reset not caused by a loss of lock in the PLL Reset caused by a loss of lock in the PLL Sticky Loss-of-Clock Reset SLOC Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 349: Sticky System Reset Status Register 1 (Rcm_Ssrs1)
This read-only field is reserved and always has the value 0. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Sticky Stop Mode Acknowledge Error Reset SSACKERR Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 350 Sticky JTAG Generated Reset SJTAG Indicates a reset has been caused by JTAG selection of certain IR codes: EZPORT, EXTEST, HIGHZ, and CLAMP. Reset not caused by JTAG Reset caused by JTAG K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 351: System Mode Controller (Smc)
The WFI or WFE instruction is used to invoke Sleep and Deep Sleep modes. Run, Wait, and Stop are the common terms used for the primary operating modes of Kinetis microcontrollers. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 352 The core, system, bus, and flash clock maximum frequencies are restricted in this mode. See the Power Management chapter for details about the maximum allowable frequencies. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 353: Memory Map And Register Descriptions
For more information about the types of reset on this chip, refer to the Reset section details. NOTE The SMC registers can be written only in supervisor mode. Write accesses in user mode are blocked and will result in a bus error. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 354: Power Mode Protection Register (Smc_Pmprot)
Chip Reset not VLLS. See the Reset section details for more information. Address: 4007_E000h base + 0h offset = 4007_E000h Read AHSRUN AVLP ALLS AVLLS Write Reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 355: Power Mode Control Register (Smc_Pmctrl)
(PMPROT) register. NOTE This register is reset on Chip POR not VLLS and by reset types that trigger Chip POR not VLLS. It is unaffected by reset types K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 356 NOTE: When set to STOP, the PSTOPO bits in the STOPCTRL register can be used to select a Partial Stop mode if desired. Normal Stop (STOP) Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 357: Stop Control Register (Smc_Stopctrl)
PSTOP2 - Partial Stop with system clock disabled and bus clock enabled Reserved POR Power Option PORPO This bit controls whether the POR detect circuit is enabled in VLLS0 mode. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 358: Power Mode Status Register (Smc_Pmstat)
Address: 4007_E000h base + 3h offset = 4007_E003h Read PMSTAT Write Reset SMC_PMSTAT field descriptions Field Description PMSTAT Power Mode Status NOTE: When debug is enabled, the PMSTAT will not update to STOP or VLPS K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 359: Functional Description
15.4 Functional description 15.4.1 Power mode transitions The following figure shows the power mode state transitions available on the chip. Any reset always brings the MCU back to the normal RUN state. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 360 Sleep-now or sleep-on-exit modes entered with SLEEPDEEP clear, controlled in System Control Register in ARM core. See note. WAIT Interrupt or Reset STOP PMCTRL[RUNM]=00, PMCTRL[STOPM]=000 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 361 Wakeup from enabled LLWU input source or RESET pin VLPR VLLSx PMPROT[AVLLS]=1, PMCTRL[STOPM]=100, STOPCTRL[LLSM]=x (VLLSx), Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 362: Power Mode Entry/Exit Sequencing
Entry into a low-power stop mode (Stop, VLPS, LLS, VLLSx) is initiated by a CPU executing the WFI instruction. After the instruction is executed, the following sequence occurs: 1. The CPU clock is gated off immediately. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 363 For wait modes (WAIT and VLPW), the CPU clock is gated off while all other clocking continues, as in RUN and VLPR mode operation. Some modules that support stop-in- wait functionality have their clocks disabled in these configurations. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 364: Run Modes
• All clock monitors in the MCG must be disabled. • The maximum frequencies of the system, bus, flash, and core are restricted. See the Power Management details about which frequencies are supported. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 365 HSRUN mode. To reenter normal RUN mode, clear PMCTRL[RUNM]. Any reset also clears PMCTRL[RUNM] and causes the system to exit to normal RUN mode after the MCU exits its reset flow. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 366: Wait Modes
A system reset causes an exit from VLPW mode, returning the device to normal RUN mode. 15.4.5 Stop modes This device contains a variety of stop modes to meet your application needs. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 367 A system reset will cause an exit from STOP mode, returning the device to normal RUN mode via an MCU reset. 15.4.5.2 Very-Low-Power Stop (VLPS) mode The two ways in which VLPS mode can be entered are listed here. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 368 NOTE The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit Stop mode on an LLS recovery. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 369 An asserted RESET pin will cause an exit from any VLLS mode, returning the device to normal RUN mode. When exiting VLLS via the RESET pin, RCM_SRS[PIN] and RCM_SRS[WAKEUP] are set. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 370: Debug In Low Power Modes
CPU operation to begin. The VLLDBGACK bit is cleared by the debugger (or can be left set as is) or clears automatically due to the reset generated as part of the next VLLS recovery. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 371: Power Management Controller (Pmc)
The system is comprised of a power-on reset (POR) circuit and a LVD circuit with a user-selectable trip voltage: high (V ) or low (V ). The trip voltage is selected by LVDH LVDL LVDSC1[LVDV]. The LVD is disabled upon entering VLPx, LLS, and VLLSx modes. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 372: Lvd Reset Operation
LVD voltage. The LVW also has an interrupt, which is enabled by setting LVDSC2[LVWIE]. If enabled, an LVW interrupt request occurs when LVDSC2[LVWF] is set. LVDSC2[LVWF] is cleared by writing 1 to LVDSC2[LVWACK]. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 373: I/O Retention
PMC memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) Low Voltage Detect Status And Control 1 register 4007_D000 16.5.1/374 (PMC_LVDSC1) Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 374: Low Voltage Detect Status And Control 1 Register (Pmc_Lvdsc1)
PMC_LVDSC1 field descriptions Field Description Low-Voltage Detect Flag LVDF This read-only status field indicates a low-voltage detect event. Low-voltage event not detected Low-voltage event detected Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 375: Low Voltage Detect Status And Control 2 Register (Pmc_Lvdsc2)
LVWV is reset solely on a POR Only event. The other fields of the register are reset on Chip Reset Not VLLS. For more information about these reset types, refer to the Reset section details. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 376: Regulator Status And Control Register (Pmc_Regsc)
CMP and ADC. The internal regulator provides a status bit (REGONS) indicating the regulator is in run regulation. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 377 Regulator is in stop regulation or in transition to/from it Regulator is in run regulation This field is reserved. Reserved NOTE: This reserved bit must remain cleared (set to 0). Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 378 Memory map and register descriptions PMC_REGSC field descriptions (continued) Field Description Bandgap Buffer Enable BGBE Enables the bandgap buffer. Bandgap buffer not enabled Bandgap buffer enabled K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 379: Low-Leakage Wakeup Unit (Llwu)
LLS or VLLS. See the chip configuration information for wakeup input sources for this device. • External pin wake-up inputs, each of which is programmable as falling-edge, rising- edge, or any change K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 380: Modes Of Operation
When the wake-up pin filters are enabled, filter operation begins immediately. If a low leakage mode is entered within five LPO clock cycles of an active edge, the edge event will be detected by the LLWU. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 381: Block Diagram
Edge interrupt flow Pin filter 2 Synchronizer detect reset flow WUPE15 FILT2[FILTSEL] LLWU_P15 Edge wakeup occurred detect External pin sources LLWU_P0 wakeup occurred Edge detect WUPE0 Figure 17-1. LLWU block diagram K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 382: Llwu Signal Descriptions
LLWU registers are unaffected by reset types that do not trigger Chip Reset not VLLS. For more information about the types of reset on this chip, refer to the Introduction details. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 383: Llwu Pin Enable 1 Register (Llwu_Pe1)
External input pin enabled with any change detection 5–4 Wakeup Pin Enable For LLWU_P2 WUPE2 Enables and configures the edge detection for the wakeup pin. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 384: Llwu Pin Enable 2 Register (Llwu_Pe2)
Enables and configures the edge detection for the wakeup pin. External input pin disabled as wakeup input External input pin enabled with rising edge detection Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 385: Llwu Pin Enable 3 Register (Llwu_Pe3)
Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 2h offset = 4007_C002h Read WUPE11 WUPE10 WUPE9 WUPE8 Write Reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 386: Llwu Pin Enable 4 Register (Llwu_Pe4)
This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 387: Llwu Module Enable Register (Llwu_Me)
LLWU_ME contains the bits to enable the internal module flag as a wakeup input source for inputs MWUF7–MWUF0. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 388 WUME1 Enables an internal module as a wakeup source input. Internal module flag not used as wakeup source Internal module flag used as wakeup source Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 389: Llwu Flag 1 Register (Llwu_F1)
Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF6. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 390 Indicates that an enabled external wake-up pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF0. LLWU_P0 input was not a wakeup source LLWU_P0 input was a wakeup source K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 391: Llwu Flag 2 Register (Llwu_F2)
Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF13. LLWU_P13 input was not a wakeup source LLWU_P13 input was a wakeup source Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 392: Llwu Flag 3 Register (Llwu_F3)
CMP module, the flag from the associated peripheral is accessible as the MWUFx bit. The flag will need to be cleared in the peripheral instead of writing a 1 to the MWUFx bit. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 393 Module 3 input was not a wakeup source Module 3 input was a wakeup source Wakeup flag For module 2 MWUF2 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 394: Llwu Pin Filter 1 Register (Llwu_Filt1)
Indicates that the filtered external wakeup pin, selected by FILTSEL, was a source of exiting a low-leakage power mode. To clear the flag write a one to FILTF. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 395: Llwu Pin Filter 2 Register (Llwu_Filt2)
Indicates that the filtered external wakeup pin, selected by FILTSEL, was a source of exiting a low-leakage power mode. To clear the flag write a one to FILTF. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 396: Functional Description
5 cycles of delay before the detect circuit alerts the system to the wakeup or reset event when the filter function is enabled. Two wakeup detect filters are available for selected external pins. Glitch filtering is not provided on the internal modules. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 397: Lls Mode
LLWU flag from being falsely set when PMC_REGSC[ACKISO] is cleared. The signal selected as a wake-up source pin must be a digital pin, as selected in the pin mux control. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 398 Functional description K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 399: Miscellaneous Control Module (Mcm)
Crossbar Switch (AXBS) Slave Configuration E008_0008 001Fh 18.2.1/400 (MCM_PLASC) Crossbar Switch (AXBS) Master Configuration E008_000A 0017h 18.2.2/400 (MCM_PLAMC) E008_000C Crossbar Switch (AXBS) Control Register (MCM_PLACR) 0000_0000h 18.2.3/401 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 400: Crossbar Switch (Axbs) Slave Configuration (Mcm_Plasc)
18.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC) PLAMC is a 16-bit read-only register identifying the presence/absence of bus master connections to the device's crossbar switch. Address: E008_0000h base + Ah offset = E008_000Ah Read Write Reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 401: Crossbar Switch (Axbs) Control Register (Mcm_Placr)
The MCM_ISCR register includes the enable and status bits associated with the core’s floating-point exceptions. The individual event indicators are first qualified with their exception enables and then logically summed to form an interrupt request sent to the core’s NVIC. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 402 This read-only field is reserved and always has the value 0. FPU inexact interrupt enable FIXCE Disable interrupt Enable interrupt FPU underflow interrupt enable FUFCE Disable interrupt Enable interrupt Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 403 This read-only bit is a copy of the core’s FPSCR[DZC] bit and signals a divide by zero has been detected in the processor’s FPU. Once set, this bit remains set until software clears the FPSCR[DZC] bit. No interrupt Interrupt occurred Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 404: Compute Operation Control Register (Mcm_Cpo)
This read-only field is reserved and always has the value 0. 18.2.5 Compute Operation Control Register (MCM_CPO) This register controls the Compute Operation. Address: E008_0000h base + 40h offset = E008_0040h Reset Reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 405: Functional Description
• FPU invalid operation interrupt is enabled (FDZCE) and an invalid occurs (FDZC) 18.3.1.1 Determining source of the interrupt To determine the exact source of the interrupt qualify the interrupt status flags with the corresponding interrupt enable bits. 1. From MCM_ISCR[31:16] && MCM_ISCR[15:0] K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 406 Functional description 2. Search the result for asserted flags, which indicate the exact interrupt sources K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 407: Crossbar Switch Lite (Axbs-Lite)
• Symmetric crossbar bus switch implementation • Allows concurrent accesses from different masters to different slaves • Up to single-clock 32-bit transfer • Programmable configuration for fixed-priority or round-robin slave port arbitration (see the chip-specific information). K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 408: Memory Map / Register Definition
This is done to save the initial clock of arbitration delay that otherwise would be seen if the same master had to arbitrate to gain control of the slave port. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 409: Arbitration
• The new requesting master's priority level is higher than that of the current master. Both of the following are true: At the next arbitration point for the undefined length burst transfer Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 410: Initialization/Application Information
19.4 Initialization/application information No initialization is required for the crossbar switch. See the chip-specific crossbar switch information for the reset state of the arbitration scheme. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 411: Peripheral Bridge (Aips-Lite)
The slave devices connected to the peripheral bridge are modules which contain a programming model of control and status registers. The system masters read and write these registers through the peripheral bridge. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 412: Memory Map/Register Definition
All accesses to the peripheral slots must be sized less than or equal to the designated peripheral slot size. If an access is attempted that is larger than the targeted port, an error response is generated. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 413: Direct Memory Access Multiplexer (Dmamux)
21.1.1 Overview The Direct Memory Access Multiplexer (DMAMUX) routes DMA sources, called slots, to any of the 16 DMA channels. This process is illustrated in the following figure. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 414: Features
• Each channel router can be assigned to one of the possible peripheral DMA slots or to one of the always-on slots. 21.1.3 Modes of operation The following operating modes are available: • Disabled mode K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 415: External Signal Description
21.3.1/416 4002_1005 Channel Configuration register (DMAMUX_CHCFG6) 21.3.1/416 4002_1006 Channel Configuration register (DMAMUX_CHCFG5) 21.3.1/416 4002_1007 Channel Configuration register (DMAMUX_CHCFG4) 21.3.1/416 4002_1008 Channel Configuration register (DMAMUX_CHCFG11) 21.3.1/416 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 416: Channel Configuration Register (Dmamux_Chcfgn)
DMA channel. DMA channel is enabled DMA Channel Trigger Enable TRIG Enables the periodic trigger capability for the triggered DMA channel. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 417: Functional Description
The trigger is generated by the periodic interrupt timer (PIT); as such, the configuration of the periodic triggering interval is done via configuration registers in the PIT. See the section on periodic interrupt timer for more information on this topic. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 418 This trigger works by gating the request from the peripheral to the DMA until a trigger event has been seen. This is illustrated in the following figure. Peripheral request Trigger DMA request Figure 21-3. DMAMUX channel triggering: normal operation K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 419: Dma Channels With No Triggering Capability
21.4.2 DMA channels with no triggering capability The other channels of the DMAMUX provide the normal routing functionality as described in Modes of operation. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 420: Always-Enabled Dma Sources
DMA registers after every minor loop. For this option, the DMA channel must be disabled in the DMA channel MUX. • Use an always-enabled DMA source. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 421: Initialization/Application Information
DMA channels that have triggering capability. To configure source #5 transmit for use with DMA channel 1, with periodic triggering capability: 1. Write 0x00 to CHCFG1. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 422 *CHCFG10= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0009); volatile unsigned char *CHCFG11= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0008); volatile unsigned char *CHCFG12= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000F); volatile unsigned char *CHCFG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000E); K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 423 *CHCFG12= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000F); volatile unsigned char *CHCFG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000E); volatile unsigned char *CHCFG14= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D); volatile unsigned char *CHCFG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C); K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 424 Initialization/application information In File main.c: #include "registers.h" *CHCFG8 = 0x00; *CHCFG8 = 0x87; K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 425: Enhanced Direct Memory Access (Edma)
• Local memory containing transfer control descriptors for each of the 16 channels 22.1.1 eDMA system block diagram Figure 22-1 illustrates the components of the eDMA system, including the eDMA module ("engine"). K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 426: Block Parts
After the minor loop completes execution, the address path hardware writes Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 427: Features
The eDMA module features: • All data movement via dual-address transfers: read from source, write to destination • Programmable source and destination addresses and transfer size • Support for enhanced addressing modes K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 428: Modes Of Operation
• Support for complex data structures In the discussion of this module, n is used to reference the channel number. 22.2 Modes of operation The eDMA operates in the following modes: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 429: Memory Map/Register Definition
0, channel 1, ... channel 15. Each TCDn definition is presented as 11 registers of 16 or 32 bits. 22.3.2 TCD initialization Prior to activating a channel, you must initialize its TCD with the appropriate transfer profile. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 430: Tcd Structure
Enable Error Interrupt Register (DMA_EEI) 0000_0000h 22.3.8/448 4000_8018 Clear Enable Error Interrupt Register (DMA_CEEI) (always 22.3.9/450 reads 0) 4000_8019 Set Enable Error Interrupt Register (DMA_SEEI) (always 22.3.10/451 reads 0) Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 431 See section 22.3.21/468 4000_9000 TCD Source Address (DMA_TCD0_SADDR) Undefined 22.3.22/469 4000_9004 TCD Signed Source Address Offset (DMA_TCD0_SOFF) Undefined 22.3.23/469 4000_9006 TCD Transfer Attributes (DMA_TCD0_ATTR) Undefined 22.3.24/470 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 432 TCD Current Minor Loop Link, Major Loop Count (Channel 4000_9036 Undefined 22.3.31/476 Linking Enabled) (DMA_TCD1_CITER_ELINKYES) 4000_9036 DMA_TCD1_CITER_ELINKNO Undefined 22.3.32/477 TCD Last Destination Address Adjustment/Scatter Gather 4000_9038 Undefined 22.3.33/478 Address (DMA_TCD1_DLASTSGA) Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 433 TCD Signed Minor Loop Offset (Minor Loop Mapping 4000_9068 Enabled and Offset Disabled) Undefined 22.3.26/472 (DMA_TCD3_NBYTES_MLOFFNO) TCD Signed Minor Loop Offset (Minor Loop Mapping and 4000_9068 Undefined 22.3.27/473 Offset Enabled) (DMA_TCD3_NBYTES_MLOFFYES) Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 434 Undefined 22.3.35/481 (DMA_TCD4_BITER_ELINKYES) TCD Beginning Minor Loop Link, Major Loop Count 4000_909E Undefined 22.3.36/482 (Channel Linking Disabled) (DMA_TCD4_BITER_ELINKNO) 4000_90A0 TCD Source Address (DMA_TCD5_SADDR) Undefined 22.3.22/469 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 435 TCD Signed Destination Address Offset 4000_90D4 Undefined 22.3.30/475 (DMA_TCD6_DOFF) TCD Current Minor Loop Link, Major Loop Count (Channel 4000_90D6 Undefined 22.3.31/476 Linking Enabled) (DMA_TCD6_CITER_ELINKYES) 4000_90D6 DMA_TCD6_CITER_ELINKNO Undefined 22.3.32/477 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 436 TCD Minor Byte Count (Minor Loop Mapping Disabled) 4000_9108 Undefined 22.3.25/471 (DMA_TCD8_NBYTES_MLNO) TCD Signed Minor Loop Offset (Minor Loop Mapping 4000_9108 Enabled and Offset Disabled) Undefined 22.3.26/472 (DMA_TCD8_NBYTES_MLOFFNO) Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 437 Address (DMA_TCD9_DLASTSGA) 4000_913C TCD Control and Status (DMA_TCD9_CSR) Undefined 22.3.34/479 TCD Beginning Minor Loop Link, Major Loop Count 4000_913E (Channel Linking Enabled) Undefined 22.3.35/481 (DMA_TCD9_BITER_ELINKYES) Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 438 TCD Signed Minor Loop Offset (Minor Loop Mapping and 4000_9168 Undefined 22.3.27/473 Offset Enabled) (DMA_TCD11_NBYTES_MLOFFYES) TCD Last Source Address Adjustment 4000_916C Undefined 22.3.28/474 (DMA_TCD11_SLAST) 4000_9170 TCD Destination Address (DMA_TCD11_DADDR) Undefined 22.3.29/475 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 439 TCD Beginning Minor Loop Link, Major Loop Count 4000_919E (Channel Linking Disabled) Undefined 22.3.36/482 (DMA_TCD12_BITER_ELINKNO) 4000_91A0 TCD Source Address (DMA_TCD13_SADDR) Undefined 22.3.22/469 4000_91A4 TCD Signed Source Address Offset (DMA_TCD13_SOFF) Undefined 22.3.23/469 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 440 TCD Signed Destination Address Offset 4000_91D4 Undefined 22.3.30/475 (DMA_TCD14_DOFF) TCD Current Minor Loop Link, Major Loop Count (Channel 4000_91D6 Undefined 22.3.31/476 Linking Enabled) (DMA_TCD14_CITER_ELINKYES) 4000_91D6 DMA_TCD14_CITER_ELINKNO Undefined 22.3.32/477 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 441: Control Register (Dma_Cr)
22.3.35/481 (DMA_TCD15_BITER_ELINKYES) TCD Beginning Minor Loop Link, Major Loop Count 4000_91FE (Channel Linking Disabled) Undefined 22.3.36/482 (DMA_TCD15_BITER_ELINKNO) 22.3.5 Control Register (DMA_CR) The CR defines the basic operating configuration of the DMA. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 442 NBYTES field is a 30-bit vector. When minor loop mapping is disabled (EMLM is 0), all 32 bits of TCDn word2 are assigned to the NBYTES field. Address: 4000_8000h base + 0h offset = 4000_8000h Reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 443 Halt DMA Operations HALT Normal operation Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 444: Error Status Register (Dma_Es)
• A cancel transfer with error bit that will be set when a transfer is canceled via the corresponding cancel transfer control bit Fault reporting and handling for more details. Address: 4000_8000h base + 4h offset = 4000_8004h Reset ERRCHN Reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 445 The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. • TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 446: Enable Request Register (Dma_Erq)
Address: 4000_8000h base + Ch offset = 4000_800Ch Reset ERQ9 ERQ8 ERQ7 ERQ6 ERQ5 ERQ4 ERQ3 ERQ2 ERQ1 ERQ0 Reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 447 The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled Enable DMA Request 4 ERQ4 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 448: Enable Error Interrupt Register (Dma_Eei)
The DMA error indicator and the error interrupt enable flag must be asserted before an error interrupt request for a given channel is asserted to the interrupt controller. Address: 4000_8000h base + 14h offset = 4000_8014h Reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 449 The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request Enable Error Interrupt 6 EEI6 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 450: Clear Enable Error Interrupt Register (Dma_Ceei)
If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: 4000_8000h base + 18h offset = 4000_8018h Read Write CAEE CEEI Reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 451: Set Enable Error Interrupt Register (Dma_Seei)
Sets All Enable Error Interrupts SAEE Set only the EEI bit specified in the SEEI field. Sets all bits in EEI 5–4 This field is reserved. Reserved Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 452: Clear Enable Request Register (Dma_Cerq)
Clear only the ERQ bit specified in the CERQ field Clear all bits in ERQ 5–4 This field is reserved. Reserved CERQ Clear Enable Request Clears the corresponding bit in ERQ. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 453: Set Enable Request Register (Dma_Serq)
Set only the ERQ bit specified in the SERQ field Set all bits in ERQ 5–4 This field is reserved. Reserved SERQ Set Enable Request Sets the corresponding bit in ERQ. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 454: Clear Done Status Bit Register (Dma_Cdne)
Clears only the TCDn_CSR[DONE] bit specified in the CDNE field Clears all bits in TCDn_CSR[DONE] 5–4 This field is reserved. Reserved CDNE Clear DONE Bit Clears the corresponding bit in TCDn_CSR[DONE] K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 455: Set Start Bit Register (Dma_Ssrt)
Set only the TCDn_CSR[START] bit specified in the SSRT field Set all bits in TCDn_CSR[START] 5–4 This field is reserved. Reserved SSRT Set START Bit Sets the corresponding bit in TCDn_CSR[START] K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 456: Clear Error Register (Dma_Cerr)
Clear only the ERR bit specified in the CERR field Clear all bits in ERR 5–4 This field is reserved. Reserved CERR Clear Error Indicator Clears the corresponding bit in ERR K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 457: Clear Interrupt Request Register (Dma_Cint)
Clear only the INT bit specified in the CINT field Clear all bits in INT 5–4 This field is reserved. Reserved CINT Clear Interrupt Request Clears the corresponding bit in INT K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 458: Interrupt Request Register (Dma_Int)
Address: 4000_8000h base + 24h offset = 4000_8024h Reset Reset DMA_INT field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 459 The interrupt request for corresponding channel is active Interrupt Request 4 INT4 The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 460: Error Register (Dma_Err)
A zero in any bit position has no affect on the corresponding channel’s current error status. The CERR is provided so the error indicator for a single channel can easily be cleared. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 461 An error in this channel has occurred Error In Channel 10 ERR10 An error in this channel has not occurred An error in this channel has occurred Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 462 An error in this channel has not occurred An error in this channel has occurred Error In Channel 0 ERR0 An error in this channel has not occurred An error in this channel has occurred K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 463: Hardware Request Status Register (Dma_Hrs)
Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Hardware Request Status Channel 15 HRS15 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 464 The HRS bit for its respective channel remains asserted for the period when a Hardware Request is Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically cleared by hardware. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 465 A hardware service request for channel 3 is not present A hardware service request for channel 3 is present Hardware Request Status Channel 2 HRS2 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 466: Enable Asynchronous Request In Stop Register (Dma_Ears)
Address: 4000_8000h base + 44h offset = 4000_8044h Reset Reset DMA_EARS field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 467 Enable asynchronous DMA request in stop mode for channel 4 EDREQ_4 Disable asynchronous DMA request for channel 4. Enable asynchronous DMA request for channel 4. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 468: Channel N Priority Register (Dma_Dchprin)
Channel n cannot be suspended by a higher priority channel’s service request. Channel n can be temporarily suspended by the service request of a higher priority channel. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 469: Tcd Source Address (Dma_Tcdn_Saddr)
22.3.23 TCD Signed Source Address Offset (DMA_TCDn_SOFF) Address: 4000_8000h base + 1004h offset + (32d × i), where i=0d to 15d Read SOFF Write Reset * Notes: • x = Undefined at reset. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 470: Tcd Transfer Attributes (Dma_Tcdn_Attr)
NOTE: Using a Reserved value causes a configuration error. 8-bit 16-bit 32-bit Reserved 16-byte burst 32-byte burst Reserved Reserved 7–3 Destination Address Modulo DMOD See the SMOD definition DSIZE Destination data transfer size Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 471: Tcd Minor Byte Count (Minor Loop Mapping Disabled) (Dma_Tcdn_Nbytes_Mlno)
TCD memory. If the major iteration count is completed, additional processing is performed. NOTE: An NBYTES value of 0x0000_0000 is interpreted as a 4 GB transfer. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 472: Tcd Signed Minor Loop Offset (Minor Loop Mapping Enabled And Offset Disabled)
The minor loop offset is applied to the SADDR Destination Minor Loop Offset enable DMLOE Selects whether the minor loop offset is applied to the destination address upon minor loop completion. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 473: Tcd Signed Minor Loop Offset (Minor Loop Mapping And Offset Enabled)
TCD_NBYTES_MLOFFNO register description. If minor loop mapping is disabled, then refer to the TCD_NBYTES_MLNO register description. Address: 4000_8000h base + 1008h offset + (32d × i), where i=0d to 15d MLOFF Reset MLOFF NBYTES Reset * Notes: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 474: Tcd Last Source Address Adjustment (Dma_Tcdn_Slast)
This register uses two's complement notation; the overflow bit is discarded. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 475: Tcd Destination Address (Dma_Tcdn_Daddr)
= Undefined at reset. DMA_TCDn_DOFF field descriptions Field Description DOFF Destination Address Signed Offset Sign-extended offset applied to the current destination address to form the next-state value as each destination write is completed. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 476: Tcd Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (Dma_Tcdn_Citer_Elinkyes)
CITER field from the Beginning Iteration Count (BITER) field. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 477: Tcd Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (Dma_Tcdn_Citer_Elinkno)
It is decremented each time the minor loop is completed and updated in the transfer control descriptor memory. After the major iteration count is exhausted, the channel performs a number of operations, for Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 478: Tcd Last Destination Address Adjustment/Scatter Gather Address (Dma_Tcdn_Dlastsga)
This channel reload is performed as the major iteration count completes. The scatter/gather address must be 0-modulo-32-byte, otherwise a configuration error is reported. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 479: Tcd Control And Status (Dma_Tcdn_Csr)
The software clears it, or the hardware when the channel is activated. NOTE: This bit must be cleared to write the MAJORELINK or ESG bits. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 480 If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the INT when the current major iteration count reaches zero. The end-of-major loop interrupt is disabled. The end-of-major loop interrupt is enabled. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 481: Tcd Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (Dma_Tcdn_Biter_Elinkyes)
CITER field. The channel-to-channel linking is disabled The channel-to-channel linking is enabled 14–13 This field is reserved. Reserved 12–9 Link Channel Number LINKCH Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 482: Tcd Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (Dma_Tcdn_Biter_Elinkno)
15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel linking. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 483: Functional Description
22.4.1 eDMA basic data flow The basic flow of a data transfer can be partitioned into three segments. As shown in the following diagram, the first segment involves the channel activation: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 484 The following diagram illustrates the second part of the basic data flow: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 485 (if scatter/ gather is enabled). The updates to the TCD memory and the assertion of an interrupt request are shown in the following diagram. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 486: Fault Reporting And Handling
Each of these possible causes are detailed below: • The addresses and offsets must be aligned on 0-modulo-transfer-size boundaries. • The minor loop byte count must be a multiple of the source and destination transfer sizes. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 487 Due to pipeline effect, the next transfer is already in progress when the bus error is received by the eDMA. If a bus error K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 488 If a channel is terminated by an error and then issues another service request before the error is fixed, that channel executes and terminates with the same error condition. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 489: Channel Preemption
However, the microarchitecture of the eDMA also factors significantly into the resulting metric. 22.4.4.1 Peak transfer rates The peak transfer rates for several different source and destination transfers are shown in the following tables. These tables assume: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 490 In the case of an internal peripheral bus read and internal SRAM write, the combined data phase time is 4 cycles. For an SRAM read and internal peripheral bus write, it is 5 cycles. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 491 11.5 cycles (4 + (4+5)/2 + 3). This is the time from Cycle 4 to Cycle x +5. The resulting peak request rate, as a function of the system frequency, is shown in the following table. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 492 For an SRAM to internal peripheral bus transfer, PEAKreq = 150 MHz / [ 4 + (1 + 1) + (1 + 3) + 3 ] cycles = 11.5 Mreq/sec For an internal peripheral bus to SRAM transfer, K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 493: Initialization/Application Information
2. Write the channel priority levels to the DCHPRIn registers if a configuration other than the default is desired. 3. Enable error interrupts in the EEI register if so desired. 4. Write the 32-byte TCD for each channel that may request service. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 494 CPU intervention. DMA arbitration can occur after each minor loop, and one level of minor loop DMA preemption is allowed. The number of minor loops in a major loop is specified by the beginning iteration count (BITER). K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 495: Programming Errors
The eDMA performs various tests on the transfer control descriptor to verify consistency in the descriptor data. Most programming errors are reported on a per channel basis with the exception of channel priority error (ES[CPE]). K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 496: Arbitration Mode Considerations
(TCDn_CITER = TCDn_BITER = 1). The data transfer begins after the channel service request is acknowledged and the channel is selected to execute. After the transfer is complete, the TCDn_CSR[DONE] bit is set and an interrupt generates if properly enabled. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 497 Write 32-bits to location 0x2008 → third iteration of the minor loop. g. Read byte from location 0x100C, read byte from location 0x100D, read byte from 0x100E, read byte from 0x100F. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 498 Write 32-bits to location 0x2004 → second iteration of the minor loop. e. Read byte from location 0x1008, read byte from location 0x1009, read byte from 0x100A, read byte from 0x100B. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 499 Write 32-bits to location 0x201C → last iteration of the minor loop → major loop complete. 14. eDMA engine writes: TCDn_SADDR = 0x1000, TCDn_DADDR = 0x2000, TCDn_CITER = 2 (TCDn_BITER). K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 500: Monitoring Transfer Descriptor Status
There are two methods to test for minor loop completion when using software initiated service requests. The first is to read the TCDn_CITER field and test for a change. Another method may be extracted from the sequence shown below. The second method is K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 501 The true values of the SADDR, DADDR, and NBYTES are the values the eDMA engine currently uses in its internal register file and not the values in the TCD local memory for that channel. The addresses, SADDR and K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 502: Channel Linking
TCDn_CITER[E_LINK] = 1 TCDn_CITER[LINKCH] = 0xC TCDn_CITER[CITER] value = 0x4 TCDn_CSR[MAJOR_E_LINK] = 1 TCDn_CSR[MAJOR_LINKCH] = 0x7 executes as: 1. Minor loop done → set TCD12_CSR[START] bit K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 503: Dynamic Programming
This section provides recommended methods to change the programming model during channel execution. 22.5.7.1 Dynamically changing the channel priority The following two options are recommended for dynamically changing channel priority levels: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 504 NOTE The user must clear the TCD.done bit before writing the TCD.major.e_link bit. The TCD.done bit is cleared automatically by the eDMA engine after a channel begins execution. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 505 1. When the descriptors are built, write a unique TCD ID in the TCD.major.linkch field for each TCD associated with a channel using dynamic scatter/gather. 2. Write 1b to the TCD.d_req bit. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 506 If e_sg = 0b, read the 32 bit TCD dlast_sga field. If e_sg = 0b and the dlast_sga did not change, the attempted dynamic link did not succeed (the channel was already retiring). K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 507: Lockstep
Checker. To initialize the eDMA data output buffer, the eDMA must perform a one or more 32-bit data transfers using any data value. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 508 It saves the last recorded error. The VLD bit shows the user whether any error bits in the Error Register are set, thus indicating an error occurred that hasn't been cleared. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 509: External Watchdog Monitor (Ewm)
EWM_out signal. 23.1.1 Features Features of EWM module include: • Independent LPO_CLK clock source • Programmable time-out period specified in terms of number of EWM LPO_CLK clock cycles. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 510: Modes Of Operation
15 (EWM_refresh_time) peripheral bus clocks after exiting from stop mode. User must mask all interrupts prior to executing EWM refresh instructions. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 511: Block Diagram
Logic Cell Reset to Enable Counter Reset EWM_CLKPRESCALER[CLK_DIV] EWM_CTRL[EWMEN] EWM Refreshed Counter overflow EWM Refresh EWM_CMPH[COMPAREH] EWM_out /EWM_out Output EWM_CMPL[COMPAREL] Control EWM_in Mechanism EWM Service Register Figure 23-1. EWM Block Diagram K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 512: Ewm Signal Descriptions
INEN, ASSIN and EWMEN bits can be written once after a CPU reset. Modifying these bits more than once, generates a bus transfer error. Address: 4006_1000h base + 0h offset = 4006_1000h Read INTEN INEN ASSIN EWMEN Write Reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 513: Service Register (Ewm_Serv)
This fixed number of cycles is called EWM_refresh_time. 23.3.3 Compare Low Register (EWM_CMPL) The CMPL register is reset to zero after a CPU reset. This provides no minimum time for the CPU to refresh the EWM counter. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 514: Compare High Register (Ewm_Cmph)
EWM_CMPH field descriptions Field Description COMPAREH To prevent runaway code from changing this field, software should write to this field after a CPU reset even if the (default) maximum refresh time is required. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 515: Clock Prescaler Register (Ewm_Clkprescaler)
The EWM_out is a digital output signal used to gate an external circuit (application specific) that controls critical safety functions. For example, the EWM_out could be connected to the high voltage transistors circuits that control an AC motor in a large appliance. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 516: The Ewm_In Signal
(setting the CTRL[INEN] bit), the EWM_in signal must be in the deasserted state prior to the CPU start refreshing the EWM. This ensures that the EWM_out stays in the deasserted state; otherwise, the EWM_out output signal is asserted. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 517: Ewm Counter
EWM Service Register. The CPU must access the EWM service register with correct write of unique data within the windowed time frame as determined by the CMPL and CMPH registers for correct EWM refresh operation. Therefore, three possible conditions can occur: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 518: Ewm Interrupt
CLKPRESCALER[CLK_DIV]. This divided clock is used to run the EWM counter. NOTE The divided clock used to run the EWM counter must be no more than half the frequency of the bus clock. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 519: Watchdog Timer (Wdog)
• External system clock • Unlock sequence for allowing updates to write-once WDOG control/configuration bits. • All WDOG control/configuration bits are writable once only within 256 bus clock cycles of being unlocked. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 520: Functional Overview
• Count of WDOG resets as they occur. • Configurable interrupt on time-out to provide debug breadcrumbs. This is followed by a reset after 256 bus clock cycles. 24.3 Functional overview K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 521 Software can adjust the period of servicing or the time-out value for the watchdog timer to meet the needs of the application. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 522: Unlocking And Updating The Watchdog
The watchdog issues a reset, that is, interrupt-then-reset if enabled, to the system for any of these invalid unlock sequences: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 523: Watchdog Configuration Time (Wct)
Updates in the write-once registers take effect only after the WCT window closes with the following exceptions for which changes take effect immediately: • Stop, Wait, and Debug mode enable • IRQ_RST_EN The operations of refreshing the watchdog goes undetected during the WCT. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 524: Refreshing The Watchdog
However, the watchdog still generates a reset, or interrupt-then-reset if enabled, on a non- time-out exception. See Generated Resets and Interrupts. You need to unlock the watchdog before enabling it. A system reset brings the watchdog out of the disabled mode. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 525: Debug Modes Of Operation
Do not enable the watchdog interrupt during these tests. If required, you must ensure that the effective time-out value is greater than WCT time. See Generated Resets and Interrupts more details. To run a particular test: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 526: Quick Test
The byte test is a more thorough a test of the watchdog timer. In this test, the timer is split up into its constituent byte-wide stages that are run independently and tested for time-out against the corresponding byte of the time-out value register. The following figure explains the splitting concept: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 527: Backup Reset Generator
Two successive timer time-outs without an intervening system reset result in the backup reset generator routing out the time-out signal as a reset to the system. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 528: Generated Resets And Interrupts
Also, jobs such as counting the number of watchdog resets would not be done. 24.7 Memory map and register definition This section consists of the memory map and register descriptions. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 529: Watchdog Status And Control Register High (Wdog_Stctrlh)
WDOG functional test mode is disabled permanently until reset. 13–12 This 2-bit field selects the byte to be tested when the watchdog is in the byte test mode. BYTESEL[1:0] Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 530 Selects clock source for the WDOG timer and other internal timing operations. CLKSRC WDOG clock sourced from LPO . WDOG clock sourced from alternate clock source. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 531: Watchdog Status And Control Register Low (Wdog_Stctrll)
WDOG_TOVALH field descriptions Field Description TOVALHIGH Defines the upper 16 bits of the 32-bit time-out value for the watchdog timer. It is defined in terms of cycles of the watchdog clock. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 532: Watchdog Time-Out Value Register Low (Wdog_Tovall)
A refresh outside this window resets the system or if IRQRSTEN is set, it interrupts and then resets the system. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 533: Watchdog Window Register Low (Wdog_Winl)
20 bus cycles, resets the system, or if IRQRSTEN is set, it interrupts and then resets the system. 24.7.8 Watchdog Unlock register (WDOG_UNLOCK) Address: 4005_2000h base + Eh offset = 4005_200Eh Read WDOGUNLOCK Write Reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 534: Watchdog Timer Output Register High (Wdog_Tmrouth)
Address: 4005_2000h base + 12h offset = 4005_2012h Read TIMEROUTLOW Write Reset WDOG_TMROUTL field descriptions Field Description TIMEROUTLOW Shows the value of the lower 16 bits of the watchdog timer. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 535: Watchdog Reset Count Register (Wdog_Rstcnt)
When performing 8-bit accesses to the watchdog's 16-bit registers where the intention is to access both the bytes of a register, place the two 8-bit accesses one after the other in your code. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 536: Refresh And Unlock Operations With 8-Bit Access
16-bit value is correctly written, write4. Hence, the requirement of writing value2 of the sequence within 20 bus clock cycles of value1 is checked by measuring the gap between write2 and write4. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 537: Restrictions On Watchdog Operation
• The time-out value of the watchdog should be set to a minimum of four watchdog clock cycles. This is to take into account the delay in new settings taking effect in the watchdog clock domain. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 538 If the second refresh value is not written within 20 bus cycles of the first value, the system is reset, or interrupt-then- reset if enabled. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 539: Multipurpose Clock Generator (Mcg)
• Option to program and maximize DCO output frequency for a low frequency external reference clock source. • Option to prevent FLL from resetting its current locked frequency when switching clock modes if FLL reference frequency is not changed. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 540 • External clock monitor with reset and interrupt request capability to check for external clock failure when running in FBE, PEE, BLPE, or FEE modes • Lock detector with interrupt request capability for use with the PLL K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 541 • MCG Fixed Frequency Clock (MCGFFCLK) is provided as a clock source for other on-chip peripherals • MCG Internal Reference Clock (MCGIRCLK) is provided as a clock source for other on-chip peripherals This figure presents the block diagram of the MCG module. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 542 LOLS LOCK VDIV Filter /(24,25,26..55) Multipurpose Clock Generator (MCG) Figure 25-1. Multipurpose Clock Generator (MCG) block diagram NOTE Refer to the chip configuration chapter to identify the oscillator used in this MCU. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 543: Modes Of Operation
MCG Auto Trim Compare Value Low Register 25.3.10/ 4006_400B (MCG_ATCVL) 25.3.11/ 4006_400C MCG Control 7 Register (MCG_C7) 25.3.12/ 4006_400D MCG Control 8 Register (MCG_C8) 25.3.13/ 4006_4011 MCG Control 12 Register (MCG_C12) Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 544: Mcg Control 1 Register (Mcg_C1)
If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 . Internal Reference Select IREFS Selects the reference clock source for the FLL. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 545: Mcg Control 2 Register (Mcg_C2)
Selects the frequency range for the crystal oscillator or external clock source. See the Oscillator (OSC) chapter for more details and the device data sheet for the frequency ranges used. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 546: Mcg Control 3 Register (Mcg_C3)
The SCTRIM bits are binary weighted, that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value increases the period, and decreasing the value decreases the period. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 547: Mcg Control 4 Register (Mcg_C4)
The DRS bits select the frequency range for the FLL output, DCOOUT. When the LP bit is set, writes to the DRS bits are ignored. The DRST read field indicates the current frequency range for DCOOUT. The Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 548: Mcg Control 5 Register (Mcg_C5)
OSCINIT 0 bit should be checked to make sure it is set. MCGPLLCLK is inactive. MCGPLLCLK is active. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 549: Mcg Control 6 Register (Mcg_C6)
00110 01110 10110 11110 Reserve 00111 01111 10111 11111 Reserve 25.3.6 MCG Control 6 Register (MCG_C6) Address: 4006_4000h base + 5h offset = 4006_4005h Read LOLIE0 PLLS CME0 VDIV0 Write Reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 550 01000 10000 11000 00001 01001 10001 11001 00010 01010 10010 11010 00011 01011 10011 11011 00100 01100 10100 11100 00101 01101 10101 11101 00110 01110 10110 11110 00111 01111 10111 11111 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 551: Mcg Status Register (Mcg_S)
IREFS bit due to internal synchronization between clock domains. Source of FLL reference clock is the external reference clock. Source of FLL reference clock is the internal reference clock. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 552: Mcg Status And Control Register (Mcg_Sc)
Writing to C1, C3, C4, and SC registers or entering Stop mode aborts the auto trim operation and clears this bit. Auto Trim Machine disabled. Auto Trim Machine enabled. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 553 The LOCS0 indicates when a loss of OSC0 reference clock has occurred. The LOCS0 bit only has an effect when CME0 is set. This bit is cleared by writing a logic 1 to it when set. Loss of OSC0 has not occurred. Loss of OSC0 has occurred. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 554: Mcg Auto Trim Compare Value High Register (Mcg_Atcvh)
Values are used by Auto Trim Machine to compare and adjust Internal Reference trim values during ATM SAR conversion. 25.3.11 MCG Control 7 Register (MCG_C7) Address: 4006_4000h base + Ch offset = 4006_400Ch Read OSCSEL Write Reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 555: Mcg Control 8 Register (Mcg_C8)
Enables the loss of clock monitoring circuit for the output of the RTC external reference clock. The LOCRE1 bit will determine whether an interrupt or a reset request is generated following a loss of RTC Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 556: Mcg Control 12 Register (Mcg_C12)
Address: 4006_4000h base + 12h offset = 4006_4012h Read Write Reset MCG_S2 field descriptions Field Description Reserved This field is reserved. This read-only field is reserved and always has the value 0. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 557: Mcg Test 3 Register (Mcg_T3)
Returns to the state that was active before the MCU enters Stop mode Stop the MCU entered Stop mode, unless a reset occurs while in Stop mode. Figure 25-2. MCG mode state diagram K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 558 • C1[FRDIV] must be written to divide external reference clock to be within the range of 31.25 kHz to 39.0625 kHz • 0 is written to C6[PLLS]. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 559 The FLL is disabled in a low-power state. PLL Bypassed External PLL Bypassed External (PBE) mode is entered when all the following conditions occur: (PBE) • 10 is written to C1[CLKS]. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 560 2’b10 and S[LOCK] bit will clear without setting S[LOLS]. If C5[PLLSTEN]=1, the S[LOCK] bit will not get cleared and on exit the MCG will continue to run in PEE mode. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 561: Low-Power Bit Usage
(slow IRC) and 4 MHz (fast IRC). The fast IRC frequency can be divided down by programming of the FCRDIV to produce a frequency range of 32 kHz to 4 MHz. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 562: External Reference Clock
LOCRE bit is set. Otherwise the MCG sets the respective LOCS bit and the MCG generates a LOCS interrupt request. In the case where a OSC loss of clock is detected, the PLL LOCK status bit is cleared. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 563: Mcg Fixed Frequency Clock
Therefore, it is required that the MCG is configured in a clock mode where the reference clock used to generate the system clock is the external reference clock such as K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 564: Initialization / Application Information
The following sections include examples on how to initialize the MCG and properly switch between the various available modes. 25.5.1 MCG module initialization sequence The MCG comes out of reset configured for FEI mode. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 565 • If the MCG is in FEE, FBE, PEE, PBE, or BLPE mode, and C2[EREFS] was also set in step 1, wait here for S[OSCINIT0] bit to become set indicating that the external clock source has finished its initialization cycles and stabilized. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 566 5. Wait for the FLL lock time to guarantee FLL is running at new C4[DRST_DRS] and C4[DMX32] programmed frequency. To change from FEI clock mode to FBI clock mode, follow this procedure: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 567: Using A 32.768 Khz Reference
Each time any of these bits are changed (C6[PLLS], C1[IREFS], C1[CLKS], C2[IRCS], or C2[EREFS], the corresponding bits in the MCG status register (PLLST, IREFST, CLKST, IRCST, or OSCINIT) must be checked before moving on in the application software. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 568 This section will include several mode switching examples, using an 4 MHz external crystal. If using an external clock source less than 2 MHz, the MCG must not be configured for any of the PLL modes (PEE and PBE). K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 569 • C5[PRDIV] set to 5'b00001, or divide-by-2 resulting in a pll reference frequency of 4MHz/2 = 2 MHz. 3. Then, FBE must transition either directly to PBE mode or first through BLPE mode and then to PBE mode: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 570 Loop until S[CLKST] are 2'b11, indicating that the PLL output is selected to feed MCGOUTCLK in the current clock mode. • Now, with PRDIV of divide-by-2, and C6[VDIV] of multiply-by-24, MCGOUTCLK = [(4 MHz / 2) * 24] = 48 MHz. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 571 S[CLKST] = %11? ENTER BLPE MODE ? CONTINUE IN PEE MODE C2 = 0x1E (C2[LP] = 1) Figure 25-3. Flowchart of FEI to PEE mode transition using an 4 MHz crystal K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 572 PLLS clock is the FLL. 3. Next, FBE mode transitions into FBI mode: a. C1 = 0x54 • C1[CLKS] set to 2'b01 to switch the system clock to the internal reference clock. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 573 C2 = 0x02 • C2[LP] is 1 • C2[RANGE], C2[HGO], C2[EREFS], C1[IRCLKEN], and C1[IREFSTEN] bits are ignored when the C1[IREFS] bit is set. They can remain set, or be cleared at this point. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 574 BLPE MODE ? BLPE MODE ? (C2[LP]=1) CONTINUE IN BLPI MODE C2 = 0x1C (C2[LP] = 0) Figure 25-4. Flowchart of PEE to BLPI mode transition using an 4 MHz crystal K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 575 At this point, by default, the C4[DRST_DRS] bits are set to 2'b00 and C4[DMX32] is cleared to 0. If the MCGOUTCLK frequency of 40 MHz is desired instead, set the C4[DRST_DRS] bits to 0x01 to switch the FLL K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 576 C2 = 0x1C CHECK S[CLKST] = %00? C1 = 0x10 CONTINUE IN FEE MODE CHECK S[OSCINIT] = 1 ? Figure 25-5. Flowchart of BLPI to FEE mode transition using an 4 MHz crystal K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 577: Oscillator (Osc)
• Optionally external input bypass clock from EXTAL signal directly • One clock for MCU clock system • Two clocks for on-chip peripherals that can work in Stop modes Functional Description describes the module's operation in more detail. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 578: Block Diagram
Control and Decoding OSCCLK OSC clock selection logic STOP Figure 26-1. OSC Module Block Diagram 26.4 OSC Signal Descriptions The table found here shows the user-accessible signals available for the OSC module. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 579: External Crystal / Resonator Connections
2. With the low-power mode, the oscillator has the internal feedback resistor R . Therefore, the feedback resistor must not be externally with the Connection 3. XTAL EXTAL Crystal or Resonator Figure 26-2. Crystal/Ceramic Resonator Connections - Connection 1 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 580: External Clock Connections
In external clock mode, the pins can be connected as shown in the figure found here. NOTE XTAL can be used as a GPIO when the GPIO alternate function is configured for it. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 581: Memory Map/Register Definitions
After OSC is enabled and starts generating the clocks, the configurations such as low power and frequency range, must not be changed. Address: 4006_5000h base + 0h offset = 4006_5000h Read ERCLKEN EREFSTEN SC2P SC4P SC8P SC16P Write Reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 582 Disable the selection. Add 8 pF capacitor to the oscillator load. Oscillator 16 pF Capacitor Load Configure SC16P Configures the oscillator load. Disable the selection. Add 16 pF capacitor to the oscillator load. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 583: Functional Description
Functional details of the module can be found here. 26.8.1 OSC module states The states of the OSC module are shown in the following figure. The states and their transitions between each other are described in this section. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 584 MCU, refer to the chip configuration details. The EXTAL and XTAL pins are also decoupled from all other oscillator circuitry in this state. The OSC module circuitry is configured to draw minimal current. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 585: Osc Module Modes
(MCG, Timer, and so on) is configured to use the oscillator output clock (OSC_CLK_OUT). Table 26-3. Oscillator modes Mode Frequency Range Low-frequency, high-gain (32.768 kHz) up to f (39.0625 kHz) osc_lo osc_lo Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 586 (not sensitive to the DC level of EXTAL). Also in this mode, all external components except for the resonator itself are integrated, which includes the load capacitors and feeback resistor that biases EXTAL. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 587: Counter
There is no reset state associated with the OSC module. The counter logic is reset when the OSC is not configured to generate clocks. There are no sources of reset requests for the OSC module. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 588: Low Power Modes Operation
OSC is still functional in these modes. After waking up from Very Low Leakage Stop (VLLSx) modes, all OSC register bits are reset and initialization is required through software. 26.11 Interrupts The OSC module does not generate any interrupts. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 589: Rtc Oscillator (Osc32K)
• Automatic Gain Control (AGC) to optimize power consumption The RTC oscillator operations are described in detail in Functional Description 27.1.2 Block Diagram The following is the block diagram of the RTC oscillator. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 590: Rtc Signal Descriptions
27.2.1 EXTAL32 — Oscillator Input This signal is the analog input of the RTC oscillator. 27.2.2 XTAL32 — Oscillator Output This signal is the analog output of the RTC oscillator module. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 591: External Crystal Connections
EXTAL32 and XTAL32. In addition, there are two programmable capacitors with this oscillator, which can be used as the Cload of the oscillator. The programmable range is from 0pF to 30pF. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 592: Reset Overview
Reset Overview 27.6 Reset Overview There is no reset state associated with the RTC oscillator. 27.7 Interrupts The RTC oscillator does not generate any interrupts. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 593: Flash Memory Controller (Fmc)
64-bit flash memory location, and both a 4-way, 8-set cache and a single-entry 64-bit buffer can store previously accessed flash memory data for quick access times. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 594: Features
The programming model consists of the FMC control registers and the program visible cache (data and tag/valid entries). NOTE Program the registers only while the flash controller is idle (for example, execute from RAM). Changing configuration settings K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 595 [63:32] of data entry way 1, and U and L represent upper and set 0, and DATAW1S0L lower word, respectively. represents bits [31:0] of data entry way 1, set 0. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 596 Cache Data Storage (upper word) (FMC_DATAW0S0U) 0000_0000h 28.4.8/610 4001_F204 Cache Data Storage (lower word) (FMC_DATAW0S0L) 0000_0000h 28.4.9/611 4001_F208 Cache Data Storage (upper word) (FMC_DATAW0S1U) 0000_0000h 28.4.8/610 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 597 4001_F26C Cache Data Storage (lower word) (FMC_DATAW1S5L) 0000_0000h 28.4.10/ 4001_F270 Cache Data Storage (upper word) (FMC_DATAW1S6U) 0000_0000h 28.4.11/ 4001_F274 Cache Data Storage (lower word) (FMC_DATAW1S6L) 0000_0000h Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 598 4001_F2C4 Cache Data Storage (lower word) (FMC_DATAW3S0L) 0000_0000h 28.4.14/ 4001_F2C8 Cache Data Storage (upper word) (FMC_DATAW3S1U) 0000_0000h 28.4.15/ 4001_F2CC Cache Data Storage (lower word) (FMC_DATAW3S1L) 0000_0000h Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 599 Cache Data Storage (upper word) (FMC_DATAW3S6U) 0000_0000h 28.4.15/ 4001_F2F4 Cache Data Storage (lower word) (FMC_DATAW3S6L) 0000_0000h 28.4.14/ 4001_F2F8 Cache Data Storage (upper word) (FMC_DATAW3S7U) 0000_0000h 28.4.15/ 4001_F2FC Cache Data Storage (lower word) (FMC_DATAW3S7L) 0000_0000h K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 600: Flash Access Protection Register (Fmc_Pfapr)
These bits control whether prefetching is enabled, based on the logical number of the requesting crossbar switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. Prefetching for this master is enabled. Prefetching for this master is disabled. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 601 No access may be performed by this master Only read accesses may be performed by this master Only write accesses may be performed by this master Both read and write accesses may be performed by this master K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 602: Flash Bank 0 Control Register (Fmc_Pfb0Cr)
The bit setting definitions are for each bit in the field. Cache way is unlocked and may be displaced Cache way is locked and its contents are not displaced 23–20 Cache Invalidate Way x CINV_WAY[3:0] Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 603 Do not cache data references. Cache data references. Bank 0 Instruction Cache Enable B0ICE This bit controls whether instruction fetches are loaded into the cache. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 604 This bit controls whether the single entry page buffer is enabled in response to flash read accesses. Its operation is independent from bank 1's cache. A high-to-low transition of this enable forces the page buffer to be invalidated. Single entry buffer is disabled. Single entry buffer is enabled. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 605: Flash Bank 1 Control Register (Fmc_Pfb1Cr)
This read-only field is reserved and always has the value 0. 18–17 Bank 1 Memory Width B1MW[1:0] This read-only field defines the width of the bank 1 memory. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 606 This bit controls whether the single entry buffer is enabled in response to flash read accesses. Its operation is independent from bank 0's cache. A high-to-low transition of this enable forces the page buffer to be invalidated. Single entry buffer is disabled. Single entry buffer is enabled. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 607: Cache Tag Storage (Fmc_Tagvdw0Sn)
This read-only field is reserved and always has the value 0. 18–5 14-bit tag for cache entry tag[18:5] 4–1 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 1-bit valid for cache entry valid K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 608: Cache Tag Storage (Fmc_Tagvdw1Sn)
This read-only field is reserved and always has the value 0. 18–5 14-bit tag for cache entry tag[18:5] 4–1 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 1-bit valid for cache entry valid K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 609: Cache Tag Storage (Fmc_Tagvdw2Sn)
This read-only field is reserved and always has the value 0. 18–5 14-bit tag for cache entry tag[18:5] 4–1 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 1-bit valid for cache entry valid K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 610: Cache Tag Storage (Fmc_Tagvdw3Sn)
This section represents data for the upper word (bits [63:32]) of all sets in the indicated way. Address: 4001_F000h base + 200h offset + (8d × i), where i=0d to 7d data[63:32] Reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 611: Cache Data Storage (Lower Word) (Fmc_Dataw0Snl)
This section represents data for the upper word (bits [63:32]) of all sets in the indicated way. Address: 4001_F000h base + 240h offset + (8d × i), where i=0d to 7d data[63:32] Reset FMC_DATAW1SnU field descriptions Field Description data[63:32] Bits [63:32] of data entry K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 612: Cache Data Storage (Lower Word) (Fmc_Dataw1Snl)
This section represents data for the upper word (bits [63:32]) of all sets in the indicated way. Address: 4001_F000h base + 280h offset + (8d × i), where i=0d to 7d data[63:32] Reset FMC_DATAW2SnU field descriptions Field Description data[63:32] Bits [63:32] of data entry K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 613: Cache Data Storage (Lower Word) (Fmc_Dataw2Snl)
This section represents data for the upper word (bits [63:32]) of all sets in the indicated way. Address: 4001_F000h base + 2C0h offset + (8d × i), where i=0d to 7d data[63:32] Reset FMC_DATAW3SnU field descriptions Field Description data[63:32] Bits [63:32] of data entry K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 614: Cache Data Storage (Lower Word) (Fmc_Dataw3Snl)
• The cache is configured for least recently used (LRU) replacement for all four ways. • The cache is configured for data or instruction replacement. • The single-entry buffer is enabled. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 615: Configuration Options
When speculative reads are enabled, the FMC immediately requests the next sequential address after a read completes. By requesting the next word immediately, speculative reads can help to reduce or even eliminate wait states when accessing sequential code and/or data. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 616: Flash Access Control (Fac) Function
• Most secure state is supervisor/privileged secure: allows execute-only and provides supervisor-only access control. • Mid-level state is execute-only. • Unsecure state is where no access control states are set. Features: • Lightweight access control logic for on-chip flash memory K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 617 See section 28.5.4.1.2/ Execute-only Access Register Low (x_XACCL) See section 28.5.4.1.3/ Supervisor-only Access Register High (x_SACCH) See section 28.5.4.1.4/ Supervisor-only Access Register Low (x_SACCL) See section 28.5.4.1.5/ Configuration Register (x_CR) See section K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 618 For more about NVM characteristics, see the functional description. Any change made to an NVM location takes effect on the next system reset. The flash basis for the values is signified by x in the reset value. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 619 Reset * Notes: • Pre-programmed flash valuex = Undefined at reset. x_SACCH field descriptions Field Description SA[63:32] Supervisor Access Control for segments 63-32 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 620 The NUMSG and SGSIZE values are fixed for a device. The chip-specific basis for the values is signified by * in the reset value. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 621 64 Segment Encodings 256 KBytes 256 KBytes/64 = 4 KBytes 512 KBytes 512 KBytes/64 = 8 KBytes 1 MBytes 1 MBytes/64 = 16 KBytes 2 MBytes 2 MBytes/64 = 32 KBytes K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 622 The next table shows segment assignments relative to the flash location. Table 28-4. Flash Protection Ranges SAn and XAn Protected Segment Address Range Segment Size (Fraction of total Flash) 64 Segment Encodings Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 623 Figure 28-1. Program flash protection (64 segments) 28.5.4.2.1 Interface Signals Table 28-5. Interface Signals Signal Width From Description xacc 64 or 32 Platform Direct xacc (execute-only access control) register Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 624 (FPROT), it will be erased. RD1XA The target regions of the command is controlled by FAC. For RD1XA, if a flash sector is in an execute-only protected segment, it will be erase verified. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 625 • If any portion of a protected segment is not used by pre-loaded code, then it (the portion of a protected segment that is not used by pre-loaded code) should be programmed with NOPs, to prevent additional code from being programmed in that segment by hackers. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 626 0x6: // {user, data} && {supv+user, ifetch-only} case 0xc: // {supv, data} && {supv-only, ifetch-only} case 0xe: // {supv, data} && {supv+user, ifetch-only} fac_error = 1; break; } // switch() } // fac_evaluation() K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 627: Initialization And Application Information
FMC's cache might need to be disabled and/or flushed to prevent the possibility of returning stale data. Use the PFB0CR[CINV_WAY] field to invalidate the cache in this manner. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 628 Initialization and application information K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 629: Flash Memory Module (Ftfa)
('1') states and/or programmed ('0') states. Therefore, it is recommended that each flash block or sector be re-erased immediately prior to factory programming to ensure that the full data retention capability is achieved. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 630: Features
• Supports MCU security mechanisms which prevent unauthorized access to the flash memory contents 29.1.2 Block Diagram The block diagram of the flash memory module is shown in the following figure. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 631: Glossary
HSRUN — An MCU power mode enabling high-speed access to the memory resources in the flash module. The user has no access to the flash command set when the MCU is in HSRUN mode. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 632: External Signal Description
Word — 16 bits of data with an aligned word having byte-address[0] = 0. 29.2 External Signal Description The flash memory module contains no signals that connect off-chip. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 633: Memory Map And Registers
Read Resource commands in Read Once Command, Program Once Command Read Resource Command). The contents of the program flash IFR are summarized in the table found here and further described in the subsequent paragraphs. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 634: Register Descriptions
The flash memory module contains a set of memory-mapped control and status registers. NOTE While a command is running (FSTAT[CCIF]=0), register writes are not accepted to any register except FCNFG and K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 635 (FTFA_FCCOB9) Flash Common Command Object Registers 29.3.3.5/ 4002_000F (FTFA_FCCOB8) 29.3.3.6/ 4002_0010 Program Flash Protection Registers (FTFA_FPROT3) Undefined 29.3.3.6/ 4002_0011 Program Flash Protection Registers (FTFA_FPROT2) Undefined Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 636 Flash Access Segment Size Register (FTFA_FACSS) Undefined 29.3.3.10/ 4002_002B Flash Access Segment Number Register (FTFA_FACSN) Undefined 29.3.3.1 Flash Status Register (FTFA_FSTAT) The FSTAT register reports the operational status of the flash memory module. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 637 The FPVIOL bit is cleared by writing a 1 to FPVIOL while CCIF is set. Writing a 0 to the FPVIOL bit has no effect. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 638 Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read collision error is detected (see the description of FSTAT[RDCOLERR]). Erase All Request ERSAREQ Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 639 X in the reset value. Address: 4002_0000h base + 2h offset = 4002_0002h Read KEYEN MEEN FSLACC Write Reset * Notes: • x = Undefined at reset. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 640 NVM at reset. The function of the bits is defined in the device's Chip Configuration details. All bits in the register are read-only . K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 641 Some commands return information to the FCCOB registers. Any values returned to FCCOB are available for reading after the FSTAT[CCIF] flag returns to 1 by the memory controller. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 642 KB of program flash memory or less, FPROT1 is not used. For configurations with 16 KB of program flash memory, FPROT2 is not used. The bitfields are defined in each register as follows: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 643 Trying to alter data in any protected area in the program flash memory results in a protection violation error and sets the FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible if it contains any protected region. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 644 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the execute-only access control fields that are loaded during the reset sequence. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 645 Supervisor-only access register Program Flash IFR address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 0xB1 0xB9 SACCH3 0xB0 0xB8 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 646 The contents of this register are loaded during the reset sequence. Address: 4002_0000h base + 28h offset = 4002_0028h Read SGSIZE Write Reset * Notes: • x = Undefined at reset. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 647 Program flash memory is divided into 32 segments (64 Kbytes, 128 Kbytes) 0x28 Program flash memory is divided into 40 segments (160 Kbytes) 0x4x Program flash memory is divided into 64 segments (256 Kbytes, 512 Kbytes) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 648: Functional Description
NOTE Flash protection features are discussed further in AN4507: Using the Kinetis Security and Flash Protection Features . Not all features described in the application note are available on this device. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 649 Figure 29-3. Program flash execute-only access control (256KB or 512KB of program flash) • FTFA_SACC — • For 2 program flash sizes greater than 128KB, eight registers control 64 segments of the program flash memory as shown in the following figure K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 650: Interrupts
Some devices also generate a bus error response as a result of a Read Collision Error event. See the chip configuration information to determine if a bus error response is also supported. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 651: Flash Operation In Low-Power Modes
Chip Configuration details of this device for how to activate each mode. 29.4.6 Flash Reads and Ignored Writes The flash memory module requires only the flash address to execute a flash memory read. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 652: Read While Write (Rww)
Flash command operations are typically used to modify flash memory contents. The next sections describe: • The command write sequence used to set flash command parameters and launch execution • A description of all flash commands available K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 653 The command processing has several steps: 1. The flash memory module reads the command code and performs a series of parameter checks and protection checks, if applicable, which are unique to each command. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 654 FCCOB and FSTAT registers. 4. The flash memory module sets FSTAT[CCIF] signifying that the command has completed. The flow for a generic command write sequence is illustrated in the following figure. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 655 The following table summarizes the function of all flash commands. FCMD Command Program flash 0 Program flash 1 Function 0x00 Read 1s Block × × Verify that a program flash block is erased. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 656 0x45 Verify Backdoor × × Release MCU security Access Key after comparing a set of user-supplied security keys to those stored in the program flash. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 657 Only the operations marked 'OK' in the following table are permitted to run simultaneously on the program flash memories. Some operations cannot be executed simultaneously because certain hardware resources are shared by the memories. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 658: Margin Read Commands
If unexpected read results are encountered when checking flash memory contents at the 'user' margin levels, loss of information might soon occur during 'normal' readout. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 659: Flash Command Description
MCU with the collision error flag (FSTAT[RDCOLERR]) set. CAUTION Flash data must be in the erased state before being programmed. Cumulative programming of bits (adding more zeros) is not allowed. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 660 The Read 1s Section command checks if a section of program flash memory is erased to the specified read margin level. The Read 1s Section command defines the starting address and the number of phrases to be verified. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 661 The requested number of phrases is 0. FSTAT[ACCERR] Read-1s fails. FSTAT[MGSTAT0] 29.4.11.3 Program Check Command The Program Check command tests a previously programmed program flash longword to see if it reads correctly at the specified margin level. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 662 Table 29-12. Program Check Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid flash address is supplied FSTAT[ACCERR] Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 663 Resource Description Resource Size Local Address Range Select Code 0x00 Program Flash 0 IFR 256 Bytes 0x00_0000–0x00_00FF 0x01 Version ID 8 Bytes 0x00_0000–0x00_0007 1. Located in program flash 0 reserved space. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 664 Flash address [15:8] Flash address [7:0] Byte 0 program value Byte 1 program value Byte 2 program value Byte 3 program value 1. Must be longword aligned (Flash address [1:0] = 00). K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 665 Flash address [23:16] in the flash block to be erased Flash address [15:8] in the flash block to be erased Flash address [7:0] in the flash block to be erased 1. Must be longword aligned (Flash address [1:0] = 00). K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 666 FPROT registers). If the erase-verify fails the FSTAT[MGSTAT0] bit is set. The CCIF flag is set after the Erase Flash Sector operation completes. The Erase Flash Sector command is suspendable (see the FCNFG[ERSSUSP] bit and Figure 29-6). K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 667 Erase Flash Sector operation (CCIF is cleared) and the request to suspend the operation again (ERSSUSP is set). This minimum time period is required to ensure that the Erase Flash Sector operation will eventually complete. If the minimum period is continually K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 668 Aborting the erase leaves the bitcells in an indeterminate, partially-erased state. Data in this sector is not reliable until a new erase command fully completes. The following figure shows how to suspend and resume the Erase Flash Sector operation. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 669 Set CCIF ERSSCR Suspended Resume Erase? ERSSUSP: Bit in FCNFG register No, Abort SUSPACK: Internal Suspend Acknowledge Clear ERSSUSP User Cmd Interrupt/Suspend Figure 29-6. Suspend and Resume of Erase Flash Sector Operation K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 670 Apply the 'Factory' margin to the normal read-1 level Table 29-24. Read 1s All Blocks Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid margin choice is specified FSTAT[ACCERR] Read-1s fails FSTAT[MGSTAT0] K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 671 The Read Once command can be executed any number of times. Table 29-26. Read Once Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid record index is supplied FSTAT[ACCERR] K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 672 Command not available in current mode/security FSTAT[ACCERR] An invalid record index is supplied FSTAT[ACCERR] The requested record has already been programmed to a non-FFFF value FSTAT[ACCERR] Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 673 Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] Any region of the program flash memory is protected FSTAT[FPVIOL] Any errors have been encountered during the verify operation FSTAT[MGSTAT0] K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 674 0x0_0003 Key Byte 1 0x0_0002 Key Byte 2 0x0_0001 Key Byte 3 0x0_0000 Key Byte 4 0x0_0007 Key Byte 5 0x0_0006 Key Byte 6 0x0_0005 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 675 '1'. Table 29-33. Read 1s All Execute-only Segments Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0x4A (RD1XA) Read-1 Margin Choice K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 676 FXACC registers, verifies all segments are erased, and releases flash access control. Table 29-36. Erase All Execute-only Segments Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0x4B (ERSXA) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 677: Security
Flash security features are discussed further in AN4507: Using the Kinetis Security and Flash Protection Features . Note that not all features described in the application note are available on this device. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 678 If the keys match, the FSEC[SEC] bits are changed to unsecure the chip. The entire 8-byte key cannot be all 0s or all 1s; that is, 0000_0000_0000_0000h and FFFF_FFFF_FFFF_FFFFh are not accepted by the Verify K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 679: Reset Sequence
29.4.13 Reset Sequence On each system reset the flash memory module executes a sequence which establishes initial values for the flash block configuration parameters, FPROT, FOPT, FSEC, FXACC, FSACC, and FACNFG registers. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 680 If a reset occurs while any flash command is in progress, that command is immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. Commands and operations do not automatically resume after exiting reset. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 681: Overview
Memory contents can be read/erased/programmed from an external source, in a format that is compatible with many standalone flash memory chips, without requiring the removal of the microcontroller from the system board. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 682: Block Diagram
• Ability to reset the microcontroller, allowing it to boot from the flash memory after the memory has been configured. 30.1.3 Modes of operation The EzPort can operate in one of two modes, enabled or disabled. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 683: External Signal Descriptions
EZP_CK is the serial clock for data transfers. The serial data in (EZP_D) and chip select (EZP_CS) are registered on the rising edge of EZP_CK, while serial data out (EZP_Q) is driven on the falling edge of EZP_CK. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 684: Ezport Chip Select (Ezp_Cs)
Table 30-2. EzPort commands Address Accepted when Command Description Code Data Bytes Bytes secure? WREN Write Enable 0x06 WRDI Write Disable 0x04 RDSR Read Status Register 0x05 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 685: Command Descriptions
WRFCCOB) to be accepted. The write enable register field clears on reset, on a Write Disable command, and at the completion of write command. This command must not be used if a write is already in progress. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 686 Table 30-3. EzPort status register BEDIS Reset: 1. Reset value reflects the status of flash security out of reset. 3. Reset value reflects whether bulk erase is enabled or disabled out of reset. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 687 Flash security can be disabled by performing a BE command. 0 = Flash is not secure. 1 = Flash is secure. 30.3.1.4 Read Data K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 688 This command can be run with an EzPort clock (EZP_CK) frequency of half the internal system clock frequency of the microcontroller or slower. This command is not accepted if the WEF, WIP, or FS field in the EzPort status register is set. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 689 This command is not accepted if the WEF, WIP, or FS field is set or if the WEN field is not set in the EzPort status register. 30.3.1.7 Sector Erase EZP_CK EZP_CS EZP_D CMD[7:0]=0xD8 ADDRESS[23:0] EZP_Q Figure 30-8. Sector Erase command sequence K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 690 WIP field is set or if the WEN field is not set in the EzPort status register. 30.3.1.9 EzPort Reset Chip EZP_CK EZP_CS EZP_D CMD[7:0]=0xB9 EZP_Q Figure 30-10. Reset Chip command sequence K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 691 This command is not accepted if the WEF or WIP field is set or if the WEN field is not set in the EzPort status register. 30.3.1.11 Read FCCOB Registers at High Speed K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 692: Flash Memory Map For Ezport Access
EzPort address width to remain 24 bits. Table 30-5. Flash Memory Map for EzPort Access Valid start address Size Flash block Valid commands See device's chip 0x0000_0000 Flash READ, FAST_READ, SP, SE, BE configuration details K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 693: External Bus Interface (Flexbus)
• Can be directly connected to the following asynchronous or synchronous slave-only devices with little or no additional circuitry: • External ROMs • Flash memories • Programmable logic devices • Other simple target (slave) devices K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 694: Features
Output Enable—Sent to the external memory or peripheral to enable a read transfer. This signal is asserted during read accesses only when a chip-select matches the current address decode. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 695 FB_TA is asserted during a read transfer, FlexBus latches the data and then terminates the transfer. When FB_TA is asserted during a write transfer, the transfer is terminated. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 696: Memory Map/Register Definition
Register name Access Reset value (in bits) page (hex) 4000_C000 Chip Select Address Register (FB_CSAR0) 0000_0000h 31.3.1/697 4000_C004 Chip Select Mask Register (FB_CSMR0) 0000_0000h 31.3.2/698 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 697: Chip Select Address Register (Fb_Csarn)
NOTE: Because the FlexBus module is one of the slaves connected to the crossbar switch, it is only accessible within a certain memory range. See the chip memory map for the applicable FlexBus Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 698: Chip Select Mask Register (Fb_Csmrn)
Specifies whether the corresponding CSAR, CSMR, and CSCR contents are valid. Programmed chip- selects do not assert until the V bit is 1b (except for FB_CS0, which acts as the global chip-select). Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 699: Chip Select Control Register (Fb_Cscrn)
CSCR0 reset value. Address: 4000_C000h base + 8h offset + (12d × i), where i=0d to 5d EXTS ASET RDAH WRAH Reset BEM BSTR Reset * Notes: • x = Undefined at reset. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 700 1 cycle (default for all but FB_CS0 ) 2 cycles Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 701 Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 702: Chip Select Port Multiplexing Control Register (Fb_Cspmcr)
FlexBus Signal Group 2 Multiplex control GROUP2 Controls the multiplexing of the FB_CS4, FB_TSIZ0, and FB_BE_31_24 signals. 0000 FB_CS4 0001 FB_TSIZ0 0010 FB_BE_31_24 Any other value Reserved Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 703: Functional Description
• Multiplexed 32-bit address and 32-bit data • Multiplexed 32-bit address and 16-bit data (non-multiplexed 16-bit address and 16- bit data) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 704: Address Comparison
31.4.4 Connecting address/data lines The external device must connect its address and data lines as follows: • Address lines • FB_AD from FB_AD0 upward • Data lines K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 705: Bit Ordering
The following figure shows the byte lanes that external memory or peripheral connects to and the sequential transfers of a 32-bit transfer for the supported port sizes when byte lane shift is disabled. For example, an 8-bit memory connects to the single lane K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 706 The following figure shows the byte lanes that external memory or peripheral connects to and the sequential transfers of a 32-bit transfer for the supported port sizes when byte lane shift is enabled. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 707: Address/Data Bus Multiplexing
CSCRn[BLS] is 0b. FB_AD Port size and phase 31–24 23–16 15–8 7–0 Address phase Address 32-bit Data phase Data Address phase Address 16-bit Data phase Data Address Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 708: Data Transfer States
The FlexBus state machine controls the data-transfer operation. This figure shows the state-transition diagram for basic read and write cycles. Next Cycle Wait States The states are described in this table. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 709: Flexbus Timing Examples
• FB_A[Y] indicates an address bus that can be 32, 24, or 16 bits wide. 31.4.11.1 Basic Read Bus Cycle During a read cycle, the MCU receives data from memory or a peripheral device. The following figure shows a read cycle flowchart. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 710 However, some applications may find this feature beneficial. The address and data busses are muxed between the FlexBus and another module. At the end of the read bus cycles the address signals are indeterminate. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 711 Figure 31-4. Basic Read-Bus Cycle 31.4.11.2 Basic Write Bus Cycle During a write cycle, the device sends data to memory or to a peripheral device. The following figure shows the write cycle flowchart. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 712 The following figure shows the write cycle timing diagram. Note The address and data busses are muxed between the FlexBus and another module. At the end of the write bus cycles, the address signals are indeterminate. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 713 The following figure illustrates the basic byte read transfer to an 8-bit device with no wait states: • The address is driven on the full FB_AD[31:0] bus in the first clock. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 714 AA=0 FB_TSIZ[1:0] TSIZ = 01 Figure 31-7. Single Byte-Read Transfer The following figure shows the similar configuration for a write transfer. The data is driven from the second clock on FB_AD[31:24]. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 715 FB_AD[15:0] throughout the bus cycle. • The external device returns the read data on FB_AD[31:16] and may tristate the data line or continue driving the data one clock after FB_TA is sampled asserted. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 716 AA=0 FB_TSIZ[1:0] TSIZ = 10 Figure 31-9. Single Word-Read Transfer The following figure shows the similar configuration for a write transfer. The data is driven from the second clock on FB_AD[31:16]. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 717 AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ=10 Figure 31-10. Single Word-Write Transfer 31.4.11.3.3 Bus Cycle Sizing—Longword Transfer, 32-bit Device, No Wait States The following figure depicts a longword read from a 32-bit device. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 718 FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn BEM=0 FB_BE/BWEn BEM=1 AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ = 00 Figure 31-11. Longword-Read Transfer The following figure illustrates the longword write to a 32-bit device. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 719 Wait states can give the peripheral or memory more time to return read data or sample write data. The following figures show the basic read and write bus cycles (also shown in Figure 31-4 Figure 31-9) with the default of no wait states respectively. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 720 TSIZ FB_AD[Y:0] indicates a 32-, 16-, 8-bit address bus (or custom size). FB_AD[31:X] indicates a 32-, 16-, 8-bit address/data bus (or custom size). Figure 31-13. Basic Read-Bus Cycle (No Wait States) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 721 If wait states are used, the S1 state repeats continuously until the chip-select auto- acknowledge unit asserts internal transfer acknowledge or the external FB_TA is recognized as asserted. The following figures show a read and write cycle with one wait state respectively. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 722 FB_TSIZ[1:0] TSIZ FB_AD[Y:0] indicates a 32-, 16-, 8-bit address bus (or custom size). FB_AD[31:X] indicates a 32-, 16-, 8-bit address/data bus (or custom size). Figure 31-15. Read-Bus Cycle (One Wait State) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 723 Each chip-select can be programmed to assert one to four clocks after transfer start/address-latch enable (FB_TS/FB_ALE) is asserted. The following figures show read- and write-bus cycles with two clocks of address setup respectively. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 724 FB_AD[Y:0] indicates a 32-, 16-, 8-bit address bus (or custom size). FB_AD[31:X] indicates a 32-, 16-, 8-bit address/data bus (or custom size). Figure 31-17. Read-Bus Cycle with Two-Clock Address Setup (No Wait States) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 725 Address and attributes can be held one to four clocks after chip-select, byte- selects, and output-enable negate. The following figures show read and write bus cycles with two clocks of address hold respectively. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 726 Address Hold Address Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn BEM=0 FB_BE/BWEn BEM=1 AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 31-19. Read Cycle with Two-Clock Address Hold (No Wait States) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 727 AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 31-20. Write Cycle with Two-Clock Address Hold (No Wait States) The following figure shows a bus cycle using address setup, wait states, and address hold. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 728: Burst Cycles
8-bit port takes two beats (two byte-sized transfers), for which FB_TSIZ[1:0] equals 10b throughout. A 32-bit transfer to an 8-bit port takes four beats (four byte-sized transfers), for which FB_TSIZ[1:0] equals 00b throughout. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 729 The transfer results in a 4-beat burst and the data is driven on FB_AD[31:24]. The transfer size is driven at 32-bit (00b) throughout the bus cycle. Note • In non-multiplexed address/data mode: the address on FB_A increments only during internally-terminated burst K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 730 FB_TBST AA=0 FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn BEM=0 FB_BE/BWEn BEM=1 AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ =00 AA=1 AA=0 Figure 31-22. 32-bit-Read burst from 8-Bit port 2-1-1-1 (no wait states) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 731 Data Data Data Data AA=1 FB_TBST AA=0 FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ=00 AA=1 AA=0 Figure 31-23. 32-bit-Write burst to 8-Bit port 3-1-1-1 (no wait states) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 732 The following figure shows a 32-bit write to an 8-bit device with burst inhibited. The transfer results in four individual transfers. The transfer size is driven at 32-bit (00b) during the first transfer and at byte (01b) during the next three transfers. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 733 Note CSCRn[WS] determines the number of wait states in the first beat. However, for subsequent beats, the CSCRn[WS] (or CSCRn[SWS] if CSCRn[SWSEN] = 1b) determines the number of wait states. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 734 Figure 31-25. 32-bit-read burst from 8-bit port 3-2-2-2 (one wait state) 31.4.12.8 32-bit-write burst to 8-bit port 3-2-2-2 (one wait state) The following figure illustrates a write burst transfer with one wait state. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 735 The following figure shows a read cycle with one clock of address setup and address hold. Note In non-multiplexed address/data mode, the address on FB_A increments only during internally-terminated burst cycles (CSCRn[AA] = 1b). The attached device must be able to K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 736 Figure 31-27. 32-bit-read burst from 8-bit port 3-1-1-1 (address setup and hold) 31.4.12.10 32-bit-write burst to 8-bit port 3-1-1-1 (address setup and hold) The following figure shows a write cycle with one clock of address setup and address hold. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 737: Extended Transfer Start/Address Latch Enable
FB_CSn asserts. See the following figure. NOTE When EXTS is set, CSCRn[WS] must be programmed to have at least one primary wait state. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 738: Bus Errors
• An access whose address is in a range covered by more than one chip-selects • A write to a reserved address in the memory map • A write to a reserved field in the CSPMCR • Any FlexBus accesses when FlexBus is secure K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 739: Initialization/Application Information
1. Invalidate the chip-select by writing 0b to the associated CSMR's Valid field (CSMRn[V]). 2. Write to the associated CSAR. 3. Write to the associated CSCR. 4. Write to the associated CSMR, including writing 1b to the Valid field (CSMRn[V]). K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 740 Initialization/Application Information K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 741: Cyclic Redundancy Check (Crc)
• Option for inversion of final CRC result • 32-bit CPU register programming interface 32.1.2 Block diagram The following is a block diagram of the CRC. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 742: Modes Of Operation
Register name Access Reset value (in bits) page (hex) 4003_2000 CRC Data register (CRC_DATA) FFFF_FFFFh 32.2.1/743 4003_2004 CRC Polynomial register (CRC_GPOLY) 0000_1021h 32.2.2/744 4003_2008 CRC Control register (CRC_CTRL) 0000_0000h 32.2.3/744 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 743: Crc Data Register (Crc_Data)
CRC Low Lower Byte When CTRL[WAS] is 1, values written to this field are part of the seed value. When CTRL[WAS] is 0, data written to this field is used for CRC checksum generation. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 744: Crc Polynomial Register (Crc_Gpoly)
CRC calculation. A new CRC calculation is initialized by asserting CTRL[WAS] and then writing the seed into the CRC data register. Address: 4003_2000h base + 8h offset = 4003_2008h TOTR FXOR WAS Reset Reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 745: Functional Description
Writes to the CRC data register are seed values. Width of CRC protocol. TCRC 16-bit CRC protocol. 32-bit CRC protocol. Reserved This field is reserved. This read-only field is reserved and always has the value 0. 32.3 Functional description K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 746: Crc Calculations
8. When all values have been written, read the final CRC result from CRC_DATA[LU:LL]. Transpose and complement operations are performed on the fly while reading or writing values. See Transpose feature CRC result complement for details. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 747: Transpose Feature
CTRL[TOT] or CTRL[TOTR] fields, according to the CRC calculation being used. The following types of transpose functions are available for writing to and reading from the CRC data register: 1. CTRL[TOT] or CTRL[TOTR] is 00. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 748 = {reg[0:7], reg[8:15],reg[16:23], reg[24:31]} Figure 32-3. Transpose type 10 4. CTRL[TOT] or CTRL[TOTR] is 11. Bytes are transposed, but bits are not transposed. reg[31:0] becomes {reg[7:0], reg[15:8], reg[23:16], reg[31:24]} K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 749: Crc Result Complement
CRC data register every time the CRC data register is read. When CTRL[FXOR] is cleared, reading the CRC data register accesses the raw checksum value. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 750 Functional description K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 751: Random Number Generator Accelerator (Rnga)
NIST-approved pseudo-random-number generator based on DES or SHA-1 and defined in NIST FIPS PUB 186-2 Appendix 3 and NIST FIPS PUB SP 800-90. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 752: Modes Of Operation
(randomness) from the clocks and stores it in shift registers. Sleep The ring-oscillator clocks are inactive; RNGA does not generate entropy. 33.2.1 Entering Normal mode To enter Normal mode, write 0 to CR[SLP]. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 753: Memory Map And Register Definition
0) 4002_900C RNGA Output Register (RNG_OR) 0000_0000h 33.3.4/757 33.3.1 RNGA Control Register (RNG_CR) Controls the operation of RNGA. Address: 4002_9000h base + 0h offset = 4002_9000h Reset INTM CLRI Reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 754 Disabled Enabled Specifies whether random-data generation and loading (into OR[RANDOUT]) is enabled. NOTE: This field is sticky. You must reset RNGA to stop RNGA from loading OR[RANDOUT] with data. Disabled Enabled K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 755: Rnga Status Register (Rng_Sr)
NOTE: If you read OR[RANDOUT] when SR[OREG_LVL] is not 0, then the contents of a random number contained in OR[RANDOUT] are returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL]. No words (empty) One word (valid) Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 756 Used only when high assurance is enabled (CR[HA]). Indicates that a security violation has occurred. NOTE: This field is sticky. To clear SR[SECV], you must reset RNGA. No security violation Security violation K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 757: Rnga Entropy Register (Rng_Er)
Reset RNG_OR field descriptions Field Description RANDOUT Random Output Stores a random-data word generated by RNGA. This is a read-only field. NOTE: Before reading RANDOUT, be sure it is valid (SR[OREG_LVL]=1). K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 758: Functional Description
OR when it is empty, RNGA returns all zeros and, if the interrupt is enabled, RNGA drives a request to the interrupt controller. Polling SR[OREG_LVL] is very important to make sure random values are present before reading from OR. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 759: Initialization/Application Information
2. Write 1 to CR[INTM], CR[HA], and CR[GO]. 3. Poll SR[OREG_LVL] until it is not 0. 4. When SR[OREG_LVL] is not 0, read the available random data from OR[RANDOUT]. 5. Repeat steps 3 and 4 as needed. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 760 Initialization/application information For application information, see Overview. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 761: Analog-To-Digital Converter (Adc)
• Output format in 2's complement 16-bit sign extended for differential modes • Output in right-justified unsigned format for single-ended • Single or continuous conversion, that is, automatic return to idle after single conversion K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 762: Block Diagram
• Temperature sensor • Hardware average function • Selectable voltage reference: external or alternate • Self-Calibration mode 34.1.2 Block diagram The following figure is the ADC module block diagram. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 763 CLPx TempP CLMx CLMx DADM0 Calibration Offset subtractor ADCOFS CALF DADM3 AVGE, AVGS Averager TempM MODE CFG1,2 Formatting REFH ALTH transfer REFL ACFE ACFGT, ACREN Compare ALTL Compare true logic CV1:CV2 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 764: Adc Signal Descriptions
The ADC module supports up to 4 pairs of differential inputs and up to 24 single-ended inputs. Each differential pair requires two inputs, DADPx and DADMx. The ADC also requires four supply/reference/ground connections. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 765: Analog Power (Vdda)
, and a ground reference that must be at the same potential as . The two pairs are external (V and V ) and alternate (V and V REFH REFL ALTH ALTL These voltage references are selected using SC2[REFSEL]. The alternate V ALTH K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 766: Analog Channel Inputs (Adx)
34.3.1/768 4002_7008 ADC Configuration Register 1 (ADC1_CFG1) 0000_0000h 34.3.2/772 4002_700C ADC Configuration Register 2 (ADC1_CFG2) 0000_0000h 34.3.3/773 4002_7010 ADC Data Result Register (ADC1_RA) 0000_0000h 34.3.4/774 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 767 34.3.1/768 4003_B008 ADC Configuration Register 1 (ADC0_CFG1) 0000_0000h 34.3.2/772 4003_B00C ADC Configuration Register 2 (ADC0_CFG2) 0000_0000h 34.3.3/773 4003_B010 ADC Data Result Register (ADC0_RA) 0000_0000h 34.3.4/774 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 768: Adc Status And Control Registers 1 (Adcx_Sc1N)
(ADC0_CLM1) ADC Minus-Side General Calibration Value Register 34.3.24/ 4003_B06C 0000_0020h (ADC0_CLM0) 34.3.1 ADC Status and Control Registers 1 (ADCx_SC1n) SC1A is used for both software and hardware trigger modes of operation. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 769 SC1B–SC1n registers do not initiate a new conversion. Address: Base address + 0h offset + (4d × i), where i=0d to 1d Reset AIEN DIFF ADCH Reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 770 When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. 00111 When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 771 Voltage reference selected is determined by SC2[REFSEL]. 11110 When DIFF=0,V is selected as input; when DIFF=1, it is reserved. Voltage reference REFSL selected is determined by SC2[REFSEL]. 11111 Module is disabled. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 772: Adc Configuration Register 1 (Adcx_Cfg1)
When ADLSMP=1, the long sample time select bits, (ADLSTS[1:0]), can select the extent of the long sample time. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 773: Adc Configuration Register 2 (Adcx_Cfg2)
Configuration Register 2 (CFG2) selects the special high-speed configuration for very high speed conversions and selects the long sample time duration during long sample mode. Address: Base address + Ch offset Reset ADLSTS Reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 774: Adc Data Result Register (Adcx_Rn)
The data result registers (Rn) contain the result of an ADC conversion of the channel selected by the corresponding status and channel control register (SC1A:SC1n). For every status and channel control register, there is a corresponding data result register. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 775 Address: Base address + 10h offset + (4d × i), where i=0d to 1d Reset ADCx_Rn field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Data result K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 776: Compare Value Registers (Adcx_Cvn)
Address: Base address + 18h offset + (4d × i), where i=0d to 1d Reset ADCx_CVn field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Compare Value. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 777: Status And Control Register 2 (Adcx_Sc2)
Conversion not in progress. Conversion in progress. Conversion Trigger Select ADTRG Selects the type of trigger used for initiating a conversion. Two types of trigger are selectable: Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 778 . This pair may be additional external pins or ALTH ALTL internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU Reserved Reserved K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 779: Status And Control Register 3 (Adcx_Sc3)
Calibration failed. ADC accuracy specifications are not guaranteed. 5–4 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 780: Adc Offset Correction Register (Adcx_Ofs)
Address: Base address + 28h offset Reset ADCx_OFS field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 781: Adc Plus-Side Gain Register (Adcx_Pg)
MG[15] and MG[14]. This register must be written by the user with the value described in the calibration procedure. Otherwise, the gain error specifications may not be met. For more information regarding the calibration procedure, please refer to the Calibration function section. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 782: Adc Plus-Side General Calibration Value Register (Adcx_Clpd)
Address: Base address + 34h offset CLPD Reset ADCx_CLPD field descriptions Field Description 31–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CLPD Calibration Value Calibration Value K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 783: Adc Plus-Side General Calibration Value Register (Adcx_Clps)
Address: Base address + 3Ch offset CLP4 Reset ADCx_CLP4 field descriptions Field Description 31–10 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CLP4 Calibration Value Calibration Value K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 784: Adc Plus-Side General Calibration Value Register (Adcx_Clp3)
Address: Base address + 44h offset CLP2 Reset ADCx_CLP2 field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CLP2 Calibration Value Calibration Value K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 785: Adc Plus-Side General Calibration Value Register (Adcx_Clp1)
Address: Base address + 4Ch offset CLP0 Reset ADCx_CLP0 field descriptions Field Description 31–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CLP0 Calibration Value Calibration Value K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 786: Adc Minus-Side General Calibration Value Register (Adcx_Clmd)
Address: Base address + 58h offset CLMS Reset ADCx_CLMS field descriptions Field Description 31–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 787: Adc Minus-Side General Calibration Value Register (Adcx_Clm4)
Address: Base address + 60h offset CLM3 Reset ADCx_CLM3 field descriptions Field Description 31–9 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CLM3 Calibration Value Calibration Value K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 788: Adc Minus-Side General Calibration Value Register (Adcx_Clm2)
Address: Base address + 68h offset CLM1 Reset ADCx_CLM1 field descriptions Field Description 31–7 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CLM1 Calibration Value Calibration Value K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 789: Adc Minus-Side General Calibration Value Register (Adcx_Clm0)
The ADC module has the capability of automatically comparing the result of a conversion with the contents of the CV1 and CV2 registers. The compare function is enabled by setting SC2[ACFE] and operates in any of the conversion modes and configurations. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 790: Clock Select And Divide Control
If the available clocks are too fast, the clock must be divided to the appropriate frequency. This divider is specified by CFG1[ADIV] and can be divide-by 1, 2, 4, or 8. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 791: Voltage Reference Selection
ADHWT signal to trigger a new conversion. The channel and status fields selected for the conversion depend on the active trigger select signal: • ADHWTSA active selects SC1A. • ADHWTSn active selects SC1n. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 792: Conversion Control
SC2[ADTRG]=1, and a hardware trigger select event, ADHWTSn, has occurred. The channel and status fields selected depend on the active trigger select signal: • ADHWTSA active selects SC1A. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 793 SC1n[COCO] sets only if the last of the selected number of conversions is completed and the compare condition is true. An interrupt is generated if the respective SC1n[AIEN] is high at the time that the respective SC1n[COCO] is set. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 794 CFG2[ADACKEN]=1, it remains active regardless of the state of the ADC or the MCU power mode. Power consumption when the ADC is active can be reduced by setting CFG1[ADLPC]. This results in a lower maximum value for f ADCK K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 795 2. When sampling is completed, the converter is isolated from the input channel and a successive approximation algorithm is applied to determine the digital value of the analog signal. 3. The result of the conversion is transferred to Rn upon completion of the conversion algorithm. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 796 9b differential 27 ADCK cycles 10b single-ended 20 ADCK cycles 11b differential 30 ADCK cycles 12b single-ended 20 ADCK cycles 13b differential 30 ADCK cycles Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 797 • 10-bit mode, with the bus clock selected as the input clock source • The input clock divide-by-1 ratio selected • Bus frequency of 8 MHz • Long sample time disabled • High-speed conversion disabled K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 798 Equation 1 on page 796. Table 34-9. Typical conversion time Variable Time SFCAdder 3 ADCK cycles + 5 bus clock cycles AverageNum 34 ADCK cycles LSTAdder 20 ADCK cycles HSCAdder K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 799 After the selected input is sampled and converted, the result is placed in an accumulator from which an average is calculated once the selected number of conversions have been completed. When hardware averaging is selected, the completion of a single conversion will not set SC1n[COCO]. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 800: Automatic Compare Function
CV1 And the result is less than or equal to CV2. Greater than Outside range, inclusive Compare true if the result is greater than or equal to CV1 Or the result is less than or equal to CV2. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 801: Calibration Function
Prior to calibration, the user must configure the ADC's clock source and frequency, low power configuration, voltage reference selection, sample time, and high speed configuration according to the application's clock source availability and needs. If the K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 802 7. Repeat the procedure for the minus-side gain calibration value. When calibration is complete, the user may reconfigure and use the ADC as desired. A second calibration may also be performed, if desired, by clearing and again setting SC3[CAL]. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 803: User-Defined Offset Function
ADC error specifications may not be met. Storing the value generated by the calibration function in memory before overwriting with a user- specified value is recommended. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 804: Temperature Sensor
• m is referred as temperature sensor slope in the device data sheet. It is the hot or cold voltage versus temperature slope in V/°C. For temperature calculations, use the V and temperature sensor slope values from TEMP25 the ADC Electricals table. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 805: Mcu Wait Mode Operation
34.4.10 MCU Normal Stop mode operation Stop mode is a low-power consumption Standby mode during which most or all clock sources on the MCU are disabled. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 806: Mcu Low-Power Stop Mode Operation
Therefore, the module must be re-enabled and re-configured following exit from Low-Power Stop mode. NOTE For the chip specific modes of operation, see the power management information for the device. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 807: Initialization Information
5. Update SC1:SC1n registers to select whether conversions will be single-ended or differential and to enable or disable conversion complete interrupts. Also, select the input channel which can be used to perform conversions. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 808 Bit 5 DIFF 0 Single-ended conversion selected. Bit 4:0 ADCH 00001 Input channel 1 selected as ADC input channel. RA = 0xxx Holds results of conversion. CV = 0xxx Holds compare value when compare function enabled. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 809: Application Information
Measurements. 34.6.1 External pins and routing 34.6.1.1 Analog supply pins Depending on the device, the analog power and ground supplies, V and V , of the ADC module are available as: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 810 V and V loop. The REFH REFL best external component to meet this current demand is a 0.1 μF capacitor with good K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 811: Sources Of Error
RAS + RADIN =SC / (FMAX * NUMTAU * CADIN) Figure 34-3. Sampling equation Where: RAS = External analog source resistance SC = Number of ADCK cycles used during sample window K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 812 REFL plane. • Operate the MCU in Wait or Normal Stop mode before initiating (hardware-triggered conversions) or immediately after initiating (hardware- or software-triggered conversions) the ADC conversion. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 813 12-bit modes. As a consequence, however, the code width of the first (0x000) conversion is only 1/2 LSB and the code width of the last (0xFF or 0x3FF) is 1.5 LSB. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 814 However, even small amounts of system noise can cause the converter to be indeterminate, between two codes, for a range of input voltages around the transition voltage. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 815 • Missing codes: Missing codes are those values never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and have no missing codes. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 816 Application information K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 817: Introduction
35.1.1 CMP features The CMP has the following features: • Operational over the entire supply range • Inputs may range from rail to rail • Programmable hysteresis control K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 818: 6-Bit Dac Key Features
The 6-bit DAC has the following features: • 6-bit resolution • Selectable supply reference source • Power Down mode to conserve power when not in use • Option to route the output to internal comparator input K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 819: Cmp, Dac And Anmux Diagram
• Two 8-to-1 channel mux • Operational over the entire supply range 35.1.4 CMP, DAC and ANMUX diagram The following figure shows the block diagram for the High-Speed Comparator, DAC, and ANMUX modules. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 820: Cmp Block Diagram
Reference Input 6 Window ANMUX and filter control CMPO MSEL[2:0] Figure 35-1. CMP, DAC and ANMUX block diagram 35.1.5 CMP block diagram The following figure shows the block diagram for the CMP module. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 821 CR0[FILTER_CNT] is set greater than 0x01. • If CR1[SE] = 1, the external SAMPLE input is used as sampling clock • If CR1[SE] = 0, the divided bus clock is used as sampling clock K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 822: Memory Map/Register Definitions
CMPx_CR0 field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. 6–4 Filter Sample Count FILTER_CNT Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 823: Cmp Control Register 1 (Cmpx_Cr1)
WE is cleared. However, avoid writing 1s to both field locations because this "11" case is reserved and may change in future implementations. Sampling mode is not selected. Sampling mode is selected. Windowing Enable Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 824 Enables the Analog Comparator module. When the module is not enabled, it remains in the off state, and consumes no power. When the user selects the same input from analog mux to the positive and negative port, the comparator is disabled automatically. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 825: Cmp Filter Period Register (Cmpx_Fpr)
Enables the DMA transfer triggered from the CMP module. When this field is set, a DMA request is asserted when CFR or CFF is set. DMA is disabled. DMA is enabled. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 826: Dac Control Register (Cmpx_Daccr)
Write Reset CMPx_DACCR field descriptions Field Description DAC Enable DACEN Enables the DAC. When the DAC is disabled, it is powered down to conserve power. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 827: Mux Control Register (Cmpx_Muxcr)
Minus Input Mux Control Determines which input is selected for the minus input of the comparator. For INx inputs, see CMP, DAC, and ANMUX block diagrams. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 828: Functional Description
The external sample input is enabled using CR1[SE]. When set, the output of the comparator is sampled only on rising edges of the sample input. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 829 SAMPLE=1 to generate COUTA, which is then resampled and filtered to generate COUT. See the Windowed/Filtered mode (#7). All other combinations of CR1[EN], CR1[WE], CR1[SE], CR0[FILTER_CNT], and FPR[FILT_PER] are illegal. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 830 Filter Interrupt control block control select CMPO COUT To other system functions WINDOW/SAMPLE bus clock Clock COUTA CMPO to prescaler divided FILT_PER CGMUX clock Figure 35-3. Comparator operation in Continuous mode K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 831 In Sampled, Non-Filtered mode, the analog comparator block is powered and active. The path from analog inputs to COUTA is combinational unclocked. Windowing control is completely bypassed. COUTA is sampled whenever a rising-edge is detected on the filter block clock input. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 832 COUTA is sampled whenever a rising edge is detected on the filter block clock input. The only difference in operation between Sampled, Non-Filtered (# 3A) and Sampled, Filtered (# 4A) is that, now, CR0[FILTER_CNT]>1, which activates filter operation. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 833 CMPO COUT To other SOC functions WINDOW/SAMPLE bus clock Clock COUTA CMPO to prescaler divided FILT_PER CGMUX clock SE=1 Figure 35-6. Sampled, Filtered (# 4A): sampling point externally driven K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 834 WINDOW signal is high. In actual operation, COUTA may lag the analog inputs by up to one bus clock cycle plus the combinational path delay through the comparator and polarity select logic. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 835 COUTA Clock CMPO to divided prescaler FILT_PER CGMUX clock SE=0 Figure 35-9. Windowed mode For control configurations which result in disabling the filter block, see Filter Block Bypass Logic diagram. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 836 FPR[FILT_PER] and the bus clock rate. Configuration for this mode is virtually identical to that for the Windowed/Filtered Mode shown in the next section. The only difference is that the value of CR0[FILTER_CNT] must be 1. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 837: Power Modes
Figure 35-11. Windowed/Filtered mode 35.3.2 Power modes 35.3.2.1 Wait mode operation During Wait and VLPW modes, the CMP, if enabled, continues to operate normally and a CMP interrupt can wake the MCU. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 838: Startup And Operation
The filter delay is specified in the Low-pass filter. • During operation, the propagation delay of the selected data paths must always be considered. It may take many bus clock cycles for COUT and SCR[CFR]/SCR[CFF] K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 839: Low-Pass Filter
In other words, SCR[COUT] will be 0 for some initial period, even when COUTA is at logic 1. Setting both CR1[SE] and FPR[FILT_PER] to 0 disables the filter and eliminates switching current associated with the filtering process. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 840 > 0x01 Sampled, Filtered mode + (CR0[FILTER_CNT] * ) + T SAMPLE > 0x01 > 0x00 + (CR0[FILTER_CNT] * FPR[FILT_PER] x T ) + T Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 841: Cmp Interrupts
DMA transfer request and clears the flag to allow a subsequent change on comparator output to occur and force another DMA request. The comparator can remain functional in STOP modes. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 842: Cmp Asynchronous Dma Support
STOP modes. After the data transfer has finished, system will go back to STOP modes. Refer to DMA chapters in the device reference manual for the asynchronous DMA function for details. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 843: Digital-To-Analog Converter
This section provides DAC functional description information. 35.8.1 Voltage reference source select • V connects to the primary voltage source as supply reference of 64 tap resistor ladder • V connects to an alternate voltage source K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 844: Dac Resets
This module has a single reset input, corresponding to the chip-wide peripheral reset. 35.10 DAC clocks This module has a single clock input, the bus clock. 35.11 DAC interrupts This module has no interrupts. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 845: Introduction
• Static operation in Normal Stop mode • 16-word data buffer supported with configurable watermark and multiple operation modes • DMA support 36.3 Block diagram The block diagram of the DAC module is as follows: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 846: Memory Map/Register Definition
DACBFRP & DACBBIEN DACBFMD DACTRGSE Figure 36-1. DAC block diagram 36.4 Memory map/register definition The DAC has registers to control analog comparator and programmable voltage divider to perform the digital-to-analog functions. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 847 DAC Control Register 1 (DAC1_C1) 36.4.5/852 4002_8023 DAC Control Register 2 (DAC1_C2) 36.4.6/853 4003_F000 DAC Data Low Register (DAC0_DAT0L) 36.4.1/849 4003_F001 DAC Data High Register (DAC0_DAT0H) 36.4.2/849 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 848 DAC Data High Register (DAC0_DAT15H) 36.4.2/849 4003_F020 DAC Status Register (DAC0_SR) 36.4.3/850 4003_F021 DAC Control Register (DAC0_C0) 36.4.4/851 4003_F022 DAC Control Register 1 (DAC0_C1) 36.4.5/852 4003_F023 DAC Control Register 2 (DAC0_C2) 36.4.6/853 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 849: Dac Data Low Register (Dacx_Datnl)
When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage based on the following formula. V * (1 + DACDAT0[11:0])/4096 When the DAC buffer is enabled, DATA[11:0] is mapped to the 16-word buffer. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 850: Dac Status Register (Dacx_Sr)
DAC trigger making the DAC read pointer increase. Write to this bit is ignored in FIFO mode. The DAC buffer read pointer is not equal to C2[DACBFUP]. The DAC buffer read pointer is equal to C2[DACBFUP]. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 851: Dac Control Register (Dacx_C0)
The DAC buffer read pointer top flag interrupt is disabled. The DAC buffer read pointer top flag interrupt is enabled. DAC Buffer Read Pointer Bottom Flag Interrupt Enable DACBBIEN Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 852: Dac Control Register 1 (Dacx_C1)
Buffer read pointer is disabled. The converted data is always the first word of the buffer. Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 853: Dac Control Register 2 (Dacx_C2)
When both the DAC and the buffer are enabled, the DAC converts the data in the data buffer to analog output voltage. The data buffer read pointer advances to the next word whenever a hardware or software trigger event occurs. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 854 FIFO access, address bit[1] needs to be 0; otherwise, the write is ignored. For any 32bit FIFO access, the Write_Pointer needs to be an EVEN number; otherwise, the write is ignored. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 855: Dma Operation
During reset, the DAC is configured in the default mode and is disabled. 36.5.4 Low-Power mode operation The following table shows the wait mode and the stop mode operation of the DAC module. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 856 In low-power stop modes, the DAC is fully shut down. NOTE The assignment of module modes to core modes is chip- specific. For module-to-core mode assignments, see the chapter that describes how modules are configured. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 857: Introduction
ADC, DAC, or CMP. The voltage reference has three operating modes that provide different levels of supply rejection and power consumption. The following figure is a block diagram of the Voltage Reference. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 858: Overview
37.1.2 Features The Voltage Reference has the following features: • Programmable trim register with 0.5 mV steps, automatically loaded with factory trimmed value upon reset • Programmable buffer mode selection: • Off K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 859: Voltage Reference (Vrefv1)
The following table shows the Voltage Reference signals properties. Table 37-1. VREF Signal Descriptions Signal Description VREF_OUT Internally-generated Voltage Reference output NOTE When the VREF output buffer is disabled, the status of the VREF_OUT signal is high-impedence. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 860: Memory Map And Register Definition
NOTE: Min = minimum and max = maximum voltage reference output. For minimum and maximum voltage reference output values, refer to the Data Sheet for this chip. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 861: Vref Status And Control Register (Vref_Sc)
Internal 1.75 V regulator is enabled. Second order curvature compensation enable ICOMPEN This bit should be written to 1 to achieve the performance stated in the data sheet. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 862: Functional Description
100 nF capacitor is required. Voltage Reference enabled, VREF_OUT available for low power buffer on internal and external use. 100 nF capacitor is required. Reserved Reserved K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 863: Voltage Reference Disabled, Sc[Vrefen] = 0
(Tstup) and the value is specified in the appropriate device data sheet. If this mode is entered when the VREF module is enabled then you must wait the longer of K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 864: Internal Voltage Regulator
1. Enable the chop oscillator (VREF_TRM[CHOPEN] = 1) 2. Configure the VREF_SC register to the desired settings with the internal regulator disabled, VREF_SC[REGEN] = 0 3. Wait > 300ns K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 865: Initialization/Application Information
The TRM[CHOPEN], SC[REGEN] and SC[ICOMPEN] bits must be written to 1 to achieve the performance stated in the device data sheet. NOTE See section "Internal voltage regulator" for details on the required sequence to enable the internal regulator. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 866 Initialization/Application Information K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 867: Introduction
• Trigger outputs can be enabled or disabled independently • One 16-bit delay register per pre-trigger output • Optional bypass of the delay registers of the pre-trigger outputs • Operation in One-Shot or Continuous modes K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 868: Implementation
• y—Pulse-Out number, valid value is from 0 to Y-1. NOTE The number of module output triggers to core is chip-specific. For module to core output triggers implementation, see the chip configuration information. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 869: Programmable Delay Block (Pdb)
38.1.4 DAC External Trigger Input Connections The implementation of DAC external trigger inputs is chip-specific. See the chip configuration information for details. 38.1.5 Block diagram This diagram illustrates the major components of the PDB. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 870 In this diagram, only one PDB channel n, one DAC interval trigger x, and one Pulse-Out y are shown. The PDB-enabled control logic and the sequence error interrupt logic are not shown. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 871: Modes Of Operation
External Trigger Input Source If the PDB is enabled and external trigger input source is selected, a positive edge on the EXTRG signal resets and starts the counter. 38.3 Memory map and register definition K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 872 4003_615C DAC Interval n register (PDB0_DACINT1) 0000_0000h 38.3.11/ 4003_6190 Pulse-Out n Enable register (PDB0_POEN) 0000_0000h 38.3.12/ 4003_6194 Pulse-Out n Delay register (PDB0_PO0DLY) 0000_0000h 38.3.12/ 4003_6198 Pulse-Out n Delay register (PDB0_PO1DLY) 0000_0000h K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 873: Status And Control Register (Pdbx_Sc)
Enables the PDB sequence error interrupt. When this field is set, any of the PDB channel sequence error flags generates a PDB sequence error interrupt. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 874 1011 Trigger-In 11 is selected. 1100 Trigger-In 12 is selected. 1101 Trigger-In 13 is selected. 1110 Trigger-In 14 is selected. 1111 Software trigger is selected. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 875 • LDOK is automatically cleared when the values in the internal buffers are loaded into the registers or when PDBEN bit (PDB Enable) is cleared. • Writing 0 to LDOK has no effect. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 876: Modulus Register (Pdbx_Mod)
PDBx_CNT field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. PDB Counter Contains the current value of the counter. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 877: Interrupt Delay Register (Pdbx_Idly)
Description 31–24 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 23–16 PDB Channel Pre-Trigger Back-to-Back Operation Enable Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 878: Channel N Status Register (Pdbx_Chns)
This read-only field is reserved and always has the value 0. PDB Channel Sequence Error Flags Only the lower M bits are implemented in this MCU. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 879: Channel N Delay 0 Register (Pdbx_Chndly0)
Specifies the delay value for the channel's corresponding pre-trigger. The pre-trigger asserts when the counter is equal to DLY. Reading this field returns the value of internal register that is effective for the current PDB cycle. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 880: Channel N Delay 1 Register (Pdbx_Chndly1)
PDBx_DACINTCn field descriptions Field Description 31–2 This field is reserved. Reserved This read-only field is reserved and always has the value 0. DAC External Trigger Input Enable Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 881: Dac Interval N Register (Pdbx_Dacintn)
Specifies the interval value for DAC interval trigger. DAC interval trigger triggers DAC[1:0] update when the DAC interval counter is equal to the DACINT. Reading this field returns the value of internal register that is effective for the current PDB cycle. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 882: Pulse-Out N Enable Register (Pdbx_Poen)
Specifies the delay 2 value for the PDB Pulse-Out. Pulse-Out goes low when the PDB counter is equal to the DLY2. Reading this field returns the value of internal register that is effective for the current PDB cycle. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 883: Functional Description
The waveforms shown in the following diagram show the pre-trigger and trigger outputs of PDB channel n. The delays can be independently set using the CHnDLYm registers, and the pre-triggers can be enabled or disabled in CHnC1[EN[m]]. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 884 A PDB interrupt can be generated if SC[PDBIE] is set and SC[DMAEN] is cleared. If SC[DMAEN] is set, then the PDB requests a DMA transfer when the SC[PDBIF] flag is set. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 885: Pdb Trigger Input Source Selection
ADC pre-trigger/trigger outputs and Pulse-Out generation have the same time base, because they both share the PDB counter. The pulse-out connections implemented in this MCU are described in the device's chip configuration details. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 886: Updating The Delay Registers
The following registers control the timing of the PDB operation; and in some of the applications, they may need to become effective at the same time. • PDB Modulus register (MOD) • PDB Interrupt Delay register (IDLY) • PDB Channel n Delay m register (CHnDLYm) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 887 The following diagrams show the cases of the internal registers being updated with SC[LDMOD] is 00 and x1. CHnDLY1 CHnDLY0 PDB counter SC[LDOK] Ch n pre-trigger 0 Ch n pre-trigger 1 Figure 38-4. Registers update with SC[LDMOD] = 00 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 888: Interrupts
SC[PDBEIE] = 1 38.4.6 DMA If SC[DMAEN] is set, PDB can generate a DMA transfer request when SC[PDBIF] is set. When DMA is enabled, the PDB interrupt is not issued. 38.5 Application information K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 889 If the applications need a really long delay value and use a prescaler set to 128, then the resolution would be limited to 128 peripheral clock cycles. Therefore, use the lowest possible prescaler and multiplication factor for a given application. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 890 Application information K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 891: Flextimer Module (Ftm)
TPM module. Several key enhancements are made: • Signed up counter • Deadtime insertion hardware • Fault control inputs K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 892: Features
• Prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128 • 16-bit counter • It can be a free-running counter or a counter with initial and final value • The counting can be up or up-down K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 893: Modes Of Operation
• Dual edge capture for pulse and period width measurement • Quadrature decoder with input filters, relative position counting, and interrupt on position count or capture of position count on external event K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 894: Block Diagram
For example, if a module instance supports only six channels, references to channel numbers 6 and 7 do not apply for that instance. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 895 7 and polarity control) mode logic input DECAPEN CH7F channel 7 COMBINE3 channel 7 interrupt CPWMS CH7TRIG match trigger CH7IE MS7B:MS7A ELS7B:ELS7A Figure 39-1. FTM block diagram K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 896: Ftm Signal Descriptions
This section presents a high-level summary of the FTM registers and how they are mapped. The registers and bits of an unavailable function in the FTM remain in the memory map and in the reset value, but they have no active function. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 897: Register Descriptions
0000_0000h 39.3.7/909 4002_6044 Channel (n) Status And Control (FTM3_C7SC) 0000_0000h 39.3.6/906 4002_6048 Channel (n) Value (FTM3_C7V) 0000_0000h 39.3.7/909 4002_604C Counter Initial Value (FTM3_CNTIN) 0000_0000h 39.3.8/909 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 898 4003_800C Channel (n) Status And Control (FTM0_C0SC) 0000_0000h 39.3.6/906 4003_8010 Channel (n) Value (FTM0_C0V) 0000_0000h 39.3.7/909 4003_8014 Channel (n) Status And Control (FTM0_C1SC) 0000_0000h 39.3.6/906 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 899 Input Capture Filter Control (FTM0_FILTER) 0000_0000h 39.3.20/ 4003_807C Fault Control (FTM0_FLTCTRL) 0000_0000h 39.3.21/ 4003_8080 Quadrature Decoder Control And Status (FTM0_QDCTRL) 0000_0000h 39.3.22/ 4003_8084 Configuration (FTM0_CONF) 0000_0000h Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 900 Synchronization (FTM1_SYNC) 0000_0000h 39.3.12/ 4003_905C Initial State For Channels Output (FTM1_OUTINIT) 0000_0000h 39.3.13/ 4003_9060 Output Mask (FTM1_OUTMASK) 0000_0000h 39.3.14/ 4003_9064 Function For Linked Channels (FTM1_COMBINE) 0000_0000h Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 901 4003_A034 Channel (n) Status And Control (FTM2_C5SC) 0000_0000h 39.3.6/906 4003_A038 Channel (n) Value (FTM2_C5V) 0000_0000h 39.3.7/909 4003_A03C Channel (n) Status And Control (FTM2_C6SC) 0000_0000h 39.3.6/906 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 902 FTM Fault Input Polarity (FTM2_FLTPOL) 0000_0000h 39.3.24/ 4003_A08C Synchronization Configuration (FTM2_SYNCONF) 0000_0000h 39.3.25/ 4003_A090 FTM Inverting Control (FTM2_INVCTRL) 0000_0000h 39.3.26/ 4003_A094 FTM Software Output Control (FTM2_SWOCTRL) 0000_0000h 39.3.27/ 4003_A098 FTM PWM Load (FTM2_PWMLOAD) 0000_0000h K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 903: Status And Control (Ftmx_Sc)
TOF remains set indicating an overflow has occurred. In this case, a TOF interrupt request is not lost due to the clearing sequence for a previous TOF. FTM counter has not overflowed. FTM counter has overflowed. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 904: Counter (Ftmx_Cnt)
Reset clears the CNT register. Writing any value to COUNT updates the counter with its initial value, CNTIN. When BDM is active, the FTM counter is frozen. This is the value that you may read. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 905: Modulo (Ftmx_Mod)
Address: Base address + 8h offset Reserved Reset FTMx_MOD field descriptions Field Description 31–16 This field is reserved. Reserved Modulo Value K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 906: Channel (N) Status And Control (Ftmx_Cnsc)
(set on channel (n) match, and clear on channel (n+1) match) Low-true pulses (clear on channel (n) match, and set on channel (n +1) match) Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 907 Rising edge Enabled Falling edge Enabled Rising and falling edges Address: Base address + Ch offset + (8d × i), where i=0d to 7d Reset CHIE MSB MSA ELSB ELSA Reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 908 FTM counter is not reset when the selected channel (n) input event is detected. FTM counter is reset when the selected channel (n) input event is detected. DMA Enable Enables DMA transfers for the channel. Disable DMA transfers. Enable DMA transfers. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 909: Channel (N) Value (Ftmx_Cnv)
FTM counter starts with the value 0x0000. To avoid this behavior, before the first write to select the FTM clock, write the new value to the the CNTIN register and then initialize the FTM counter by writing any value to the CNT register. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 910: Capture And Compare Status (Ftmx_Status)
CHnF remains set indicating an event has occurred. In this case, a CHnF interrupt request is not lost due to the clearing sequence for a previous CHnF. Address: Base address + 50h offset Reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 911 Channel 3 Flag CH3F See the register description. No channel event has occurred. A channel event has occurred. Channel 2 Flag CH2F See the register description. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 912: Features Mode Selection (Ftmx_Mode)
• Capture Test mode • PWM synchronization • Write protection • Channel output initialization These controls relate to all channels within this module. Address: Base address + 54h offset Reset FAULTM INIT Reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 913 The INIT bit is always read as 0. FTM Enable FTMEN This field is write protected. It can be written only when MODE[WPDIS] = 1. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 914: Synchronization (Ftmx_Sync)
The synchronization event selection also depends on the PWMSYNC (MODE register) and SYNCMODE (SYNCONF register) bits. See synchronization. Address: Base address + 58h offset Reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 915 The REINIT bit configures the synchronization when SYNCMODE is zero. FTM counter continues to count normally. FTM counter is updated with its initial value when the selected trigger is detected. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 916: Initial State For Channels Output (Ftmx_Outinit)
Selects the value that is forced into the channel output when the initialization occurs. The initialization value is 0. The initialization value is 1. Channel 6 Output Initialization Value CH6OI Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 917: Output Mask (Ftmx_Outmask)
This feature is used for BLDC control where the PWM signal is presented to an electric motor at specific times to provide electronic commutation. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 918 Channel output is masked. It is forced to its inactive state. Channel 3 Output Mask CH3OM Defines if the channel output is masked or unmasked. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 919: Function For Linked Channels (Ftmx_Combine)
Dual Edge Capture mode, Complementary, and Combine mode for each pair of channels (n) and (n+1), where n equals 0, 2, 4, and 6. Address: Base address + 64h offset Reset Reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 920 This field is write protected. It can be written only when MODE[WPDIS] = 1. The channel (n+1) output is the same as the channel (n) output. The channel (n+1) output is the complement of the channel (n) output. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 921 The Dual Edge Capture mode in this pair of channels is disabled. The Dual Edge Capture mode in this pair of channels is enabled. Complement Of Channel (n) For n = 4 COMP2 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 922 Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in Dual Edge Capture mode according to Table 39-2. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 923 DECAP bit is cleared automatically by hardware if dual edge capture – one-shot mode is selected and when the capture of channel (n+1) event is made. The dual edge captures are inactive. The dual edge captures are active. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 924: Deadtime Insertion Control (Ftmx_Deadtime)
Selects the division factor of the system clock. This prescaled clock is used by the deadtime counter. This field is write protected. It can be written only when MODE[WPDIS] = 1. Divide the system clock by 1. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 925: Ftm External Trigger (Ftmx_Exttrig)
Several channels can be selected to generate multiple triggers in one PWM period. See Channel trigger output Initialization trigger. Channels 6 and 7 are not used to generate channel triggers. Address: Base address + 6Ch offset Reserved Reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 926 Enables the generation of the channel trigger when the FTM counter is equal to the CnV register. The generation of the channel trigger is disabled. The generation of the channel trigger is enabled. Channel 5 Trigger Enable CH5TRIG Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 927: Channels Polarity (Ftmx_Pol)
That is, the safe value of a channel is the value of its POL bit. Address: Base address + 70h offset Reserved Reset Reserved POL7 POL6 POL5 POL4 POL3 POL2 POL1 POL0 Reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 928 Channel 1 Polarity POL1 Defines the polarity of the channel output. This field is write protected. It can be written only when MODE[WPDIS] = 1. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 929: Fault Mode Status (Ftmx_Fms)
39.3.18 Fault Mode Status (FTMx_FMS) This register contains the fault detection flags, write protection enable bit, and the logic OR of the enabled fault inputs. Address: Base address + 74h offset Reset Reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 930 Writing a 1 to FAULTF2 has no effect. FAULTF2 bit is also cleared when FAULTF bit is cleared. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 931: Input Capture Filter Control (Ftmx_Filter)
Writing to the FILTER register has immediate effect and must be done only when the channels 0, 1, 2, and 3 are not in input modes. Failure to do this could result in a missing valid signal. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 932: Fault Control (Ftmx_Fltctrl)
39.3.20 Fault Control (FTMx_FLTCTRL) This register selects the filter value for the fault inputs, enables the fault inputs and the fault inputs filter. Address: Base address + 7Ch offset Reset FFVAL Reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 933 Enables the fault input. This field is write protected. It can be written only when MODE[WPDIS] = 1. Fault input is disabled. Fault input is enabled. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 934 Fault Input 0 Enable FAULT0EN Enables the fault input. This field is write protected. It can be written only when MODE[WPDIS] = 1. Fault input is disabled. Fault input is enabled. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 935: Quadrature Decoder Control And Status (Ftmx_Qdctrl)
CH0FVAL field of FILTER. The phase A filter is also disabled when CH0FVAL is zero. Phase A input filter is disabled. Phase A input filter is enabled. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 936 The Quadrature Decoder mode has precedence over the other modes. See Table 39-2. This field is write protected. It can be written only when MODE[WPDIS] = 1. Quadrature Decoder mode is disabled. Quadrature Decoder mode is enabled. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 937: Configuration (Ftmx_Conf)
Selects the FTM behavior in BDM mode. See mode. This field is reserved. Reserved This read-only field is reserved and always has the value 0. NUMTOF TOF Frequency Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 938: Ftm Fault Input Polarity (Ftmx_Fltpol)
Fault Input 2 Polarity FLT2POL Defines the polarity of the fault input. This field is write protected. It can be written only when MODE[WPDIS] = 1. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 939: Synchronization Configuration (Ftmx_Synconf)
Reset INVC Reset FTMx_SYNCONF field descriptions Field Description 31–21 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 940 The software trigger activates the FTM counter synchronization. Synchronization Mode SYNCMODE Selects the PWM Synchronization mode. Legacy PWM synchronization is selected. Enhanced PWM synchronization is selected. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 941: Ftm Inverting Control (Ftmx_Invctrl)
This register has a write buffer. The INVmEN bit is updated by the INVCTRL register synchronization. Address: Base address + 90h offset Reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 942: Ftm Software Output Control (Ftmx_Swoctrl)
• The CHnOCV bits select the value that is forced at the corresponding channel (n) output. This register has a write buffer. The fields are updated by the SWOCTRL register synchronization. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 943 The software output control forces 0 to the channel output. The software output control forces 1 to the channel output. Channel 0 Software Output Control Value CH0OCV Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 944 The channel output is affected by software output control. Channel 0 Software Output Control Enable CH0OC The channel output is not affected by software output control. The channel output is affected by software output control. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 945: Ftm Pwm Load (Ftmx_Pwmload)
Include the channel in the matching process. Channel 5 Select CH5SEL Do not include the channel in the matching process. Include the channel in the matching process. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 946: Functional Description
Include the channel in the matching process. 39.4 Functional description The notation used in this document to represent the counters and the generation of the signals is shown in the following figure. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 947: Clock Source
FTM information for further details. Due to FTM hardware implementation limitations, the frequency of the fixed frequency clock must not exceed 1/2 of the system clock frequency. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 948: Prescaler
The FTM counter has these modes of operation: • Up counting • Up-down counting • Quadrature Decoder mode 39.4.3.1 Up counting Up counting is selected when: • QUADEN = 0, and • CPWMS = 0 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 949 FTM counting is up and signed. CNTIN[15] = 0 and CNTIN ≠ 0x0000 The initial value of the FTM counter is a positive number, so the FTM counting is up and unsigned. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 950 • Setting CNTIN to be greater than the value of MOD is not recommended as this unusual setting may make the FTM operation difficult to comprehend. However, there is no restriction on this configuration, and an example is shown in the following figure. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 951 The TOF bit is set when the FTM counter changes from MOD to (MOD – 1). If (CNTIN = 0x0000), the FTM counting is equivalent to TPM up-down counting, that is, up-down and unsigned counting. See the following figure. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 952 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 FTM counter TOF bit set TOF bit Figure 39-8. Example when the FTM counter is free running The FTM counter is also a free running counter when: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 953 FTM counter NUMTOF[4:0] 0x02 TOF counter 0x01 0x01 0x00 0x02 0x00 0x02 0x01 0x02 set TOF bit Figure 39-9. Periodic TOF when NUMTOF = 0x02 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 954: Input Capture Mode
While in BDM, the input capture function works as configured. When a selected edge event occurs, the FTM counter value, which is frozen because of BDM, is captured into the CnV register and the CHnF bit is set. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 955 As long as the new state is stable on the input, the counter continues to increment. When the counter is equal to CHnFVAL[3:0], the state change of the input signal is validated. It is then transmitted as a pulse edge to the edge detector. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 956 The figure below shows an example of input capture with filter enabled and the delay added by each part of the input capture logic. Note that the input signal is delayed only by the synchronizer and edge dector logic if the filter is disabled. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 957 The figure below shows the FTM counter reset when the selected input capture event is detected in a channel in input capture mode with ICRST = 1. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 958: Output Compare Mode
The CHnF bit is set and the channel (n) interrupt is generated if CHnIE = 1 at the channel (n) match (FTM counter = CnV). K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 959: Edge-Aligned Pwm (Epwm) Mode
CHnF bit is set and the channel (n) interrupt is generated if CHnIE = 1, however the channel (n) output is not modified and controlled by FTM. 39.4.6 Edge-Aligned PWM (EPWM) mode The Edge-Aligned mode is selected when: • QUADEN = 0 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 960 If (ELSnB:ELSnA = X:1), then the channel (n) output is forced low at the counter overflow when the CNTIN register value is loaded into the FTM counter, and it is forced high at the channel (n) match (FTM counter = CnV). See the following figure. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 961: Center-Aligned Pwm (Cpwm) Mode
0x0001 to 0x7FFF because values outside this range can produce ambiguous results. In the CPWM mode, the FTM counter counts up until it reaches MOD and then counts down until it reaches CNTIN. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 962 If (ELSnB:ELSnA = X:1), then the channel (n) output is forced low at the channel (n) match (FTM counter = CnV) when counting down, and it is forced high at the channel (n) match when counting up. See the following figure. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 963: Combine Mode
(n) match (FTM counter = C(n)V). The CH(n+1)F bit is set and the channel (n +1) interrupt is generated, if CH(n+1)IE = 1, at the channel (n+1) match (FTM counter = C(n+1)V). K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 964 ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 Figure 39-26. Channel (n) output if (CNTIN < C(n)V < MOD) and (CNTIN < C(n+1)V < MOD) and (C(n)V < C(n+1)V) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 965 0% duty cycle channel (n) output with ELSnB:ELSnA = X:1 Figure 39-29. Channel (n) output if (CNTIN < C(n)V < MOD) and (C(n)V is Almost Equal to CNTIN) and (C(n+1)V = MOD) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 966 0% duty cycle with ELSnB:ELSnA = 1:0 channel (n) output 100% duty cycle with ELSnB:ELSnA = X:1 Figure 39-31. Channel (n) output if C(n)V and C(n+1)V are not between CNTIN and MOD K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 967 (n) output 0% duty cycle with ELSnB:ELSnA = 1:0 channel (n) output 100% duty cycle with ELSnB:ELSnA = X:1 Figure 39-34. Channel (n) output if (C(n)V = C(n+1)V = MOD) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 968 0% duty cycle with ELSnB:ELSnA = 1:0 channel (n) output 100% duty cycle with ELSnB:ELSnA = X:1 Figure 39-36. Channel (n) output if (C(n)V < CNTIN) and (CNTIN < C(n+1)V < MOD) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 969 0% duty cycle with ELSnB:ELSnA = 1:0 channel (n) output 100% duty cycle with ELSnB:ELSnA = X:1 Figure 39-38. Channel (n) output if (C(n)V > MOD) and (CNTIN < C(n+1)V < MOD) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 970: Complementary Mode
(n+1) match occurs, that is, FTM counter = C(n+1)V. So, Combine mode allows the generation of asymmetrical PWM signals. 39.4.9 Complementary mode The Complementary mode is selected when: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 971: Registers Updated From Write Buffers
COMP = 1 Figure 39-42. Channel (n+1) output in Complementary mode with (ELSnB:ELSnA = X:1) NOTE The complementary mode is not available in Output Compare mode. 39.4.10 Registers updated from write buffers K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 972 When CnV register is written, independent of FTMEN bit. • CLKS[1:0] ≠ 0:0, and According to the selected mode, that is: • FTMEN = 0 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 973: Pwm Synchronization
If (HWTRIGMODE = 0) then the TRIGn bit is cleared when 0 is written to it or when the trigger n event is detected. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 974 Boundary cycle and loading points and the following figure. If (PWMSYNC = 0) and (REINIT = 1) then SWSYNC bit is cleared when the software trigger event occurs. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 975 For both counting modes, if neither CNTMIN nor CNTMAX are 1, then the boundary cycles are not used as loading points for registers updates. See the register synchronization descriptions in the following sections for details. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 976 = 0). However, it is expected that the MOD register be synchronized only by the enhanced PWM synchronization. In the case of enhanced PWM synchronization, the MOD register synchronization depends on SWWRBUF, SWRSTCNT, HWWRBUF, and HWRSTCNT bits according to this flowchart: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 977 If the trigger event was a software trigger, then the SWSYNC bit is cleared on the next selected K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 978 SWSYNC bit is cleared according to the following example. If the trigger event was a hardware trigger, then the TRIGn bit is cleared according to Hardware trigger. Examples with software and hardware triggers follow. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 979 1 to SWSYNC bit SWSYNC bit software trigger event selected loading point MOD register is updated Figure 39-51. MOD synchronization with (SYNCMODE = 0) and (PWMSYNC = 1) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 980 SYNCMODE = 0). However, it is expected that the OUTMASK register be synchronized only by the enhanced PWM synchronization. In the case of enhanced PWM synchronization, the OUTMASK register synchronization depends on SWOM and HWOM bits. See the following flowchart: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 981 ? clear TRIGn bit Figure 39-52. OUTMASK register synchronization flowchart In the case of legacy PWM synchronization, the OUTMASK register synchronization depends on PWMSYNC bit according to the following description. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 982 If (SYNCMODE = 0), (SYNCHOM = 1), and (PWMSYNC = 1), then this synchronization is made on the next enabled hardware trigger. The TRIGn bit is cleared according to Hardware trigger. An example with a hardware trigger follows. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 983 PWM synchronization (INVC = 1 and SYNCMODE = 1) according to the following flowchart. In the case of enhanced PWM synchronization, the INVCTRL register synchronization depends on SWINVC and HWINVC bits. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 984 HWTRIGMODE bit ? clear TRIGn bit Figure 39-56. INVCTRL register synchronization flowchart 39.4.11.9 SWOCTRL register synchronization The SWOCTRL register synchronization updates the SWOCTRL register with its buffer value. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 985 ? bit ? wait hardware trigger n update SWOCTRL with its buffer value update SWOCTRL with its buffer value HWTRIGMODE bit ? clear TRIGn bit Figure 39-57. SWOCTRL register synchronization flowchart K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 986 = 0). However, the FTM counter must be synchronized only by the enhanced PWM synchronization. In the case of enhanced PWM synchronization, the FTM counter synchronization depends on SWRSTCNT and HWRSTCNT bits according to the following flowchart. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 987 SWSYNC bit is cleared according to the following example. If the trigger event was a hardware trigger then the TRIGn bit is cleared according to Hardware trigger. Examples with software and hardware triggers follow. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 988 Figure 39-62. FTM counter synchronization with (SYNCMODE = 0), (HWTRIGMODE = 0), (REINIT = 1), (PWMSYNC = 1), and a hardware trigger was used K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 989: Inverting
NOTE INV(m) bit selects the inverting to the pair channels (n) and (n+1). Figure 39-63. Channels (n) and (n+1) outputs after the inverting in High-True (ELSnB:ELSnA = 1:0) Combine mode K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 990: Software Output Control
The software output control forces the channel output according to software defined values at a specific time in the PWM generation. The software output control is selected when: • QUADEN = 0 • DECAPEN = 0, and • CHnOC = 1 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 991 Software output control forces the following values on channels (n) and (n+1) when the COMP bit is one. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 992: Deadtime Insertion
If POL(n) = 1, POL(n+1) = 1, and the deadtime is enabled, then when the channel (n) match (FTM counter = C(n)V) occurs, the channel (n) output remains at the high value until the end of the deadtime delay when the channel (n) output is cleared. Similarly, K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 993 • The deadtime feature must be used only in Complementary mode. • The deadtime feature is not available in Output Compare mode. 39.4.14.1 Deadtime insertion corner cases If (PS[2:0] is cleared), (DTPS[1:0] = 0:0 or DTPS[1:0] = 0:1): K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 994 Figure 39-69. Example of the deadtime insertion (ELSnB:ELSnA = 1:0, POL(n) = 0, and POL(n+1) = 0) when the deadtime delay is comparable to channels (n) and (n+1) duty cycle K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 995: Output Mask
Table 39-10. Output mask result for channel (n) before the polarity control CHnOM Output Mask Input Output Mask Result inactive state inactive state active state active state inactive state inactive state active state K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 996: Fault Control
FAULTFn* control detector Fault filter (5-bit counter) system clock * where n = 3, 2, 1, 0 Figure 39-71. Fault input n control block diagram K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... - Page 997 If the automatic fault clearing is selected (FAULTM[1:0] = 1:1), then the channels output disabled by fault control is again enabled when the fault input signal (FAULTIN) returns to zero and a new PWM cycle begins. See the following figure. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
- Page 998 If the manual fault clearing is selected (FAULTM[1:0] = 0:1 or 1:0), then the channels output disabled by fault control is again enabled when the FAULTF bit is cleared and a new PWM cycle begins. See the following figure. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors...
-
Page 999: Polarity Control
• If POLn = 1, the channel (n) output polarity is low, so the logical zero is the active state and the logical one is the inactive state. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors... -
Page 1000: Initialization
See the description of the CLKS field in the Status and Control register. 39.4.19 Features priority The following figure shows the priority of the features used at the generation of channels (n) and (n+1) outputs signals. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 1000 NXP Semiconductors...
Need help?
Do you have a question about the K22F series and is the answer not in the manual?
Questions and answers