NXP Semiconductors MPC5644A Reference Manual page 102

Resets
Table 4-5. Reset Configuration Half Word (RCHW) field descriptions
Field
0–3 Reserved
These bit values are ignored when the halfword is read. Program to 0 for future compatibility.
SWT Software watchdog timer enable
This bit determines if the software watchdog timer is enabled after passing control to the user
application code.
0 Disable software watchdog timer
1 Enable software watchdog timer after reset. The timeout period is 261,600 system clocks.
WTE MCU core watchdog timer enable
This bit determines if the core software watchdog timer is enabled.after passing control to the user
application code.
0 Disable core software watchdog timer
1 Enable core watchdog timer after reset. The timeout period is 2.5*2
PS0 Port size
Defines the width of the data bus connected to the memory on D_CS0. After system reset, the BAM
changes D_CS0 to a 16-bit port to fetch the RCHW from either 16- or 32-bit external memories. Then
the BAM reconfigures the EBI as a 16- or 32-bit port, depending on this bit.
0 32-bit D_CS0 port size
1 16-bit D_CS0 port size
Note: Used in development bus boot modes only (not available on all packages). Do not clear this
bit if the device only has a 16-bit data bus.
VLE VLE Code Indicator
This bit configures the MMU entries 1–3 coded as Power Architecture embedded category
instructions or as Freescale VLE instructions.
0 User code executes as classic Book E code
1 User code executes as Freescale VLE code
BOOTID Boot identifier
This field serves two functions:
• Indicates which block in flash memory contains the boot program
• Indicates if the flash memory is programmed (BOOTID=0x5A) or invalid
When enabled by RCHW[SWT, WTE] bits, the watchdog timeout periods are as shown in
Note the following:
• The SWT clock source is directly from the crystal oscillator. The core WD is clocked by the PLL.
• The core WD timeouts reported here correspond to the PLL settings after reset. Core WD timeouts
will change as soon as the PLL is programmed with different multipliers.
Crystal frequency (MHz)
102
Table 4-6. Watchdog timeout periods
Core WD timeout
8 40.1
12 27.3
16 20.5
20 16.4
40 8.2
MPC5644A Microcontroller Reference Manual, Rev. 6
Description
17
1
(ms) SWT timeout
32.7
21.8
16.35
13.08
6.54
system clocks.
Table 4-6.
2
(ms)
Freescale Semiconductor