Channel Registers Layout - NXP Semiconductors MPC5644A Reference Manual

Enhanced Time Processing Unit (eTPU2)
24.4.5

Channel registers layout

The channel registers area is shown in
32 channels per engine. Reserved areas are placed to allow doubling the number of channels to 64 for each
eTPU engine.
24.4.6 Global channel registers
The registers in this section group, by type, the interrupt status and enable bits from all the channels. This
organization eases management of all channels or groups of channels by a single interrupt handler routine.
These bits, except the service and watchdog status, are mirrored in the individual channel registers,
grouped by channel.
792
Figure 24-12 and detailed in the next sections for eTPU systems of
0x200
Global Channel Registers
0x26C
RESERVED
0x400
Engine 1 Channel Registers
0x600
RESERVED
0x800
Engine 2 Channel Registers
0xA00
RESERVED
Figure 24-12. Channel registers area
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor