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Device Performance Optimization
be initialized in an application. The maximum frequency of operation for this device is specified in the
device data sheet.
System performance cannot be linearly extrapolated with system frequency, as is often the expectation. It
is due to the insertion of additional Flash wait states as system frequency increases that system
performance does not scale linearly. Take care to ensure that the correct internal and/or external Flash
configuration is chosen for the selected system frequency. The specific flash access times to be applied are
detailed in
Section 12.3.2.8, Bus Interface Unit Configuration Register
6.3.3
Flash bus interface unit
6.3.3.1
Description
The Flash Bus Interface Unit (FBIU) interfaces the system bus to the Flash memory array controller. The
FBIU contains prefetch buffers and a prefetch controller which, if enabled, speculatively prefetches
sequential lines of data from the Flash array into the buffer. Prefetch buffer hits allow zero-wait state
responses.
The Flash Bus Interface Configuration Registers (BIUCRx) control access to the internal Flash array. Its
settings define the number of cycles required to access the array, access times, and how the prefetch
buffering scheme operates.
Following negation of reset and execution of the BAM, the instruction and data prefetching is disabled,
and the number of cycles required to access the internal Flash array is set to its maximum value of fifteen
additional wait states.
6.3.3.2
Recommended configuration
As the operating frequency of the device is set by configuring the FMPLL (see
Frequency-modulated
PLL), the number of cycles required to access the internal array should be
configured accordingly. Note that the Flash BIUCRx registers cannot be altered by code executing from
the Flash array. Code for configuring the Flash should be executed from a separate memory array i.e copied
to and executed from system RAM.
Section 12.3.2.8, Bus Interface Unit Configuration Register
to configure flash wait state settings. The "Platform flash controller electrical characteristics" section of
the device data sheet contains the specific values for the flash wait state settings for a given operating
frequency. This also provides recommendations for the prefetch buffer settings. Note that the BIUCRx
settings may vary between revisions of the MPC5644A.
6.3.4
Crossbar switch
6.3.4.1
Description
The multi-port crossbar switch (XBAR) supports simultaneous connections between master ports and
slave ports. The XBAR allows for concurrent transactions to occur from any master port to any slave port.
If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher
120
MPC5644A Microcontroller Reference Manual, Rev. 6
(BIUCR).
Section 6.3.2,
(BIUCR), documents the register fields used
Freescale Semiconductor
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