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Enhanced Time Processing Unit (eTPU2)
24.5.2.2
Interrupts and data transfer requests
24.5.2.2.1
Interrupt types and sources
Each one of the eTPU channels can be a source of two requests: Channel Interrupt request and Data
Transfer Request. Channel Interrupts are targeted to a Host CPU. Data Transfer Requests may be targeted
to a data transfer module (e.g., a DMA controller). Interrupt and Data Transfer registers are used by the
Host to enable interrupts and data transfer requests, indicate their status and service them. Interrupt and
Data Transfer requests have the same sets of registers and external signals, and are handled in the same
way. They differ only by the fact that Data Transfer Requests are also cleared by the assertion of respective
DMA completion acknowledge line. Data Transfer Requests can be used as another source for Host
interrupts at MCU integration if not used with a DMA.
Interrupt and Data Transfer requests can be cleared even when engines are
in Module Disable Mode, through the Global Channel Registers, and also
DMA completion for Data Transfer requests.
Channel Interrupts and Data Transfer Requests can only be issued by eTPU microcode, through one of the
Channel Control instruction fields (see
Both Channel Interrupt and Data Transfer requests can be individually enabled for each channel.
eTPU Interrupt and Data Transfer Registers are mirrored in two organizations: grouped by Channel and
grouped by type (interrupt status, interrupt enable, data transfer status, data transfer enable). This allows
either "channel-oriented" or "bundled channel" Host interrupt service schemes, or a combination of them.
For a detailed description, refer to
channel
registers.
eTPU can also assert a Global Exception interrupt indicating a global illegal state. There are three possible
sources for a Global Exception:
•
Execution of an illegal instruction by the microengine (see
This Global Exception source is flagged by the bits ILF1 and ILF2 in register ETPU_MCR.
•
An SCM signature mismatch detected by the Multiple Input Signature Calculator (MISC). See
Section 24.5.10.3.1, SCM Test – Multiple input signature
bit SCMMISF in register ETPU_MCR.
•
Microcode request, through microinstruction field CIRC (see
interrupt and data transfer
MGE1(Engine 1) and MGE2(Engine 2) in register ETPU_MCR. The cause of this illegal state is
application-dependent. The microcode may write an error code into the SPRAM to indicate the
cause of the exception, for instance.
•
An SDM or SCM non-correctable error due to a microengine access
Global Exceptions cannot be directly disabled within eTPU, except by disabling its sources (MISC and
microcode), and it is cleared by writing 1 to the GEC bit in ETPU_MCR. Clearing Global Exception clears
all Global Exception source status bits (ILF1, ILF2, SCMMISF, MGE1, MGE2). If GEC is written 1 at the
same time any of the sources issues a Global Exception, both the interrupt and the status bit of that source
824
NOTE
Section 24.5.9.3.10, Channel interrupt and data transfer
Section 24.4.5, Channel registers
requests). This Global Exception source is flagged by bits
MPC5644A Microcontroller Reference Manual, Rev. 6
layout, and
Section 24.4.6, Global
Section 24.5.9.5, Illegal
calculator. This source is flagged by the
Section 24.5.9.3.10, Channel
Freescale Semiconductor
requests).
Instructions).
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