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Software Watchdog Timer (SWT)
two pseudorandom keys are written to the SWT_SR[WSC] field to service the watchdog. The key values
are determined by the pseudorandom key generator defined in
Equation
20-1. This algorithm will generate
16
a sequence of 2
different key values before repeating. The state of the key generator is held in the
SWT_SK register. For example, if SWT_SK[SK] is 0x0100 then the service sequence keys are 0x1103,
0x2136. In this mode, each time a valid key is written to the SWT_SR register, the SWT_SK register is
updated. So, after servicing the watchdog by writing 0x1103 and then 0x2136 to the SWT_SR[WSC] field,
SWT_SK[SK] is 0x2136 and the next key sequence is 0x3499, 0x7E2C.
Eqn. 20-1
16
SK
= (17*SK
+3) mod 2
n+1
n
Accesses to SWT registers occur with no peripheral bus wait states. (The peripheral bus bridge may add
one or more system wait states.) However, due to synchronization logic in the SWT design, recognition of
the service sequence or configuration changes may require up to three system plus seven counter clock
cycles.
If window mode is enabled (SWT_MCR[WND] bit is set), the service sequence must be performed in the
last part of the time-out period defined by the window register. The window is open when the down counter
is less than the value in the SWT_WN register. Outside of this window, service sequence writes are invalid
accesses and generate a bus error or reset depending on the value of the SWT_MCR[RIA] bit. For
example, if the SWT_TO register is set to 5000 and SWT_WN register is set to 1000 then the service
sequence must be performed in the last 20% of the time-out period. There is a short lag in the time it takes
for the window to open due to synchronization logic in the watchdog design. This delay could be up to
three system plus four counter clock cycles.
The interrupt then reset bit (SWT_MCR[ITR]) controls the action taken when a time-out occurs. If the
SWT_MCR[ITR] bit is not set, a reset is generated immediately on a time-out. If the SWT_MCR[ITR] bit
is set, an initial time-out causes the SWT to generate an interrupt and load the down counter with the
time-out period. If the service sequence is not written before the second consecutive time-out, the SWT
generates a system reset. The interrupt is indicated by the time-out interrupt flag (SWT_IR[TIF]). The
interrupt request is cleared by writing a '1' to the SWT_IR[TIF] bit.
The SWT_CO register shows the value of the down counter when the watchdog is disabled. When the
watchdog is enabled this register is cleared. The value shown in this register can lag behind the value in
the internal counter for up to six system plus eight counter clock cycles.
The SWT_CO can be used during a software self test of the SWT. For example, the SWT can be enabled
and not serviced for a fixed period of time less than the time-out value. Then the SWT can be disabled
(SWT_MCR[WEN] cleared) and the value of the SWT_CO read to determine if the internal down counter
is working properly.
MPC5644A Microcontroller Reference Manual, Rev. 6
620
Freescale Semiconductor
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