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24.4.4.2
ETPU_IDLE – eTPU Idle Register
The Idle Counter Register (ETPU_IDLE) continuously counts microcycles in which the microengine is
not busy with channel service. It can be used to measure the microengine utilization by rating the count
measured during a period of time to the number of microcycles contained in the period. The Idle counter
does not count microcycles when the engine is stopped, or is in TST or halt states.
Each eTPU2 engine has an associated ETPU_IDLE register.
Offset: eTPU_A: eTPU_Base + 0x068; eTPU_B: eTPU_Base + 0x078
0
1
R
W
Reset
0
0
16
17
R
W
Reset
0
0
= Unimplemented or Reserved
Field
0-31
IDLE_CNT[31:0]—Idle Count
This is a freerunning count of the number of idle microcycles in the microengine. For more information on
idle counter operation, see
31
ICLR—Idle Clear
This write-only bit is used to clear the idle count IDLE_CNT.
1: Clear the idle count IDLE_CNT
0: Do not clear idle count IDLE_CNT
Freescale Semiconductor
2
3
4
5
6
IDLE_CNT[31:16]
0
0
0
0
0
18
19
20
21
22
IDLE_CNT[15:0]
0
0
0
0
0
Figure 24-11. ETPU_IDLE Register
Table 24-22. ETPU_IDLE field description
Section 24.5.10.4.1, Idle
MPC5644A Microcontroller Reference Manual, Rev. 6
Enhanced Time Processing Unit (eTPU2)
7
8
9
10
11
0
0
0
0
0
23
24
25
26
27
0
0
0
0
0
Description
Counter.
Access: User read/write
12
13
14
15
0
0
0
0
28
29
30
31
ICLR
0
0
0
0
791
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