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NXP Semiconductors MK30DX128VMC7 Reference Manual (1377 pages)

K30 Sub-Family

Brand: NXP Semiconductors | Category: Controller | Size: 15 MB

Table of Contents
3
Chapter 1 About this Document

49
- Overview
  49
  - Purpose
    49
  - Audience
    49
- Conventions
  49
  - Numbering Systems
    49
  - Typographic Notation
    50
  - Special Terms
    50
Chapter 2 Introduction

51
- Overview
  51
- Module Functional Categories
  51
  - ARM Cortex-M4 Core Modules
    52
  - System Modules
    53
  - Memories and Memory Interfaces
    54
  - Clocks
    54
  - Security and Integrity Modules
    55
  - Analog Modules
    55
  - Timer Modules
    56
  - Communication Interfaces
    57
  - Human-Machine Interfaces
    57
- Orderable Part Numbers
  58
Chapter 3 Chip Configuration

59
- Introduction
  59
- Core Modules
  59
- System Modules
  69
- Clock Modules
  83
  - MCG Configuration
    83
  - OSC Configuration
    84
  - RTC OSC Configuration
    85
- Memories and Memory Interfaces
  85
  - Flash Memory Configuration
    85
    
    Freescale Semiconductor, Inc
    86
    
    Freescale Semiconductor, Inc
    87
  - Flash Memory Controller Configuration
    88
  - SRAM Configuration
    89
    
    Freescale Semiconductor, Inc
    90
    
    Freescale Semiconductor, Inc
    91
  - SRAM Controller Configuration
    92
    
    K30 Sub-Family Reference Manual, Rev. 1.1, Dec
    93
    
    VBAT Register File Configuration
    94
    
    Ezport Configuration
    95
  - Analog
    96
  - 16-Bit SAR ADC with PGA Configuration
    96
    
    Freescale Semiconductor, Inc
    97
    
    Freescale Semiconductor, Inc
    98
    
    Freescale Semiconductor, Inc
    99
    
    Freescale Semiconductor, Inc
    100
    
    Freescale Semiconductor, Inc
    101
    
    Freescale Semiconductor, Inc
    102
    
    Freescale Semiconductor, Inc
    103
    
    Freescale Semiconductor, Inc
    104
    
    Freescale Semiconductor, Inc
    105
  - CMP Configuration
    106
  - Freescale Semiconductor, Inc
    107
  - 12-Bit DAC Configuration
    108
  - VREF Configuration
    109
  - Timers
    110
  - PDB Configuration
    110
    
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    111
    
    Freescale Semiconductor, Inc
    112
  - Flextimer Configuration
    113
    
    Freescale Semiconductor, Inc
    114
    
    Freescale Semiconductor, Inc
    115
    
    Freescale Semiconductor, Inc
    116
  - PIT Configuration
    117
  - Low-Power Timer Configuration
    118
  - Freescale Semiconductor, Inc
    119
  - CMT Configuration
    120
  - RTC Configuration
    121
  - Communication Interfaces
    122
  - CAN Configuration
    122
  - Freescale Semiconductor, Inc
    123
  - SPI Configuration
    124
    
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    125
    
    Freescale Semiconductor, Inc
    126
    
    Freescale Semiconductor, Inc
    127
  - I2C Configuration
    128
  - UART Configuration
    128
    
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    129
    
    Freescale Semiconductor, Inc
    130
  - I2S Configuration
    131
    
    Freescale Semiconductor, Inc
    131
    
    Freescale Semiconductor, Inc
    132
    
    Freescale Semiconductor, Inc
    133
  - Human-Machine Interfaces
    134
  - GPIO Configuration
    134
  - TSI Configuration
    135
    
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    136
    
    Freescale Semiconductor, Inc
    137
  - Segment LCD Configuration
    138
    
    Freescale Semiconductor, Inc
    139
    
    Freescale Semiconductor, Inc
    140
  - Introduction
    141
  - System Memory Map
    141
Chapter 4 Aliased Bit-Band Regions

142
Chapter 5 Clock Distribution

155
- Introduction
  155
- Programming Model
  155
- High-Level Device Clocking Diagram
  155
- Clock Definitions
  156
- Device Clock Summary
  157
- Internal Clocking Requirements
  158
- Clock Divider Values after Reset
  159
- VLPR Mode Clocking
  159
- Clock Gating
  160
- Module Clocks
  160
- PMC 1-Khz LPO Clock
  161
  - Freescale Semiconductor, Inc
    161
  - Debug Trace Clock
    162
  - WDOG Clocking
    162
  - LPTMR Clocking
    163
  - PORT Digital Filter Clocking
    163
  - Flexcan Clocking
    164
  - I2S/SAI Clocking
    164
  - UART Clocking
    164
  - TSI Clocking
    165
- Freescale Semiconductor, Inc
  166
Chapter 6 Reset and Boot

167
- Introduction
  167
- Reset
  168
- Power-On Reset (POR)
  168
- System Reset Sources
  168
  - K30 Sub-Family Reference Manual, Rev. 1.1, Dec
    168
  - Freescale Semiconductor, Inc
    169
  - Freescale Semiconductor, Inc
    170
  - Freescale Semiconductor, Inc
    171
  - MCU Resets
    172
  - Freescale Semiconductor, Inc
    173
  - Debug Resets
    174
  - Reset Pin
    174
  - Boot
    175
  - Boot Options
    175
  - Boot Sources
    175
  - FOPT Boot Options
    176
  - Boot Sequence
    177
- Freescale Semiconductor, Inc
  178
Chapter 7 Power Management

179
- Introduction
  179
- Power Modes
  179
  - Freescale Semiconductor, Inc
    180
  - Entering and Exiting Power Modes
    181
  - Power Mode Transitions
    182
  - Module Operation in Low Power Modes
    183
  - Power Modes Shutdown Sequencing
    183
    
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    184
    
    Freescale Semiconductor, Inc
    185
  - Clock Gating
    186
Chapter 8 Security

187
- Introduction
  187
- Flash Security
  187
- Security Interactions with Other Modules
  188
- Security Interactions with Ezport
  188
- Security Interactions with Debug
  188
- Introduction
  189
  - K30 Sub-Family Reference Manual, Rev. 1.1, Dec
    189
  - Freescale Semiconductor, Inc
    190
Chapter 9 References

191
- The Debug Port
  191
- JTAG-To-SWD Change Sequence
  192
- JTAG-To-Cjtag Change Sequence
  192
- Debug Port Pin Descriptions
  193
- System TAP Connection
  193
- IR Codes
  194
- JTAG Status and Control Registers
  194
- MDM-AP Control Register
  195
  - Freescale Semiconductor, Inc
    196
  - MDM-AP Status Register
    197
  - Debug Resets
    198
  - Ahb-Ap
    199
  - Core Trace Connectivity
    200
  - Dwt
    200
  - Itm
    200
  - Tpiu
    200
  - Debug in Low Power Modes
    201
  - Debug & Security
    202
  - Debug Module State in Low Power Modes
    202
Chapter 10 Signal Multiplexing and Signal Descriptions

203
- Introduction
  203
- Signal Multiplexing Integration
  203
- Port Control and Interrupt Module Features
  204
- Pcrn Reset Values for Port a
  204
- Clock Gating
  204
- Signal Multiplexing Constraints
  204
- Pinout
  205
- K30 Signal Multiplexing and Pin Assignments
  205
  - K30 Sub-Family Reference Manual, Rev. 1.1, Dec
    205
  - Freescale Semiconductor, Inc
    206
  - Freescale Semiconductor, Inc
    207
  - Freescale Semiconductor, Inc
    208
  - Freescale Semiconductor, Inc
    209
  - K30 Pinouts
    210
  - Freescale Semiconductor, Inc
    211
  - Module Signal Description Tables
    212
  - Core Modules
    213
  - Clock Modules
    214
  - System Modules
    214
  - Analog
    215
  - Memories and Memory Interfaces
    215
  - Freescale Semiconductor, Inc
    216
  - Timer Modules
    217
  - Communication Interfaces
    218
    
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    219
    
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    220
  - Human-Machine Interfaces (HMI)
    221
- Freescale Semiconductor, Inc
  222
Chapter 11 Port Control and Interrupts (PORT)

223
- Introduction
  223
- Overview
  223
- External Signal Description
  224
- Detailed Signal Description
  225
- Memory Map and Register Definition
  225
  - Freescale Semiconductor, Inc
    226
  - Freescale Semiconductor, Inc
    227
  - Freescale Semiconductor, Inc
    228
  - Freescale Semiconductor, Inc
    229
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    230
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    231
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    232
  - Freescale Semiconductor, Inc
    233
  - Freescale Semiconductor, Inc
    234
  - Functional Description
    235
  - Freescale Semiconductor, Inc
    236
  - Freescale Semiconductor, Inc
    237
  - Freescale Semiconductor, Inc
    238
Chapter 12 System Integration Module (SIM)

239
Chapter 13

273
- System Reset Status Register 1 (RCM_SRS1)
  273
- Reset Pin Filter Control Register (RCM_RPFC)
  274
- Reset Pin Filter Width Register (RCM_RPFW)
  275
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    276
  - Mode Register (RCM_MR)
    277
    
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    278
    
    Introduction
    279
    
    Freescale Semiconductor, Inc
    280
  - Memory Map and Register Descriptions
    281
- Freescale Semiconductor, Inc
  282
Chapter 14

283
- Power Mode Control Register (SMC_PMCTRL)
  283
- VLLS Control Register (SMC_VLLSCTRL)
  284
- Power Mode Status Register (SMC_PMSTAT)
  285
  - Functional Description
    286
  - Freescale Semiconductor, Inc
    287
  - Freescale Semiconductor, Inc
    288
  - Power Mode Entry/Exit Sequencing
    289
  - Freescale Semiconductor, Inc
    290
  - Run Modes
    291
  - Freescale Semiconductor, Inc
    292
  - Wait Modes
    293
  - Stop Modes
    294
  - Freescale Semiconductor, Inc
    295
  - Freescale Semiconductor, Inc
    296
  - Debug in Low Power Modes
    297
  - Freescale Semiconductor, Inc
    298
  - Introduction
    299
Chapter 15 LVD Reset Operation

300
- I/O Retention
  301
  - Freescale Semiconductor, Inc
    302
  - Low Voltage Detect Status and Control 2 Register (PMC_LVDSC2)
    303
  - Regulator Status and Control Register (PMC_REGSC)
    304
    
    K30 Sub-Family Reference Manual, Rev. 1.1, Dec
    305
    
    Freescale Semiconductor, Inc
    306
  - Introduction
    307
  - Modes of Operation
    308
  - Block Diagram
    309
  - LLWU Signal Descriptions
    310
  - Memory Map/Register Definition
    311
  - LLWU Pin Enable 1 Register (LLWU_PE1)
    312
  - LLWU Pin Enable 2 Register (LLWU_PE2)
    313
  - LLWU Pin Enable 3 Register (LLWU_PE3)
    314
  - LLWU Pin Enable 4 Register (LLWU_PE4)
    315
  - LLWU Module Enable Register (LLWU_ME)
    316
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    317
  - LLWU Flag 1 Register (LLWU_F1)
    318
  - LLWU Flag 2 Register (LLWU_F2)
    319
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    320
  - LLWU Flag 3 Register (LLWU_F3)
    321
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    322
  - LLWU Pin Filter 1 Register (LLWU_FILT1)
    323
  - LLWU Pin Filter 2 Register (LLWU_FILT2)
    324
  - LLWU Reset Enable Register (LLWU_RST)
    325
  - Functional Description
    326
  - LLS Mode
    326
  - Initialization
    327
  - VLLS Modes
    327
- Freescale Semiconductor, Inc
  328
Chapter 17 Miscellaneous Control Module (MCM)

329
- Introduction
  329
- Features
  329
- Memory Map/Register Descriptions
  329
- Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)
  330
- Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)
  330
- Control Register (MCM_CR)
  331
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    331
  - Freescale Semiconductor, Inc
    332
Chapter 18 Crossbar Switch (AXBS)

333
- Introduction
  333
- Features
  333
- Memory Map / Register Definition
  334
- Priority Registers Slave (Axbs_Prsn)
  335
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    336
  - Freescale Semiconductor, Inc
    337
  - Control Register (Axbs_Crsn)
    338
  - Freescale Semiconductor, Inc
    339
  - Functional Description
    340
  - General Operation
    340
  - Master General Purpose Control Register (Axbs_Mgpcrn)
    340
  - Register Coherency
    341
  - Arbitration
    342
    
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    343
    
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    344
  - Initialization/Application Information
    345
- Freescale Semiconductor, Inc
  346
Chapter 19 Peripheral Bridge (AIPS-Lite)

347
- Introduction
  347
- Features
  347
- General Operation
  348
- Memory Map/Register Definition
  348
  - Freescale Semiconductor, Inc
    349
  - Master Privilege Register a (Aipsx_Mpra)
    350
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    351
  - Peripheral Access Control Register (Aipsx_Pacrn)
    352
    
    Freescale Semiconductor, Inc
    353
    
    Freescale Semiconductor, Inc
    354
    
    Freescale Semiconductor, Inc
    355
    
    Freescale Semiconductor, Inc
    356
  - Peripheral Access Control Register (Aipsx_Pacrn)
    357
    
    Freescale Semiconductor, Inc
    358
    
    Freescale Semiconductor, Inc
    359
    
    Freescale Semiconductor, Inc
    360
    
    Freescale Semiconductor, Inc
    361
  - Access Support
    362
  - Functional Description
    362
Chapter 20 Direct Memory Access Multiplexer (DMAMUX)

363
- Introduction
  363
- Overview
  363
- Features
  364
- Modes of Operation
  364
  - K30 Sub-Family Reference Manual, Rev. 1.1, Dec
    364
  - External Signal Description
    365
  - Memory Map/Register Definition
    365
  - Channel Configuration Register (Dmamux_Chcfgn)
    366
  - DMA Channels with Periodic Triggering Capability
    367
  - Functional Description
    367
  - Freescale Semiconductor, Inc
    368
  - Always Enabled" DMA Sources
    369
  - DMA Channels with no Triggering Capability
    369
  - Initialization/Application Information
    370
  - Enabling and Configuring Sources
    371
  - Reset
    371
  - Freescale Semiconductor, Inc
    372
  - Freescale Semiconductor, Inc
    373
  - Freescale Semiconductor, Inc
    374
Chapter 21 Direct Memory Access Controller (Edma)

375
- Introduction
  375
- Block Diagram
  375
- Block Parts
  376
Chapter 22 External Watchdog Monitor (EWM)

453
- Introduction
  453
- Features
  453
- Modes of Operation
  454
- Block Diagram
  455
- EWM Signal Descriptions
  456
- Memory Map/Register Definition
  456
- Control Register (EWM_CTRL)
  456
- Service Register (EWM_SERV)
  457
- Compare Low Register (EWM_CMPL)
  457
- Compare High Register (EWM_CMPH)
  458
- Functional Description
  459
- The Ewm_Out Signal
  459
- The Ewm_In Signal
  459
- EWM Counter
  460
- EWM Compare Registers
  460
- EWM Refresh Mechanism
  461
- EWM Interrupt
  461
- K30 Sub-Family Reference Manual, Rev. 1.1, Dec
  462
Chapter 23 Watchdog Timer (WDOG)

463
- Introduction
  463
- Features
  463
Chapter 24 Multipurpose Clock Generator (MCG)

485
- Introduction
  485
- Features
  485
  - Freescale Semiconductor, Inc
    486
  - Freescale Semiconductor, Inc
    487
  - Freescale Semiconductor, Inc
    488
  - External Signal Description
    489
  - Memory Map/Register Definition
    489
  - Modes of Operation
    489
  - MCG Control 1 Register (MCG_C1)
    490
  - MCG Control 2 Register (MCG_C2)
    491
  - MCG Control 3 Register (MCG_C3)
    492
  - MCG Control 4 Register (MCG_C4)
    493
  - MCG Control 5 Register (MCG_C5)
    494
  - MCG Control 6 Register (MCG_C6)
    495
  - Freescale Semiconductor, Inc
    496
  - MCG Status Register (MCG_S)
    497
  - MCG Status and Control Register (MCG_SC)
    498
  - Freescale Semiconductor, Inc
    499
  - MCG Auto Trim Compare Value High Register (MCG_ATCVH)
    500
  - MCG Auto Trim Compare Value Low Register (MCG_ATCVL)
    500
  - MCG Control 7 Register (MCG_C7)
    500
  - MCG Control 8 Register (MCG_C8)
    501
  - Functional Description
    502
  - MCG Mode State Diagram
    502
    
    Freescale Semiconductor, Inc
    503
    
    Freescale Semiconductor, Inc
    504
    
    Freescale Semiconductor, Inc
    505
    
    Freescale Semiconductor, Inc
    506
  - External Reference Clock
    507
  - Low Power Bit Usage
    507
  - MCG Internal Reference Clocks
    507
  - K30 Sub-Family Reference Manual, Rev. 1.1, Dec
    508
  - MCG Fixed Frequency Clock
    508
  - MCG PLL Clock
    508
  - MCG Auto TRIM (ATM)
    509
  - Initialization / Application Information
    510
  - MCG Module Initialization Sequence
    510
  - Freescale Semiconductor, Inc
    511
  - Using a 32.768 Khz Reference
    512
  - MCG Mode Switching
    513
  - Freescale Semiconductor, Inc
    514
  - Freescale Semiconductor, Inc
    515
  - Freescale Semiconductor, Inc
    516
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    517
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    518
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    519
  - Freescale Semiconductor, Inc
    520
  - Freescale Semiconductor, Inc
    521
  - Freescale Semiconductor, Inc
    522
Chapter 25 Oscillator (OSC)

523
- Introduction
  523
- Features and Modes
  523
- Block Diagram
  524
- OSC Signal Descriptions
  524
- External Crystal / Resonator Connections
  525
- External Clock Connections
  526
- Memory Map/Register Definitions
  527
- OSC Memory Map/Register Definition
  527
- Functional Description
  528
- OSC Module States
  529
- OSC Module Modes
  530
  - Freescale Semiconductor, Inc
    531
  - Counter
    532
  - Reference Clock Pin Requirements
    532
  - Reset
    532
  - Interrupts
    533
  - Low Power Modes Operation
    533
- K30 Sub-Family Reference Manual, Rev. 1.1, Dec
  534
Chapter 26 RTC Oscillator

535
- Introduction
  535
- Features and Modes
  535
- Block Diagram
  535
- RTC Signal Descriptions
  536
- EXTAL32 - Oscillator Input
  536
- XTAL32 - Oscillator Output
  536
- External Crystal Connections
  537
- Memory Map/Register Descriptions
  537
- Functional Description
  537
- Reset Overview
  538
- Interrupts
  538
Chapter 27 Flash Memory Controller (FMC)

539
- Introduction
  539
- Overview
  539
- Features
  540
- Modes of Operation
  540
- External Signal Description
  540
- Memory Map and Register Descriptions
  541
Chapter 28 Flash Memory Module (FTFL)

563
- Introduction
  563
- Features
  564
- Block Diagram
  565
- Glossary
  566
  - Freescale Semiconductor, Inc
    567
  - External Signal Description
    568
  - Memory Map and Registers
    568
  - Flash Configuration Field Description
    569
  - Program Flash IFR Map
    569
  - Data Flash IFR Map
    570
  - Freescale Semiconductor, Inc
    571
  - Register Descriptions
    572
    
    Freescale Semiconductor, Inc
    573
    
    Freescale Semiconductor, Inc
    574
    
    Freescale Semiconductor, Inc
    575
    
    Freescale Semiconductor, Inc
    576
    
    Freescale Semiconductor, Inc
    577
    
    Freescale Semiconductor, Inc
    578
    
    Freescale Semiconductor, Inc
    579
    
    Freescale Semiconductor, Inc
    580
    
    Freescale Semiconductor, Inc
    581
    
    Freescale Semiconductor, Inc
    582
    
    Freescale Semiconductor, Inc
    583
  - Flash Protection
    584
  - Functional Description
    584
  - Freescale Semiconductor, Inc
    585
  - Flexnvm Description
    586
    
    Freescale Semiconductor, Inc
    587
    
    Freescale Semiconductor, Inc
    588
  - Interrupts
    589
  - Flash Operation in Low-Power Modes
    590
  - Flash Reads and Ignored Writes
    590
  - Functional Modes of Operation
    590
  - K30 Sub-Family Reference Manual, Rev. 1.1, Dec
    590
  - Flash Command Operations
    591
  - Flash Program and Erase
    591
  - Read While Write (RWW)
    591
    
    Freescale Semiconductor, Inc
    592
    
    Freescale Semiconductor, Inc
    593
    
    Freescale Semiconductor, Inc
    594
    
    Freescale Semiconductor, Inc
    595
    
    Freescale Semiconductor, Inc
    596
    
    Freescale Semiconductor, Inc
    597
  - Margin Read Commands
    598
  - Flash Command Description
    599
    
    Freescale Semiconductor, Inc
    600
    
    Freescale Semiconductor, Inc
    601
    
    Freescale Semiconductor, Inc
    602
    
    Freescale Semiconductor, Inc
    603
    
    Freescale Semiconductor, Inc
    604
    
    Freescale Semiconductor, Inc
    605
    
    Freescale Semiconductor, Inc
    606
    
    Freescale Semiconductor, Inc
    607
    
    Freescale Semiconductor, Inc
    608
    
    Freescale Semiconductor, Inc
    609
    
    Freescale Semiconductor, Inc
    610
    
    Freescale Semiconductor, Inc
    611
    
    Freescale Semiconductor, Inc
    612
    
    Freescale Semiconductor, Inc
    613
    
    Freescale Semiconductor, Inc
    614
    
    Freescale Semiconductor, Inc
    615
    
    Freescale Semiconductor, Inc
    616
    
    Freescale Semiconductor, Inc
    617
    
    Freescale Semiconductor, Inc
    618
    
    Freescale Semiconductor, Inc
    619
  - Security
    620
  - Freescale Semiconductor, Inc
    621
  - Reset Sequence
    622
    
    Freescale Semiconductor, Inc
    623
    
    Freescale Semiconductor, Inc
    624
  - Overview
    625
Chapter 29

625
- Introduction
  625
- Features
  626
- Modes of Operation
  626
- External Signal Description
  627
- Ezport Clock (EZP_CK)
  627
- Ezport Chip Select (EZP_CS)
  627
- Ezport Serial Data in (EZP_D)
  628
- Ezport Serial Data out (EZP_Q)
  628
- Command Definition
  628
- Command Descriptions
  629
  - Freescale Semiconductor, Inc
    630
  - Freescale Semiconductor, Inc
    631
  - Freescale Semiconductor, Inc
    632
  - Freescale Semiconductor, Inc
    633
  - Freescale Semiconductor, Inc
    634
  - Flash Memory Map for Ezport Access
    635
- Freescale Semiconductor, Inc
  636
Chapter 30 Cyclic Redundancy Check (CRC)

637
- Introduction
  637
- Features
  637
- Block Diagram
  638
  - K30 Sub-Family Reference Manual, Rev. 1.1, Dec
    639
  - CRC Polynomial Register (CRC_GPOLY)
    640
  - Functional Description
    641
  - CRC Initialization/Reinitialization
    642
  - Transpose Feature
    643
  - Freescale Semiconductor, Inc
    644
  - CRC Result Complement
    645
  - Freescale Semiconductor, Inc
    646
  - Introduction
    647
  - Block Diagram
    648
Chapter 31 ADC Signal Descriptions

649
- Voltage Reference Select
  650
- Analog Channel Inputs (Adx)
  651
Chapter 32

702
- Bit DAC Key Features
  702
- ANMUX Key Features
  703
- CMP Block Diagram
  704
  - Freescale Semiconductor, Inc
    705
  - Memory Map/Register Definitions
    706
  - CMP Control Register 1 (Cmpx_Cr1)
    707
  - Freescale Semiconductor, Inc
    708
  - CMP Filter Period Register (Cmpx_Fpr)
    709
  - DAC Control Register (Cmpx_Daccr)
    710
  - MUX Control Register (Cmpx_Muxcr)
    711
  - CMP Functional Description
    712
    
    Freescale Semiconductor, Inc
    713
    
    Freescale Semiconductor, Inc
    714
    
    Freescale Semiconductor, Inc
    715
    
    Freescale Semiconductor, Inc
    716
    
    Freescale Semiconductor, Inc
    717
    
    Freescale Semiconductor, Inc
    718
    
    Freescale Semiconductor, Inc
    719
    
    Freescale Semiconductor, Inc
    720
  - Power Modes
    721
  - Startup and Operation
    722
  - Low-Pass Filter
    723
  - Freescale Semiconductor, Inc
    724
  - CMP Interrupts
    725
  - K30 Sub-Family Reference Manual, Rev. 1.1, Dec
    726
  - DAC Resets
    727
  - Freescale Semiconductor, Inc
    728
  - Introduction
    729
  - Memory Map/Register Definition
    730
Chapter 33

731
- DAC Data Low Register (Dacx_Datnl)
  731
- DAC Status Register (Dacx_Sr)
  732
- DAC Control Register (Dacx_C0)
  733
- DAC Control Register 1 (Dacx_C1)
  734
- DAC Control Register 2 (Dacx_C2)
  735
- DAC Data Buffer Operation
  736
- DMA Operation
  737
  - Freescale Semiconductor, Inc
    738
  - Introduction
    739
  - Overview
    740
  - Modes of Operation
    741
  - K30 Sub-Family Reference Manual, Rev. 1.1, Dec
    742
  - VREF Status and Control Register (VREF_SC)
    743
  - Functional Description
    744
  - Voltage Reference Enabled, SC[VREFEN] = 1
    745
  - Initialization/Application Information
    746
  - Introduction
    747
Chapter 35

748
- Implementation
  748
- Back-To-Back Acknowledgment Connections
  749
  - Freescale Semiconductor, Inc
    750
  - Modes of Operation
    751
  - Freescale Semiconductor, Inc
    752
  - Status and Control Register (Pdbx_Sc)
    753
  - Freescale Semiconductor, Inc
    754
  - Modulus Register (Pdbx_Mod)
    755
  - Counter Register (Pdbx_Cnt)
    756
  - Channel N Control Register 1 (Pdbx_Chnc1)
    757
  - Channel N Status Register (Pdbx_Chns)
    758
  - Channel N Delay 1 Register (Pdbx_Chndly1)
    759
  - DAC Interval N Register (Pdbx_Dacintn)
    760
    
    K30 Sub-Family Reference Manual, Rev. 1.1, Dec
    761
    
    Freescale Semiconductor, Inc
    762
  - PDB Trigger Input Source Selection
    763
  - Pulse-Out's
    764
  - Updating the Delay Registers
    765
  - Interrupts
    766
  - Application Information
    767
  - Freescale Semiconductor, Inc
    768
  - Introduction
    769
  - Features
    770
  - Modes of Operation
    771
  - Block Diagram
    772
  - Freescale Semiconductor, Inc
    773
Chapter 36 FTM Signal Descriptions

774
- Register Descriptions
  775
- Freescale Semiconductor, Inc
  776
- Freescale Semiconductor, Inc
  777
- Freescale Semiconductor, Inc
  778
- Freescale Semiconductor, Inc
  779
- Status and Control (Ftmx_Sc)
  780
- Counter (Ftmx_Cnt)
  781
- Modulo (Ftmx_Mod)
  782
- Channel (N) Status and Control (Ftmx_Cnsc)
  783
  - Freescale Semiconductor, Inc
    784
  - Channel (N) Value (Ftmx_Cnv)
    785
  - Counter Initial Value (Ftmx_Cntin)
    786
    
    K30 Sub-Family Reference Manual, Rev. 1.1, Dec
    787
    
    Features Mode Selection (Ftmx_Mode)
    788
    
    Freescale Semiconductor, Inc
    789
  - Synchronization (Ftmx_Sync)
    790
    
    Freescale Semiconductor, Inc
    791
    
    Freescale Semiconductor, Inc
    792
  - Initial State for Channels Output (Ftmx_Outinit)
    793
    
    Output Mask (Ftmx_Outmask)
    794
    
    Freescale Semiconductor, Inc
    795
  - Function for Linked Channels (Ftmx_Combine)
    796
    
    Freescale Semiconductor, Inc
    797
    
    Freescale Semiconductor, Inc
    798
    
    Freescale Semiconductor, Inc
    799
    
    Freescale Semiconductor, Inc
    800
    
    Deadtime Insertion Control (Ftmx_Deadtime)
    801
  - FTM External Trigger (Ftmx_Exttrig)
    802
  - Channels Polarity (Ftmx_Pol)
    803
    
    Freescale Semiconductor, Inc
    804
    
    Freescale Semiconductor, Inc
    805
  - Fault Mode Status (Ftmx_Fms)
    806
  - Freescale Semiconductor, Inc
    807
  - Input Capture Filter Control (Ftmx_Filter)
    808
    
    Fault Control (Ftmx_Fltctrl)
    809
    
    Freescale Semiconductor, Inc
    810
  - Quadrature Decoder Control and Status (Ftmx_Qdctrl)
    811
  - Freescale Semiconductor, Inc
    812
  - Configuration (Ftmx_Conf)
    813
  - FTM Fault Input Polarity (Ftmx_Fltpol)
    814
  - Freescale Semiconductor, Inc
    815
  - Synchronization Configuration (Ftmx_Synconf)
    816
  - Freescale Semiconductor, Inc
    817
  - FTM Inverting Control (Ftmx_Invctrl)
    818
  - FTM Software Output Control (Ftmx_Swoctrl)
    819
  - Freescale Semiconductor, Inc
    820
  - FTM PWM Load (Ftmx_Pwmload)
    821
  - Functional Description
    822
  - Clock Source
    823
  - Prescaler
    824
    
    Freescale Semiconductor, Inc
    825
    
    Freescale Semiconductor, Inc
    826
    
    Freescale Semiconductor, Inc
    827
    
    Freescale Semiconductor, Inc
    828
  - Input Capture Mode
    829
    
    Freescale Semiconductor, Inc
    830
    
    Freescale Semiconductor, Inc
    831
  - Output Compare Mode
    832
  - Edge-Aligned PWM (EPWM) Mode
    833
  - Freescale Semiconductor, Inc
    834
  - Center-Aligned PWM (CPWM) Mode
    835
  - Freescale Semiconductor, Inc
    836
  - Combine Mode
    837
    
    Freescale Semiconductor, Inc
    838
    
    Freescale Semiconductor, Inc
    839
    
    Freescale Semiconductor, Inc
    840
    
    Freescale Semiconductor, Inc
    841
    
    Freescale Semiconductor, Inc
    842
    
    Freescale Semiconductor, Inc
    843
    
    Freescale Semiconductor, Inc
    844
  - Complementary Mode
    845
    
    K30 Sub-Family Reference Manual, Rev. 1.1, Dec
    846
    
    Freescale Semiconductor, Inc
    847
  - PWM Synchronization
    848
    
    Freescale Semiconductor, Inc
    849
    
    Freescale Semiconductor, Inc
    850
    
    Freescale Semiconductor, Inc
    851
    
    Freescale Semiconductor, Inc
    852
    
    Freescale Semiconductor, Inc
    853
    
    Freescale Semiconductor, Inc
    854
    
    Freescale Semiconductor, Inc
    855
    
    Freescale Semiconductor, Inc
    856
    
    Freescale Semiconductor, Inc
    857
    
    Freescale Semiconductor, Inc
    858
    
    Freescale Semiconductor, Inc
    859
    
    Freescale Semiconductor, Inc
    860
    
    Freescale Semiconductor, Inc
    861
    
    Freescale Semiconductor, Inc
    862
    
    Freescale Semiconductor, Inc
    863
  - Inverting
    864
  - Software Output Control
    865
  - Freescale Semiconductor, Inc
    866
  - Deadtime Insertion
    867
    
    Freescale Semiconductor, Inc
    868
    
    Freescale Semiconductor, Inc
    869
  - Output Mask
    870
  - Fault Control
    871
    
    Freescale Semiconductor, Inc
    872
    
    Freescale Semiconductor, Inc
    873
  - Polarity Control
    874
  - Initialization
    875
  - Channel Trigger Output
    876
  - Initialization Trigger
    877
  - Freescale Semiconductor, Inc
    878
  - Capture Test Mode
    879
  - Freescale Semiconductor, Inc
    880
  - Dual Edge Capture Mode
    881
    
    Freescale Semiconductor, Inc
    882
    
    Freescale Semiconductor, Inc
    883
    
    Freescale Semiconductor, Inc
    884
    
    Freescale Semiconductor, Inc
    885
    
    Freescale Semiconductor, Inc
    886
    
    Freescale Semiconductor, Inc
    887
  - Quadrature Decoder Mode
    888
    
    Freescale Semiconductor, Inc
    889
    
    Freescale Semiconductor, Inc
    890
    
    Freescale Semiconductor, Inc
    891
    
    Freescale Semiconductor, Inc
    892
  - BDM Mode
    893
  - Intermediate Load
    894
  - Freescale Semiconductor, Inc
    895
  - Global Time Base (GTB)
    896
    
    Reset Overview
    897
    
    Freescale Semiconductor, Inc
    898
  - FTM Interrupts
    899
  - Freescale Semiconductor, Inc
    900
  - Introduction
    901
Chapter 16

902
- Features
  902
  - K30 Sub-Family Reference Manual, Rev. 1.1, Dec
    903
  - Timer Load Value Register (Pit_Ldvaln)
    904
  - Current Timer Value Register (Pit_Cvaln)
    905
  - Timer Flag Register (Pit_Tflgn)
    906
    
    Functional Description
    907
    
    Interrupts
    908
  - Chained Timers
    909
  - Example Configuration for Chained Timers
    910
- Introduction
  911
Chapter 38 LPTMR Signal Descriptions

912
Chapter 49

921
- Introduction
  921
  - Block Diagram
    922
  - Modes of Operation
    923
Chapter 39

924
- Wait Mode Operation
  924
- Stop Mode Operation
  925
Chapter 40

949
- RTC Time Seconds Register (RTC_TSR)
  949
- RTC Time Prescaler Register (RTC_TPR)
  950
  - Freescale Semiconductor, Inc
    951
  - RTC Control Register (RTC_CR)
    952
  - Freescale Semiconductor, Inc
    953
  - RTC Status Register (RTC_SR)
    954
  - RTC Lock Register (RTC_LR)
    955
  - RTC Interrupt Enable Register (RTC_IER)
    956
  - RTC Write Access Register (RTC_WAR)
    957
  - RTC Read Access Register (RTC_RAR)
    958
  - Functional Description
    959
  - Power, Clocking, and Reset
    960
  - Time Counter
    961
  - Time Alarm
    962
  - K30 Sub-Family Reference Manual, Rev. 1.1, Dec
    963
  - Freescale Semiconductor, Inc
    964
  - Introduction
    965
  - Overview
    966
Chapter 41 Flexcan Module Features

967
- Modes of Operation
  968
  - Freescale Semiconductor, Inc
    969
  - Flexcan Signal Descriptions
    970
    
    Freescale Semiconductor, Inc
    971
    
    Freescale Semiconductor, Inc
    972
    
    Freescale Semiconductor, Inc
    973
  - Module Configuration Register (Canx_Mcr)
    974
    
    Freescale Semiconductor, Inc
    975
    
    Freescale Semiconductor, Inc
    976
    
    Freescale Semiconductor, Inc
    977
    
    Freescale Semiconductor, Inc
    978
  - Control 1 Register (Canx_Ctrl1)
    979
    
    Freescale Semiconductor, Inc
    980
    
    Freescale Semiconductor, Inc
    981
  - Free Running Timer (Canx_Timer)
    982
  - Rx Mailboxes Global Mask Register (Canx_Rxmgmask)
    983
  - Rx 14 Mask Register (Canx_Rx14Mask)
    984
  - Rx 15 Mask Register (Canx_Rx15Mask)
    985
  - Freescale Semiconductor, Inc
    986
  - Error and Status 1 Register (Canx_Esr1)
    987
    
    Freescale Semiconductor, Inc
    988
    
    Freescale Semiconductor, Inc
    989
    
    Freescale Semiconductor, Inc
    990
  - Interrupt Masks 1 Register (Canx_Imask1)
    991
  - Interrupt Flags 1 Register (Canx_Iflag1)
    992
  - Freescale Semiconductor, Inc
    993
  - Control 2 Register (Canx_Ctrl2)
    994
    
    Freescale Semiconductor, Inc
    995
    
    Freescale Semiconductor, Inc
    996
  - Error and Status 2 Register (Canx_Esr2)
    997
  - CRC Register (Canx_Crcr)
    998
  - Rx FIFO Global Mask Register (Canx_Rxfgmask)
    999
  - Rx FIFO Information Register (Canx_Rxfir)
    1000
  - K30 Sub-Family Reference Manual, Rev. 1.1, Dec
    1001
  - Message Buffer Structure
    1002
    
    Freescale Semiconductor, Inc
    1003
    
    Freescale Semiconductor, Inc
    1004
    
    Freescale Semiconductor, Inc
    1005
    
    Freescale Semiconductor, Inc
    1006
    
    Freescale Semiconductor, Inc
    1007
  - Rx FIFO Structure
    1008
  - Freescale Semiconductor, Inc
    1009
  - Functional Description
    1010
  - Transmit Process
    1011
    
    Freescale Semiconductor, Inc
    1012
    
    Freescale Semiconductor, Inc
    1013
    
    Freescale Semiconductor, Inc
    1014
  - Receive Process
    1015
  - Freescale Semiconductor, Inc
    1016
  - Matching Process
    1017
    
    Freescale Semiconductor, Inc
    1018
    
    Freescale Semiconductor, Inc
    1019
    
    Freescale Semiconductor, Inc
    1020
    
    Freescale Semiconductor, Inc
    1021
  - Move Process
    1022
  - Data Coherence
    1023
    
    Freescale Semiconductor, Inc
    1024
    
    Freescale Semiconductor, Inc
    1025
    
    Freescale Semiconductor, Inc
    1026
  - Rx FIFO
    1027
  - CAN Protocol Related Features
    1028
    
    Freescale Semiconductor, Inc
    1029
    
    Freescale Semiconductor, Inc
    1030
    
    Freescale Semiconductor, Inc
    1031
    
    Freescale Semiconductor, Inc
    1032
    
    Freescale Semiconductor, Inc
    1033
    
    Freescale Semiconductor, Inc
    1034
  - Clock Domains and Restrictions
    1035
  - Freescale Semiconductor, Inc
    1036
  - Freescale Semiconductor, Inc
    1037
  - Freescale Semiconductor, Inc
    1038
  - Interrupts
    1039
  - Initialization/Application Information
    1040
  - Freescale Semiconductor, Inc
    1041
  - Freescale Semiconductor, Inc
    1042
  - Introduction
    1043
  - Features
    1044
  - Freescale Semiconductor, Inc
    1045
Chapter 42

1046
- Module Configurations
  1046
  - Freescale Semiconductor, Inc
    1047
  - Module Signal Descriptions
    1048
    
    PCS4 — Peripheral Chip Select 4
    1049
    
    K30 Sub-Family Reference Manual, Rev. 1.1, Dec
    1050
    
    Freescale Semiconductor, Inc
    1051
  - Module Configuration Register (Spix_Mcr)
    1052
    
    Freescale Semiconductor, Inc
    1053
    
    Freescale Semiconductor, Inc
    1054
  - DSPI Transfer Count Register (Spix_Tcr)
    1055
    
    Freescale Semiconductor, Inc
    1056
    
    Freescale Semiconductor, Inc
    1057
    
    Freescale Semiconductor, Inc
    1058
    
    Freescale Semiconductor, Inc
    1059
  - DSPI Clock and Transfer Attributes Register (in Slave Mode) (Spix_Ctarn_Slave)
    1060
  - Freescale Semiconductor, Inc
    1061
  - DSPI Status Register (Spix_Sr)
    1062
    
    Freescale Semiconductor, Inc
    1063
    
    Freescale Semiconductor, Inc
    1064
  - DSPI Dma/Interrupt Request Select and Enable Register (Spix_Rser)
    1065
  - Freescale Semiconductor, Inc
    1066
  - DSPI PUSH TX FIFO Register in Master Mode (Spix_Pushr)
    1067
  - Freescale Semiconductor, Inc
    1068
  - DSPI PUSH TX FIFO Register in Slave Mode (Spix_Pushr_Slave)
    1069
  - DSPI Transmit FIFO Registers (Spix_Txfrn)
    1070
  - Functional Description
    1071
  - Start and Stop of Module Transfers
    1072
  - Serial Peripheral Interface (SPI) Configuration
    1073
    
    Freescale Semiconductor, Inc
    1074
    
    Freescale Semiconductor, Inc
    1075
  - Module Baud Rate and Clock Delay Generation
    1076
  - Freescale Semiconductor, Inc
    1077
  - Transfer Formats
    1078
    
    Freescale Semiconductor, Inc
    1079
    
    Freescale Semiconductor, Inc
    1080
    
    Freescale Semiconductor, Inc
    1081
    
    Freescale Semiconductor, Inc
    1082
  - Continuous Serial Communications Clock
    1083
  - Freescale Semiconductor, Inc
    1084
  - Slave Mode Operation Constraints
    1085
    
    Freescale Semiconductor, Inc
    1086
    
    Freescale Semiconductor, Inc
    1087
  - Power Saving Features
    1088
  - Initialization/Application Information
    1089
  - Switching Master and Slave Mode
    1090
  - K30 Sub-Family Reference Manual, Rev. 1.1, Dec
    1091
  - Calculation of FIFO Pointer Addresses
    1092
  - Freescale Semiconductor, Inc
    1093
  - Freescale Semiconductor, Inc
    1094
  - Introduction
    1095
  - Modes of Operation
    1096
  - Memory Map and Register Descriptions
    1097
Chapter 43

1098
- I2C Address Register 1 (I2Cx_A1)
  1098
- I2C Frequency Divider Register (I2Cx_F)
  1099
- I2C Control Register 1 (I2Cx_C1)
  1100
  - Freescale Semiconductor, Inc
    1101
  - I2C Status Register (I2Cx_S)
    1102
  - I2C Data I/O Register (I2Cx_D)
    1103
  - I2C Control Register 2 (I2Cx_C2)
    1104
  - I2C Programmable Input Glitch Filter Register (I2Cx_Flt)
    1105
  - I2C Range Address Register (I2Cx_Ra)
    1106
  - Freescale Semiconductor, Inc
    1107
  - I2C Address Register 2 (I2Cx_A2)
    1108
  - I2C SCL Low Timeout Register Low (I2Cx_Sltl)
    1109
    
    Freescale Semiconductor, Inc
    1110
    
    Freescale Semiconductor, Inc
    1111
    
    Freescale Semiconductor, Inc
    1112
    
    Freescale Semiconductor, Inc
    1113
  - Bit Address
    1114
  - Freescale Semiconductor, Inc
    1115
  - Address Matching
    1116
  - System Management Bus Specification
    1117
    
    Freescale Semiconductor, Inc
    1118
    
    Resets
    1119
    
    K30 Sub-Family Reference Manual, Rev. 1.1, Dec
    1120
  - Programmable Input Glitch Filter
    1121
    
    Address Matching Wakeup
    1122
    
    Initialization/Application Information
    1123
    
    Freescale Semiconductor, Inc
    1124
    
    Freescale Semiconductor, Inc
    1125
    
    Freescale Semiconductor, Inc
    1126
    
    Introduction
    1127
    
    Freescale Semiconductor, Inc
    1128
    
    Modes of Operation
    1129
  - UART Signal Descriptions
    1130
Chapter 44

1131
- Detailed Signal Descriptions
  1131
- Memory Map and Registers
  1132
  - Freescale Semiconductor, Inc
    1133
  - Freescale Semiconductor, Inc
    1134
  - Freescale Semiconductor, Inc
    1135
  - Freescale Semiconductor, Inc
    1136
  - Freescale Semiconductor, Inc
    1137
  - Freescale Semiconductor, Inc
    1138
  - Freescale Semiconductor, Inc
    1139
  - Freescale Semiconductor, Inc
    1140
  - Freescale Semiconductor, Inc
    1141
  - UART Baud Rate Registers: High (Uartx_Bdh)
    1142
  - UART Baud Rate Registers: Low (Uartx_Bdl)
    1143
  - UART Control Register 1 (Uartx_C1)
    1144
  - UART Control Register 2 (Uartx_C2)
    1145
  - Freescale Semiconductor, Inc
    1146
  - UART Status Register 1 (Uartx_S1)
    1147
    
    Freescale Semiconductor, Inc
    1148
    
    Freescale Semiconductor, Inc
    1149
  - UART Status Register 2 (Uartx_S2)
    1150
  - Freescale Semiconductor, Inc
    1151
  - UART Control Register 3 (Uartx_C3)
    1152
  - UART Data Register (Uartx_D)
    1153
  - UART Match Address Registers 1 (Uartx_Ma1)
    1154
  - UART Match Address Registers 2 (Uartx_Ma2)
    1155
  - UART Control Register 5 (Uartx_C5)
    1156
  - UART Extended Data Register (Uartx_Ed)
    1157
  - UART Modem Register (Uartx_Modem)
    1158
  - UART Infrared Register (Uartx_Ir)
    1159
  - UART FIFO Parameters (Uartx_Pfifo)
    1160
  - K30 Sub-Family Reference Manual, Rev. 1.1, Dec
    1161
  - UART FIFO Status Register (Uartx_Sfifo)
    1162
  - UART FIFO Transmit Watermark (Uartx_Twfifo)
    1163
  - UART FIFO Transmit Count (Uartx_Tcfifo)
    1164
  - UART FIFO Receive Count (Uartx_Rcfifo)
    1165
  - Freescale Semiconductor, Inc
    1166
  - UART 7816 Interrupt Enable Register (Uartx_Ie7816)
    1167
  - UART 7816 Interrupt Status Register (Uartx_Is7816)
    1168
  - UART 7816 Wait Parameter Register (Uartx_Wp7816T0)
    1169
  - UART 7816 Wait Parameter Register (Uartx_Wp7816T1)
    1170
  - UART 7816 Wait FD Register (Uartx_Wf7816)
    1171
  - UART 7816 Transmit Length Register (Uartx_Tl7816)
    1172
  - UART CEA709.1-B Control Register 6 (Uartx_C6)
    1173
  - UART CEA709.1-B Packet Cycle Time Counter Low (Uartx_Pctl)
    1174
  - UART CEA709.1-B Secondary Delay Timer High (Uartx_Sdth)
    1175
  - UART CEA709.1-B Transmit Packet Length (Uartx_Tpl)
    1176
  - UART CEA709.1-B WBASE (Uartx_Wb)
    1177
  - UART CEA709.1-B Status Register (Uartx_S3)
    1178
  - UART CEA709.1-B Status Register (Uartx_S4)
    1179
  - UART CEA709.1-B Received Packet Length (Uartx_Rpl)
    1180
  - UART CEA709.1-B Received Preamble Length (Uartx_Rprel)
    1181
  - K30 Sub-Family Reference Manual, Rev. 1.1, Dec
    1182
  - Transmitter
    1183
  - Freescale Semiconductor, Inc
    1184
  - Receiver
    1185
    
    Freescale Semiconductor, Inc
    1186
    
    Freescale Semiconductor, Inc
    1187
    
    Freescale Semiconductor, Inc
    1188
    
    Freescale Semiconductor, Inc
    1189
    
    Freescale Semiconductor, Inc
    1190
    
    Freescale Semiconductor, Inc
    1191
    
    Freescale Semiconductor, Inc
    1192
    
    Freescale Semiconductor, Inc
    1193
    
    Freescale Semiconductor, Inc
    1194
    
    Freescale Semiconductor, Inc
    1195
    
    Freescale Semiconductor, Inc
    1196
    
    Freescale Semiconductor, Inc
    1197
    
    Freescale Semiconductor, Inc
    1198
    
    Freescale Semiconductor, Inc
    1199
    
    Freescale Semiconductor, Inc
    1200
    
    Freescale Semiconductor, Inc
    1201
    
    Freescale Semiconductor, Inc
    1202
    
    Freescale Semiconductor, Inc
    1203
    
    Freescale Semiconductor, Inc
    1204
    
    Freescale Semiconductor, Inc
    1205
    
    Freescale Semiconductor, Inc
    1206
  - Baud Rate Generation
    1207
    
    Freescale Semiconductor, Inc
    1208
    
    Freescale Semiconductor, Inc
    1209
    
    Freescale Semiconductor, Inc
    1210
    
    Freescale Semiconductor, Inc
    1211
  - Single-Wire Operation
    1212
  - Loop Operation
    1213
    
    Freescale Semiconductor, Inc
    1214
    
    Freescale Semiconductor, Inc
    1215
    
    Freescale Semiconductor, Inc
    1216
    
    Freescale Semiconductor, Inc
    1217
  - Infrared Interface
    1218
  - Reset
    1219
  - RXEDGIF Description
    1220
  - DMA Operation
    1221
  - ISO-7816 Initialization Sequence
    1222
    
    Freescale Semiconductor, Inc
    1223
    
    Freescale Semiconductor, Inc
    1224
  - Overrun (OR) Flag Implications
    1225
  - Overrun NACK Considerations
    1226
  - Match Address Registers
    1227
  - Irda Minimum Pulse Width
    1228
  - Legacy and Reverse Compatibility Considerations
    1229
  - K30 Sub-Family Reference Manual, Rev. 1.1, Dec
    1230
  - Introduction
    1231
  - Modes of Operation
    1232
Chapter 45 External Signals

1233
- Freescale Semiconductor, Inc
  1234
- SAI Transmit Control Register (I2Sx_Tcsr)
  1235
  - Freescale Semiconductor, Inc
    1236
  - Freescale Semiconductor, Inc
    1237
  - SAI Transmit Configuration 1 Register (I2Sx_Tcr1)
    1238
  - Freescale Semiconductor, Inc
    1239
  - SAI Transmit Configuration 3 Register (I2Sx_Tcr3)
    1240
  - SAI Transmit Configuration 4 Register (I2Sx_Tcr4)
    1241
  - SAI Transmit Configuration 5 Register (I2Sx_Tcr5)
    1242
  - SAI Transmit Data Register (I2Sx_Tdrn)
    1243
  - SAI Transmit Mask Register (I2Sx_Tmr)
    1244
  - SAI Receive Control Register (I2Sx_Rcsr)
    1245
    
    Freescale Semiconductor, Inc
    1246
    
    Freescale Semiconductor, Inc
    1247
  - SAI Receive Configuration 1 Register (I2Sx_Rcr1)
    1248
  - Freescale Semiconductor, Inc
    1249
  - SAI Receive Configuration 3 Register (I2Sx_Rcr3)
    1250
  - SAI Receive Configuration 4 Register (I2Sx_Rcr4)
    1251
  - SAI Receive Configuration 5 Register (I2Sx_Rcr5)
    1252
  - SAI Receive Data Register (I2Sx_Rdrn)
    1253
  - SAI Receive Mask Register (I2Sx_Rmr)
    1254
  - SAI MCLK Divide Register (I2Sx_Mdr)
    1255
  - K30 Sub-Family Reference Manual, Rev. 1.1, Dec
    1256
  - SAI Resets
    1257
  - Synchronous Modes
    1258
  - Frame Sync Configuration
    1259
  - Data FIFO
    1260
  - Word Mask Register
    1261
    
    Freescale Semiconductor, Inc
    1262
    
    Freescale Semiconductor, Inc
    1263
    
    Freescale Semiconductor, Inc
    1264
    
    Introduction
    1265
    
    Modes of Operation
    1266
  - Memory Map and Register Definition
    1267
- Freescale Semiconductor, Inc
  1268
Chapter 46

1269
- Port Data Output Register (Gpiox_Pdor)
  1269
- Port Clear Output Register (Gpiox_Pcor)
  1270
- Port Data Input Register (Gpiox_Pdir)
  1271
- General-Purpose Output
  1272
  - Introduction
    1273
  - K30 Sub-Family Reference Manual, Rev. 1.1, Dec
    1274
  - Electrode Capacitance Measurement Unit
    1275
  - Touch Detection Unit
    1276
  - TSI Disabled Mode
    1277
  - Block Diagram
    1278
  - TSI Signal Descriptions
    1279
  - General Control and Status Register (Tsix_Gencs)
    1280
    
    Freescale Semiconductor, Inc
    1281
    
    Freescale Semiconductor, Inc
    1282
    
    Freescale Semiconductor, Inc
    1283
  - SCAN Control Register (Tsix_Scanc)
    1284
  - Freescale Semiconductor, Inc
    1285
  - Pin Enable Register (Tsix_Pen)
    1286
  - Freescale Semiconductor, Inc
    1287
  - Wake-Up Channel Counter Register (Tsix_Wucntr)
    1288
  - Low-Power Channel Threshold Register (Tsix_Threshold)
    1289
    
    Freescale Semiconductor, Inc
    1290
    
    Freescale Semiconductor, Inc
    1291
    
    Freescale Semiconductor, Inc
    1292
  - TSI Measurement Result
    1293
  - Electrode Scan Unit
    1294
    
    Freescale Semiconductor, Inc
    1295
    
    Freescale Semiconductor, Inc
    1296
  - Touch Detection Unit
    1297
    
    Application Information
    1298
    
    K30 Sub-Family Reference Manual, Rev. 1.1, Dec
    1299
    
    Modes of Operation
    1300
    
    Block Diagram
    1301
  - LCD Signal Descriptions
    1302
Chapter 48

1303
- Lcd_P[63:0]
  1303
- LCD General Control Register (LCD_GCR)
  1304
  - Freescale Semiconductor, Inc
    1305
  - Freescale Semiconductor, Inc
    1306
  - Freescale Semiconductor, Inc
    1307
  - Freescale Semiconductor, Inc
    1308
  - LCD Auxiliary Register (LCD_AR)
    1309
  - Freescale Semiconductor, Inc
    1310
  - LCD Fault Detect Control Register (LCD_FDCR)
    1311
  - Freescale Semiconductor, Inc
    1312
  - LCD Fault Detect Status Register (LCD_FDSR)
    1313
  - LCD Pin Enable Register (Lcd_Penn)
    1314
  - LCD Back Plane Enable Register (Lcd_Bpenn)
    1315
  - LCD Waveform Register (LCD_WF7TO4)
    1316
  - LCD Waveform Register (LCD_WF11TO8)
    1317
  - LCD Waveform Register (LCD_WF15TO12)
    1318
  - LCD Waveform Register (LCD_WF23TO20)
    1319
  - LCD Waveform Register (LCD_WF31TO28)
    1320
  - LCD Waveform Register (LCD_WF35TO32)
    1321
  - LCD Waveform Register (LCD_WF43TO40)
    1322
  - K30 Sub-Family Reference Manual, Rev. 1.1, Dec
    1323
  - LCD Waveform Register (LCD_WF55TO52)
    1324
  - LCD Waveform Register (LCD_WF63TO60)
    1325
  - LCD Controller Driver Description
    1326
    
    Freescale Semiconductor, Inc
    1327
    
    Freescale Semiconductor, Inc
    1328
    
    Freescale Semiconductor, Inc
    1329
    
    Freescale Semiconductor, Inc
    1330
    
    Freescale Semiconductor, Inc
    1331
    
    Freescale Semiconductor, Inc
    1332
    
    Freescale Semiconductor, Inc
    1333
    
    Freescale Semiconductor, Inc
    1334
    
    Freescale Semiconductor, Inc
    1335
  - LCD Display Modes
    1336
  - Freescale Semiconductor, Inc
    1337
  - LCD Charge Pump and Power Supply Operation
    1338
    
    Freescale Semiconductor, Inc
    1339
    
    Freescale Semiconductor, Inc
    1340
    
    Freescale Semiconductor, Inc
    1341
    
    Freescale Semiconductor, Inc
    1342
    
    Resets
    1343
    
    Interrupts
    1344
    
    Freescale Semiconductor, Inc
    1345
    
    Freescale Semiconductor, Inc
    1346
    
    Freescale Semiconductor, Inc
    1347
    
    Freescale Semiconductor, Inc
    1348
    
    Freescale Semiconductor, Inc
    1349
    
    Freescale Semiconductor, Inc
    1350
    
    Initialization Section
    1351
  - Initialization Examples
    1352
    
    Freescale Semiconductor, Inc
    1353
    
    Freescale Semiconductor, Inc
    1354
    
    Freescale Semiconductor, Inc
    1355
    
    Freescale Semiconductor, Inc
    1356
    
    Freescale Semiconductor, Inc
    1357
    
    Application Information
    1358
  - LCD Seven Segment Example Description
    1359
    
    Freescale Semiconductor, Inc
    1360
    
    Freescale Semiconductor, Inc
    1361
  - LCD Contrast Control
    1362
    
    Freescale Semiconductor, Inc
    1363
    
    Freescale Semiconductor, Inc
    1364
    
    Introduction
    1365
    
    Features
    1366
    
    Freescale Semiconductor, Inc
    1367
    
    External Signal Description
    1368
    
    K30 Sub-Family Reference Manual, Rev. 1.1, Dec
    1369
  - Device Identification Register
    1370
    
    Functional Description
    1371
    
    Freescale Semiconductor, Inc
    1372
  - JTAGC Block Instructions
    1373
    
    Freescale Semiconductor, Inc
    1374
    
    Freescale Semiconductor, Inc
    1375
  - Boundary Scan
    1376
- Freescale Semiconductor, Inc
  1377

NXP Semiconductors Categories

Motherboard Microcontrollers Computer Hardware Control Unit Controller

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NXP Semiconductors MK30DX128VMC7 Manuals

NXP Semiconductors MK30DX128VMC7 Reference Manual (1377 pages)

Table of Contents

Chapter 1 About this Document

Chapter 2 Introduction

Chapter 3 Chip Configuration

Chapter 4 Aliased Bit-Band Regions

Chapter 5 Clock Distribution

Chapter 6 Reset and Boot

Chapter 7 Power Management

Chapter 8 Security

Chapter 9 References

Chapter 10 Signal Multiplexing and Signal Descriptions

Chapter 11 Port Control and Interrupts (PORT)

Chapter 12 System Integration Module (SIM)

Chapter 13

Chapter 14

Chapter 15 LVD Reset Operation

Chapter 17 Miscellaneous Control Module (MCM)

Chapter 18 Crossbar Switch (AXBS)

Chapter 19 Peripheral Bridge (AIPS-Lite)

Chapter 20 Direct Memory Access Multiplexer (DMAMUX)

Chapter 21 Direct Memory Access Controller (Edma)

Chapter 22 External Watchdog Monitor (EWM)

Chapter 23 Watchdog Timer (WDOG)

Chapter 24 Multipurpose Clock Generator (MCG)

Chapter 25 Oscillator (OSC)

Chapter 26 RTC Oscillator

Chapter 27 Flash Memory Controller (FMC)

Chapter 28 Flash Memory Module (FTFL)

Chapter 29

Chapter 30 Cyclic Redundancy Check (CRC)

Chapter 31 ADC Signal Descriptions

Chapter 32

Chapter 33

Chapter 35

Chapter 36 FTM Signal Descriptions

Chapter 16

Chapter 38 LPTMR Signal Descriptions

Chapter 49

Chapter 39

Chapter 40

Chapter 41 Flexcan Module Features

Chapter 42

Chapter 43

Chapter 44

Chapter 45 External Signals

Chapter 46

Chapter 48

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