Dma/Interrupt Request Select Register (Siu_Dirsr) - NXP Semiconductors MPC5644A Reference Manual

Field
NMI_SEL Non-Maskable Interrupt / Critical Interrupt Selection x
The SIU generates two specific sources of interrupt to the core. One of them is defined as the critical
interrupt (IVOR0 core exception) and the other is defined as the non-maskable interrupt (NMI) (IVOR1
core exception). The NMI_SEL bit selects which exception will be generated by the external NMI pin.
This bit is cleared only by a reset.
1: Critical interrupt (IVOR0) is enabled
0: NMI (IVOR1) is enabled
NMI_SEL0 Non-Maskable Interrupt / Critical Interrupt Selection x
The SIU generates two specific sources of interrupt to the core. One of them is defined as the critical
interrupt (IVOR0 core exception) and the other is defined as the non-maskable interrupt (NMI) (IVOR1
core exception). The NMI_SEL0 bit selects which exception will be generated by the SWT interrupt.
This bit is cleared only by a reset.
1: Critical interrupt (IVOR0) is enabled
0: NMI (IVOR1) is enabled
EIREx External DMA/Interrupt Request Enable x
This bit enables the assertion of a DMA or the interrupt request from the SIU to the interrupt controller
when an edge triggered event occurs on the IRQx inputs.
1: External interrupt request is enabled
0: External interrupt request is disabled
16.6.8

DMA/Interrupt Request Select Register (SIU_DIRSR)

The DMA/Interrupt Request Select Register allows selection between a DMA or interrupt request for
events on the IRQ[0:3] inputs.
SIU_BASE + 0x1C
0 1
R
0 0
W
Reset
0 0
16 17
R
0 0
W
Reset
0 0
= Unimplemented or Reserved
Figure 16-8. DMA/Interrupt Request Select Register (SIU_DIRSR)
Field
DIRSx DMA/Interrupt Request Select x
This bit selects between a DMA or interrupt request when an edge triggered event occurs on the
corresponding IRQx input.
1: DMA request is selected (on this device these DMA connections do not exist, causing the interrupt
to be inhibit)
0: Interrupt request is selected
Freescale Semiconductor
Table 16-11. SIU_DIRER field description
2 3 4 5 6
0 0 0 0 0
0 0 0 0 0
18 19 20 21 22
0 0 0 0 0
0 0 0 0 0
Table 16-12. SIU_DIRSR field description
MPC5644A Microcontroller Reference Manual, Rev. 6
Description
7 8 9 10 11
0 0 0 0 0
0 0 0 0 0
23 24 25 26 27
0 0 0 0 0
0 0 0 0 0
Description
System Integration Unit (SIU)
12 13 14 15
0 0 0 0
0 0 0 0
28 29 30 31
0 0 0 0
395