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8.3.2.11
eDMA Set START Bit Register (EDMA_SSBR)
The EDMA_SSBR provides a memory-mapped mechanism to set the START bit in the TCD of the given
channel. The data value on a register write causes the START bit in the corresponding transfer control
descriptor to be set. Setting bit 1 (SSB[0]) provides a global set function, forcing all START bits to be set.
Reads of this register return all zeroes.
If bit 0 is set, the SSB command is ignored. This allows multiple byte registers to be written as a 32-bit
word. Reads of this register return all zeroes.
Offset: EDMA_BASE + 0x001E
R
W
Reset
Field
NOP
No operation
0 Normal operation
1 No operation, ignore bits 1–7.
SSB[0:6]
Set START Bit (channel service request)
0–32 (64 for eDMA) Set the corresponding channel's TCD START bit.
64–127
8.3.2.12
eDMA Clear DONE Status Bit Register (EDMA_CDSBR)
The EDMA_CDSBR provides a memory-mapped mechanism to clear the DONE bit in the TCD of the
given channel. The data value on a register write causes the DONE bit in the corresponding transfer control
descriptor to be cleared. Setting bit 1 (CDSB[0]) provides a global clear function, forcing all DONE bits
to be cleared.
If bit 0 is set, the CDSB command is ignored. This allows multiple byte registers to be written as a 32-bit
word. Reads of this register return all zeroes.
Offset: EDMA_BASE + 0x001F
R
W
Reset
Figure 8-15. eDMA Clear DONE Status Bit Register (EDMA_CDSBR)
Freescale Semiconductor
0
1
2
NOP
0
0
0
Figure 8-14. eDMA Set START Bit Register (EDMA_SSBR)
Table 8-13. EDMA_SSBR field descriptions
Set all TCD START bits.
0
1
2
NOP
0
0
0
MPC5644A Microcontroller Reference Manual, Rev. 6
Enhanced Direct Memory Access Controller (eDMA)
Access: User write-only
3
4
5
SSB[0:6]
0
0
0
Description
Access: User write-only
3
4
5
CDSB[0:6]
0
0
0
6
7
0
0
6
7
0
0
159
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