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CLKOUT
ADDR[3:31]
RD_WR
BDIP
TS
DATA[0:31]
TA (Input)
CS[n]
WE[0:3]
The EBI drives address and control signals an extra cycle because it uses a latched
*
version of the external TA (1 cycle delayed) to terminate the cycle.
Figure 14-16. Single Beat 32-bit Write Cycle, Non-CS Access, Zero Wait States
14.5.2.4.3
Back-to-Back accesses
Due to internal bus protocol, one dead cycle is necessary between back-to-back external bus accesses that
are not part of a set of small accesses (see
length)
for small access timing). A dead cycle refers to a cycle between the TA of a previous transfer and
the TS of the next transfer.
In some cases, CS remains asserted during this dead cycle, such as the cases
of back-to-back writes or read-after-write to the same chip-select. See
Figure 14-20
Besides this dead cycle, in most cases, back-to-back accesses on the external bus do not cause any change
in the timing from that shown in the previous diagrams, and the two transactions are independent of each
other. The only exceptions to this are listed below:
•
Back-to-back accesses where the first access ends with an externally-driven TA or TEA. In these
cases, an extra cycle is required between the end of the first access and the TS assertion of the
second access. See
The following diagrams show a few examples of back-to-back accesses on the external bus.
Freescale Semiconductor
Section 14.5.2.6, Small accesses (Small port size and short burst
NOTE
and
Figure
14-21.
Section 14.5.2.8, Termination signals protocol
MPC5644A Microcontroller Reference Manual, Rev. 6
External Bus Interface (EBI)
*
DATA is valid
DATA is valid
for more details.
307
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