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Enhanced Direct Memory Access Controller (eDMA)
eDMA
eDMA engine
Bus read data
Bus write data
Bus address
*n = 32 (64 for eDMA) channels
8.5
Initialization / Application information
8.5.1
eDMA initialization
A typical initialization of the eDMA has the following sequence:
1. Write the EDMA_CR if a configuration other than the default is desired.
2. Write the channel priority levels into the EDMA_CPRn registers if a configuration other than the
default is desired.
3. Enable error interrupts in the EDMA_EEIRL and/or EDMA_EEIRH registers if desired.
4. Write the 32-byte TCD for each channel that may request service.
5. Enable any hardware service requests via the EDMA_ERQRH and/or EDMA_ERQRL registers.
6. Request channel service by software (setting bit EDMA_TCD[START]) or by hardware (slave
device asserting its DMA peripheral request signal).
After any channel requests service, a channel is selected for execution based on the arbitration and priority
levels written into the programmer's model. The DMA engine reads the entire TCD, including the primary
176
Transfer control descriptor
channel arbitration
Address
Data path
path
Figure 8-26. eDMA operation, Part 3
MPC5644A Microcontroller Reference Manual, Rev. 6
SRAM
(TCD)
SRAM
Program model/
Control
eDMA peripheral
eDMA done
request
Slave write address
Slave write data
TCD0
TCDn – 1*
Slave read data
Freescale Semiconductor
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