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Configurable Enhanced Modular IO Subsystem (eMIOS200)
If the up/down counter is selected by setting MODE[4] = 1, the counter changes direction at A1 match and
counts down until it reaches the value 0x1. After it has reached 0x1 it is set to count in up direction again.
The B1 register is used to generate a match in order to set the internal counter in up-count direction if
up/down mode is selected. Register B1 cannot be changed while this mode is selected.
Note that differently from the MC mode, the MCB mode counts between 0x1 and the A1 register value.
Only values greater than 0x1 must be written at A1 register. Loading values other than those leads to
unpredictable results. The counter cycle period is equal to A1 value in up counter mode. If in up/down
counter mode, the period is defined by the expression: (2*A1)-2.
Figure 22-26
describes the counter cycle for several A1 values. Register A1 is loaded with the A2 register
value at the cycle boundary. Thus any value written to the A2 register within cycle n will be updated to A1
at the next cycle boundary and therefore will be used on cycle n+1. The cycle boundary between cycle n
and cycle n+1 is defined as when the internal counter transitions from A1 value in cycle n to 0x1 in cycle
n+1. Note that the FLAG is generated at the cycle boundary and has a synchronous operation, meaning
that it is asserted one system clock cycle after the FLAG set event.
EMIOSCNT[n]
0x000007
0x000006
0x000005
0x000001
FLAG set event
FLAG pin/register
FLAG clear
A2 value
A1 value
0x000006
Prescaler ratio = 1
Figure 22-26. Modulus Counter Buffered (MCB) Up Count mode
Figure 22-27
describes the MCB in up/down counter mode (MODE[0:6] = 10101bb). The A1 register is
updated at the cycle boundary. If A2 is written in cycle n, this new value will be used in cycle n+1 for A1
match. Flags are generated only at A1 match start if MODE[5] is 0. If MODE[5] is set to 1 flags are also
generated at the cycle boundary.
672
cycle n
write to A2
match A1
write to A2
0x000005
0x000005
MPC5644A Microcontroller Reference Manual, Rev. 6
cycle n+1
cycle n+2
match A1
0x000007
0x000007
match A1
TIME
0x000007
Freescale Semiconductor
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