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Enhanced Time Processing Unit (eTPU2)
The Filter Delay varies with the filter clock (ETPU_ECR field FPSCK) and the filter mode used, as shown
in the
Table
24-58. For any given transition, it depends on the phase of the filter clock when the input
transition happens. In integration mode (TCRCLK filtering only), it also depends on the state of the
integrator counter. The Total Delay is defined as the number of system clock rising edges between the input
transition and the setting of TDLA/B, TCR1/2 incrementing, or EAC tooth sensing (TCRCLK) in angle
mode. The synchronizer delay is 2 or 3 system clocks, depending on the phase of the synchronizer when
the input transition happens. The edge detection takes 1 more system clock. The total delays are, thus:
Min. Total Delay = Min. Synchronizer Delay + Min. Filter Delay + Edge Detection Delay
Min. Total Delay = 3 + Min. Filter Delay
Max. Total Delay = Max. Synchronizer Delay + Max. Filter Delay + Edge Detection Delay
Max. Total Delay = 4 + Max. Filter Delay
The channel filters can be bypassed, so nullifying the filter delays in the equations above.
The channel output flip-flops drive the eTPU output signals directly, without any synchronous delays.
Consult the MCU Reference Manual for information on additional delays added at the integration.
24.7.2
Initialization code example
The code example below initializes ETPU_1 engine and configures eTPU UART FUNCTION to perform
the receiver at channel 1 and the transmitter at channel 0. The function works without parity and the data
word is 8 bits in size. The initialization code assumes the microcode function previously loaded into SCM.
***********************************************************************************
// Initilization program for eTPU engine 1, function microcode previously loaded into SCM.
// No angle mode, eTPU UART FUNCTION configured to perform at channels 0 and 1.
// Channel0 - Tx_UART
// Channel1 - Rx_UART
// UART Specifications:
// Data word size: 8 bits
// Parity: disabled
// ***************************** Definitions ***********************************
//Bases
#define ETPU_BASE
#define SPRAM_BASE
//General Configuration Registers
#define ETPU_MCR_OFFSET
#define ETPU_TBCR_1_OFFSET
#define ETPU_ECR_1_OFFSET
#define ETPU_CIER_1_OFFSET
#define ETPU_CDTRER_1_OFFSET
//channel0 configuration registers
#define ETPU_C0CR_1_OFFSET
#define ETPU_C0SCR_1_OFFSET
#define ETPU_C0HSRR_1_OFFSET
992
0x000 //MCU-dependent
0x000
//MCU-dependent
0x000
//Module Configuration Register
0x020
//Time Base Configuration Register
0x014
//Engine Configuration Register
0x240
//Channel Interrupt Enable Register
0x250
//Data TransF Interrupt Enable Register
0x400
//Channel0 Configuration Register
0x404
//Channel0 Status Control Register
0x408
//Channel0 Host Service Req. Register
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
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