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Reaction Module (REACM)
5. Hold-off timer bank data (see
(REACM_HOTBK))
6. Timer router data (see
7. ADC router data (see
The last action to perform is to enable the channel, after which the channel is able to respond to timer
signals and ADC data, thus able to perform modulation on the output pins. It is recommended to keep the
timer signals inactive until all data to all reaction channel modules are programmed and all channels have
been put in the enabled mode.
23.1.2.2
Low power mode
Coming out of reset all channels are in the disabled state. The channel may also be in low power mode
depending on a parameter that configures the initial state of the MDIS in the REACM module
configuration register (REACM_MCR) (see
may be disabled allowing for a low power state. The low power mode is controlled either by
REACM_MCR[MDIS] or by a global stop signal. There is no explicit clock gating implemented in
hardware within the reaction module.
Low power mode must be entered only when all channels are disabled by
REACM_CHCRn[CHEN] = 00.
23.1.2.3
Channel modes
After a channel is in enabled mode that channel is also said to be in the normal mode of operation, which
means it responds to timer signals from the timer inputs connected to the reaction module and also to ADC
results received from the on-chip ADC module. Channel outputs are controlled in accordance with those
inputs in order to perform an output modulation process. When performing a modulation the reaction
channel is said to be in the active state. The modes a reaction channel can be in and the ability to execute
a modulation related to the modes are:
•
Disabled: The channel cannot execute modulation.
•
Enabled: The channel is able to execute a modulation. It may be in the Active or Inactive state.
— Inactive state: The channel is not executing a modulation.
— Active state: The channel is executing a modulation.
23.1.2.4
Debug mode
The Reaction Module Debug operation is defined by bits FRZ and FREN in the REACM module
configuration register (REACM_MCR) (see
the timers in the Shared Time Bank and Hold-off Timers.
The module can enter debug mode either by software control or by the hardware debug input signal
controlled by the chip logic. In both cases the reaction module only enters debug mode if enabled by bit
REACM_MCR[FREN]:
•
If the FREN bit and the FRZ bit are both is asserted the module enters debug mode.
690
Section 23.3.11, REACM Hold-off Timer Bank Registers
Section 23.3.9, REACM Channel n Router Register
Section 23.3.4, REACM Threshold Router Register
Figure
23-4). If REACM_MCR[MDIS] = 1 the module clock
NOTE
Figure
23-4). In debug mode all timers are halted, including
MPC5644A Microcontroller Reference Manual, Rev. 6
(REACM_CHRRn))
(REACM_THRR))
Freescale Semiconductor
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