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Field
29
Reserved
30:31
External Bus Division Factor. The EBDF field specifies the frequency ratio between the system clock and
EBDF
CLKOUT. The EBDF field must not be changed during an external bus access or while an access is
pending.
00 External bus division factor = 1
01 External bus division factor = 2
10 Reserved
11 External bus division factor = 4
Note: The reset value of the EBDF field is divide-by-2. After reset, if EBDF is changed to divided-by-1,
no glitches occurs on the CLKOUT signal, but if EBDF is changed back to divide-by-2 or
divide-by-4, there is no guarantee that the switch will be glitchless.
16.6.27 Compare A High Register (SIU_CARH)
The SIU_CARH register holds the 32-bit value that is compared against the value in the SIU_CBRH
register. The CMPAH field is read/write and is reset by the IP Green-Line synchronous reset signal.
SIU_BASE + 0x988
0
1
R
W
Reset
0
0
16
17
R
W
Reset
0
0
= Unimplemented or Reserved
16.6.28 Compare A Low Register (SIU_CARL)
The SIU_CARL register holds the 32-bit value that is compared against the value in the SIU_CBRL
register. The CMPAL field is read/write and is reset by the IP Green-Line synchronous reset signal.
Freescale Semiconductor
Table 16-216. SIU_ECCR field description (continued)
2
3
4
5
6
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
Figure 16-212. Compare A High Register (SIU_CARH)
MPC5644A Microcontroller Reference Manual, Rev. 6
Description
7
8
9
10
11
CMPAH
0
0
0
0
0
23
24
25
26
27
CMPAH
0
0
0
0
0
System Integration Unit (SIU)
12
13
14
15
0
0
0
0
28
29
30
31
0
0
0
0
543
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