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Interrupt Controller (INTC)
Field
0–20 or
Vector table base address. Can be the base address of a vector table of addresses of ISRs. The VTBA
0–19
only uses the left-most 20 bits when the VTES bit in INTC_MCR is asserted.
VTBA
21–29 or
Interrupt vector. Vector of peripheral or software-configurable interrupt requests that caused the interrupt
20–28
request to the processor. When the interrupt request to the processor asserts, the INTVEC is updated,
INTVEC
whether the INTC is in software or hardware vector mode.
Note: If INTC_MCR[VTES] = 1, then the INTVEC field is shifted left one position to bits 20–28. VTBA is
then shortened by one bit to bits 0–19.
30–31 or
Reserved, must be cleared.
29–31
15.4.1.4
INTC End-of-Interrupt Register (INTC_EOIR)
Writing to the INTC_EOIR signals the end of the servicing of the interrupt request. When the INTC_EOIR
is written, the priority last pushed on the LIFO is popped into INTC_CPR. The values and size of data
written to the INTC_EOIR are ignored. The values and sizes written to this register neither update the
INTC_EOIR contents nor affect whether the LIFO pops. For possible future compatibility, write four bytes
of all 0's to the INTC_EOIR.
Reading the INTC_EOIR has no effect on the LIFO.
Address: Base + 0x0018 (INTC_EOIR)
0
1
R
0
0
W
RESET:
0
0
16
17
R
0
0
W
RESET:
0
0
= Unimplemented or Reserved
15.4.1.5
INTC Software Set/Clear Interrupt Registers INTC_SSCIR0_3 —
INTC_SSCIR4_7)
The INTC_SSCIRn supports the setting or clearing of software configurable interrupt requests. These
registers contain eight independent sets of bits to set and clear a corresponding flag bit by software. With
the exception of being set by software, this flag bit behaves the same as a flag bit set within a peripheral.
This flag bit generates an interrupt request within the INTC just like a peripheral interrupt request. Writing
a 1 to SETn leaves SETn unchanged at 0 but sets CLRn. Writing a 0 to SETn has no effect. CLRn is the
flag bit. Writing a 1 to CLRn clears it. Writing a 0 to CLRn has no effect. If a 1 is written to a pair SETn
and CLRn bits at the same time, CLRn is asserted, regardless of whether CLRn was asserted before the
write.
352
Table 15-5. INTC_IACKR Field Descriptions
2
3
4
5
6
0
0
0
0
0
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
0
0
0
0
0
Figure 15-11. INTC End-of-Interrupt Register (INTC_EOIR)
MPC5644A Microcontroller Reference Manual, Rev. 6
Description
7
8
9
10
11
0
0
0
0
0
0
0
0
0
0
23
24
25
26
27
0
0
0
0
0
0
0
0
0
0
Access: W/O
12
13
14
15
0
0
0
0
0
0
0
0
28
29
30
31
0
0
0
0
0
0
0
0
Freescale Semiconductor
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