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If it is required to more fully check the read path (in a diagnostic mode), it
is recommend that AIS be left at 0, to use the address sequence that checks
the read path more fully, and examine read transitions. This sequence takes
more time.
4. Seed the MISR UMISR0 through UMISR4 with desired values.
5. Set the UT0[AIE] bit.
a) If desired, the Array Integrity operation may be aborted prior to UT0[AID] going high. This
may be done by clearing the UT0[AIE] bit and then continuing to the next step. It should be
noted that in the event of an aborted array integrity check the MISR registers will contain a
signature for the portion of the operation that was completed prior to the abort, and will not be
deterministic. Prior to doing another array integrity operation, the UMISR0, UMISR1,
UMISR2, and UMISR3 registers may need to be initialized to the desired seed value by doing
register writes.
6. Wait until the UT0[AID] bit goes high.
7. Read values in the MISR registers (UMISR0 through UMISR4) to ensure correct signature.
8. Write a logic 0 to the UT0[AIE] bit.
12.4.4.2
Factory Margin Read
Factory Margin Read must be done following "Initial Factory Conditions". One Factory Margin Read is
allowed per erase.
Factory Margin Read may be done to selected and unlocked blocks by combining UT0[MRE] and
UT0[MRV] with the Array Integrity check. If UT0[MRE] is set, UT0[AIS] has no affect, and the reads
will be done sequentially.
The data to be read is customer specific, thus a customer can provide user code into the flash and the
correct MISR value is calculated. The customer is free to provide any random or non-random code, and a
valid MISR signature is calculated. Once the operations is completed, the results of the reads can be
checking by reading the MISR value. Factory Margin Read is a self timed event, and is independent of
system clocks, or wait states selected. Margin ECC corrections or detections are not done during the
Factory Margin Read test:
1. Enable UTest mode.
2. Select the block, or blocks to be receive margin read check by writing ones to the appropriate
registers in LMS or HBS/EHS registers. Make sure that selected blocks are also unlocked.
It is not possible to do UTest operations on the shadow block.
It is possible to do User Mode array reads during the Factory Margin Read
test, if desired, but the partition rules for Read While Write used during
program and erase are in effect during Factory Margin Reads.
3. Set the UT0[MRE] bit.
Freescale Semiconductor
NOTE
NOTE
MPC5644A Microcontroller Reference Manual, Rev. 6
Flash memory
247
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