NXP Semiconductors MPC5644A Reference Manual page 43

conversion on either ADC and start a Queue_0 conversion. This means that Queue_0 will always have a
deterministic time from trigger to start of conversion, irrespective of what tasks the ADCs were performing
when the trigger occurred. The eQADC supports software and external hardware triggers from other
blocks to initiate transfers of commands from the queues to the on-chip ADCs or to the external device. It
also monitors the fullness of command queues and result queues, and accordingly generates DMA or
interrupt requests to control data movement between the queues and the system memory, which is external
to the eQADC.
The ADCs also support features designed to allow the direct connection of high impedance acoustic
sensors that might be used in a system for detecting engine knock. These features include differential
inputs; integrated variable gain amplifiers for increasing the dynamic range; programmable pull-up and
pull-down resistors for biasing and sensor diagnostics.
The eQADC also integrates a programmable decimation filter capable of taking in ADC conversion results
at a high rate, passing them through a hardware low pass filter, then down-sampling the output of the filter
and feeding the lower sample rate results to the result FIFOs. This allows the ADCs to sample the sensor
at a rate high enough to avoid aliasing of out-of-band noise; while providing a reduced sample rate output
to minimize the amount DSP processing bandwidth required to fully process the digitized waveform.
The eQADC provides the following features:
• Dual on-chip ADCs
— 2  12-bit ADC resolution
— Programmable resolution for increased conversion speed (12-bit, 10-bit, 8-bit)
– 12-bit conversion time: 938 ns (1 M sample/sec)
– 10-bit conversion time: 813 ns (1.2 M sample/second)
– 8-bit conversion time: 688 ns (1.4 M sample/second)
— Up to 10-bit accuracy at 500 KSample/s and 8-bit accuracy at 1 MSample/s
— Differential conversions
— Single-ended signal range from 0 to 5 V
— Variable gain amplifiers on differential inputs (1, 2, 4)
— Sample times of 2 (default), 8, 64 or 128 ADC clock cycles
— Provides time stamp information when requested
— Allows time stamp information relative to eTPU clock sources, such as an angle clock
— Parallel interface to eQADC CFIFOs and RFIFOs
— Supports both right-justified unsigned and signed formats for conversion results
• 40 single-ended input channels, expandable to 56 channels with external multiplexers (supports
four external 8-to-1 muxes)
• 8 channels can be used as 4 pairs of differential analog input channels
• Differential channels include variable gain amplifier for improved dynamic range
• Differential channels include programmable pull-up and pull-down resistors for biasing and sensor
diagnostics (200 k100 k5 k
Freescale Semiconductor
MPC5644A Microcontroller Reference Manual, Rev. 6
Introduction
43