NXP Semiconductors MPC5644A Reference Manual page 966

Enhanced Time Processing Unit (eTPU2)
A HALT instruction placed after a no-flushing branch, dispatch or return
may be a problem from the debugger application standpoint: after the HALT
is executed, the eTPU debug interface informs the address of the
branch/dispatch/return destination, and the debugger application has no
direct way to identify which HALT instruction was executed, if multiple
HALTs lead to the same address. This can be solved if the debug support
block (NDEDI) has a register holding the address of the last instruction
executed, otherwise one should forbid non-flushed HALT instructions.
Software breakpoint setting and removal is possible only with SCM RAM implementations or ROM
implementations with SCM RAM emulation (see
one way of inserting software breakpoints into SCM RAM: writing bit VIS = 1 in register ETPU_MCR,
and then accessing SCM as an ordinary RAM from the slave bus. This can be done only if both engines
are halted or stopped.
24.5.10.2.6 Single-step execution
When microengine is already in halt_exec state, it can run the next microinstruction in the normal program
flow and get back to halt state. PC is incremented, or assigned the BAF value in a branch with satisfied
condition. Note that the executed instruction was already prefetched in the instruction pipeline, and a new
microinstruction is fetched during its execution. The prefetched instruction may be cleared during halt
state by the forced execution of a branch with flush (see
execution), making single-step execute a NOP instead of the next instruction in the program flow.
Single-step execution is controlled by the debug interface, and is a feature available from Nexus if eTPU
is connected to the NDEDI block.The single-step execution of a NOP instruction can be useful to control
input signal sampling and filtering, if signal ndedi_stop_pins = 1 at the Debug Interface. Single-step does
not happen if VIS = 1.
24.5.10.2.7 Forced microinstruction execution
When microengine is already in halt state (either halt_idle or halt_exec), it can run forced
microinstructions through the debug interface. This feature is available from Nexus if eTPU is connected
to the NDEDI block. The microinstruction, specified by the user, is not fetched from SCM and comes
directly from the debug interface. MDU start commands issued by forced instructions are executed, and
the MDU runs the operation until the end, independently of the halt state. The microinstruction field END
is ignored.
During forced execution of any instruction except Branches, Returns and Dispatches, the PC does not
change, and the prefetched instruction in the pipeline is bypassed, but not discarded. When halt state is
suspended, the prefetched instruction is executed and the instruction pointed by the PC is prefetched in
parallel (two-stage pipeline).
Forced execution of a Branch, Dispatch or Return loads the PC with the BAF field (if branch condition is
satisfied), PC+P or RAR, respectively. If branch condition is not satisfied, PC value stays unaltered. The
flush control (field FLS) also works, so that a successful forced branch with flush replaces the prefetched
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NOTE
Section 24.5.10.2.11, SCM
MPC5644A Microcontroller Reference Manual, Rev. 6
emulation). There is only
Section 24.5.10.2.7, Forced microinstruction
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