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Interrupt Controller (INTC)
Although the INTC supports 16 priorities, an ISR executing with PRI in the INTC_CPR equal to 15 is not
preempted. Therefore, the LIFO supports the stacking of 15 priorities. However, the LIFO is only 14
entries deep. An entry for a priority of 0 is not needed because of how pushing onto a full LIFO and
popping an empty LIFO are treated. If the LIFO is pushed 15 or more times than it is popped, the priorities
first pushed are overwritten. A priority of 0 is an overwritten priority. However, the LIFO pop zeros if it
is popped more times than it is pushed. Therefore, although a priority of 0 was overwritten, it is regenerated
with the popping of an empty LIFO.
The LIFO is not memory mapped.
15.5.3
Details on handshaking with processor
15.5.3.1
Software vector mode handshaking
15.5.3.1.1
Acknowledging interrupt request to processor
A timing diagram of the interrupt request and acknowledge handshaking in software vector mode, along
with the handshaking near the end of the interrupt exception handler, is shown in
examines the peripheral and software configurable interrupt requests. When it finds an asserted peripheral
or software configurable interrupt request with a higher priority than PRI in INTC current priority register
(INTC_CPR), it asserts the interrupt request to the processor. The INTVEC field in INTC interrupt
acknowledge register (INTC_IACKR) is updated with the preempting interrupt request's vector when the
interrupt request to the processor is asserted. The INTVEC field retains that value until the next time the
interrupt request to the processor is asserted. The rest of the handshaking is described in
Software vector
mode.
15.5.3.1.2
End-of-interrupt exception handler
Before the interrupt exception handling completes, INTC end-of-interrupt register (INTC_EOIR) must be
written. When it is written, the LIFO is popped so that the preempted priority is restored into PRI of the
INTC_CPR. Before it is written, the peripheral or software configurable flag bit must be cleared so that
the peripheral or software configurable interrupt request is negated.
To ensure proper operation across all Power Architecture MCUs, execute an
or
MBAR
write to the INTC_EOIR.
When returning from the preemption, the INTC does not search for the peripheral or software configurable
interrupt request whose ISR was preempted. Depending on how much the ISR progressed, that interrupt
request can no longer be asserted. When PRI in INTC_CPR is lowered to the priority of the preempted
ISR, the interrupt request for the preempted ISR or any other asserted peripheral or software configurable
interrupt request at or below that priority does not cause a preemption. Instead, after the restoration of the
preempted context, the processor returns to the instruction address that it was to next execute before it was
preempted. This next instruction is part of the preempted ISR or the interrupt exception handler's prolog
or epilog.
370
instruction between the access to clear the flag bit and the
MSYNC
MPC5644A Microcontroller Reference Manual, Rev. 6
NOTE
Figure
15-15. The INTC
Section 15.2.4.1,
Freescale Semiconductor
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