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External Bus Interface (EBI)
14.4.1.2
EBI Transfer Error Status Register (EBI_TESR)
EBI_BASE+0x8
0
1
R
0
0
W
RESET:
0
0
16
17
R
0
0
W
RESET:
0
0
= Unimplemented or Reserved
Figure 14-3. EBI Transfer Error Status Register (EBI_TESR)
The EBI Transfer Error Status Register contains a bit for each type of transfer error on the external bus. A
bit set to logic 1 indicates what type of transfer error occurred since the last time the bits were cleared.
Each bit can be cleared by reset or by writing a 1 to it. Writing a 0 has no effect.
This register may not be writable in Module Disable Mode due to the use of power saving clock modes,
e.g., a bus error can be generated on a timeout.
Table 14-6. EBI Transfer Error Status Register (EBI_TESR) Field Descriptions
Name
31
BMTF — Bus Monitor Timeout Flag
BMTF
This bit is set if the cycle was terminated by a bus monitor timeout.
1: Bus monitor timeout occurred
0: No error
288
2
3
4
5
6
0
0
0
0
0
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
0
0
0
0
0
MPC5644A Microcontroller Reference Manual, Rev. 6
7
8
9
10
11
0
0
0
0
0
0
0
0
0
0
23
24
25
26
27
0
0
0
0
0
0
0
0
0
0
Description
12
13
14
15
0
0
0
0
0
0
0
0
28
29
30
31
0
0
0
BMTF
0
0
0
0
Freescale Semiconductor
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