NXP Semiconductors MPC5644A Reference Manual page 655

22.4.3.4 eMIOS200 Channel Control Register (EMIOS_CCR[n])
Offset: UC[n] base address + 0x000C
0 1
R FREN ODIS
W
Reset 0 0
16 17
R 0 0 FORC
W
Reset 0 0
Figure 22-9. eMIOS200 Channel Control Register (EMIOS_CCR[n])
This register contains bits reflecting the status of channel input/output signals, the overflow condition of
the internal counter, and several read/write control bits for eMIOS channel n.
Field
FREN Freeze Enable
The FREN bit, if set and validated by bit EMIOS_MCR[FRZ], freezes all registers' values when in
debug mode, allowing the MCU to perform debug functions.
0 Normal operation
1 Freeze unified channel registers' values
ODIS Output Disable
The ODIS bit allows disabling the output pin when running any of the output modes with the
exception of GPIO mode.
0 The output pin operates normally.
1 The output pin is driven to the value in EDPOL for OPWFMB and OPWMB modes and to the
complement of EDPOL for other modes, but the channel continues to operate normally, that is,
it continues to produce FLAG and matches. When the selected output disable input signal is
negated, the output pin operates normally.
ODISSL Output Disable Select
The ODISSL bits select one of the four output disable input signals.
Freescale Semiconductor
2 3 4 5
ODISSL UCPRE UC
PREN
0 0 0 0
18 19 20 21
FORC 0 BSL
MA MB
0 0 0 0
Table 22-8. EMIOS_CCR field description
ODISSL
00
01
10
11
MPC5644A Microcontroller Reference Manual, Rev. 6
Configurable Enhanced Modular IO Subsystem (eMIOS200)
6 7 8 9 10
DMA 0
0 0 0 0 0
22 23 24 25 26
ED ED
SEL POL
0 0 0 0 0
Description
Input signal
Output disable input 0
Output disable input 1
Output disable input 2
Output disable input 3
Access: User read/write
11 12 13 14 15
IF FCK FEN 0
0 0 0 0 0
27 28 29 30 31
MODE
0 0 0 0 0
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