Optimizing For Instruction And Data Caches; Increasing Instruction Cache Performance; Data Cache And Buffer Operation Comparison For Intel® Sa-1110 And Intel Xscale - Intel PXA270 Optimization Manual

System Level Optimization
Table 3-4. Data Cache and Buffer Behavior when X = 1 (Sheet 2 of 2)
C B Cacheable?
1 0
1 1
† Normally, "bufferable" writes can coalesce with previously buffered data in the same address range
†† Refer to Intel XScale® Core Developer's Manual and the Intel® PXA27x Processor Family Developer's
Manual for a description of this register.
Note: The Intel XScale® Microarchitecture page-attributes are different than the Intel® StrongARM*
SA-1110 Microprocessor (SA-1110). The SA-1110 code may behave differently on PXA27x
processor systems due to page attribute differences.
encoding of the C and B bits for data accesses. The main difference occurs when cacheable and
nonbufferable data is specified (C=1, B=0); the SA-1110 uses this encoding for the mini-data cache
while the Intel XScale® Microarchitecture uses this encoding to specify write-through caching.
Another difference is when C=0, B=1, where the Intel XScale® Microarchitecture coalesces stores
in the write buffer; the SA-1110 does not.
Table 3-5. Data Cache and Buffer operation comparison for Intel® SA-1110 and Intel XScale®
Microarchitecture, X=0
Encoding
C=1,B=1
C=1,B=0
C=0,B=1
C=0,B=0
3.3

Optimizing for Instruction and Data Caches

Cache locking allows frequently used code to be locked in the cache. Up to 28 cache lines can be
locked in a set, while the remaining four entries still participate in the round robin replacement
policy.
3.3.1

Increasing Instruction Cache Performance

The performance of the PXA27x processor is highly dependent on the cache miss rate. Due to the
complexity of the processor fetching instructions from external memory can have a large latency.
Moreover, this cycle penalty becomes significant when the Intel XScale® core is running much
faster than external memory. Executing non-cached instructions severely curtails the processor's
performance so it is important to do everything possible to minimize cache misses.
3-4
Load Buffering
and Write
Coalescing?
(Mini-data
—
cache)
Y Y
SA-1110 Function
Cacheable in data cache; store misses can
coalesce in write buffer
Cacheable in mini-data cache; store misses
can coalesce in write buffer
Noncacheable; no coalescing in write buffer,
but can wait in write buffer
Noncacheable; no coalescing in the write
buffer, SA-110 stalls until this transaction is
done
Line Allocation
Write Policy
Policy
— —
Read/Write
Write-back
Allocate
Table 3-5 describes the differences in the
Intel XScale® Microarchitecture Function
Cacheable in data cache, store misses can
coalesce in write buffer
Cacheable in data cache, with a write-through
policy. Store misses can coalesce in write
buffer
Noncacheable; stores can coalesce in the write
buffer
Noncacheable, no coalescing in the write
buffer, Intel XScale® Microarchitecture stalls
until the operation completes.
Intel® PXA27x Processor Family Optimization Guide
Notes
Cache policy is determined by
MD field of Auxiliary Control
††
register