Busy-Waiting And Interrupts; Figure 8-8 Busy Waiting And Interrupts - ARM ARM926EJ-S Technical Reference Manual

Coprocessor Interface
8.6

Busy-waiting and interrupts

Coprocessor pipeline
CPLATECANCEL
8-10
The coprocessor is permitted to stall (busy-wait) the processor during the execution of
a coprocessor instruction if, for example, it is still busy with an earlier coprocessor
instruction. To do so, the coprocessor associated with the Decode stage instruction
drives WAIT on CHSDE[1:0]. When the instruction concerned enters the Execute stage
of the pipeline, the coprocessor can drive WAIT onto CHSEX[1:0] for as many cycles
as required to keep the instruction in the busy-wait loop.
For interrupt latency reasons the coprocessor might be interrupted while busy-waiting,
causing the instruction to be abandoned using CPPASS. The coprocessor must monitor
the state of CPPASS during every busy-wait cycle. If it is HIGH the instruction must be
executed. If it is LOW the instruction must be abandoned.
Figure 8-8 shows a busy-waited coprocessor instruction being abandoned due to an
interrupt.
Fetch
CLK
CPINSTR[31:0]
CPInstr
nCPMREQ
CPPASS
CHSDE[1:0]
CHSEX[1:0]
In Figure 8-8, CPLATECANCEL is also asserted as a result of the Execute
interruption.
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Execute Execute
Decode
(WAIT) (WAIT)
WAIT
WAIT

Figure 8-8 Busy waiting and interrupts

Execute Execute
(WAIT) interrupted
WAIT WAIT Ignored
ARM DDI0198D