Table B-7 Main Tlb Mapping To Mmuxwd - ARM ARM926EJ-S Technical Reference Manual

ARM DDI0198D
To read an entry from the 2-way main TLB, the entry must first be written using the
above instructions. The entry can then be read using the following instructions:
MRC p15, 4/5, <Rd>, c15, c2, 0 ; read tag main TLB
MRC p15, 4/5, <Rd>, c15, c4, 0 ; read PA/PROT main TLB
The data RAM attached to the main MMU is 112 bits wide. The mapping into the data
RAM for main TLB writes for the TAG is shown below and would appear on
MMUxWD[111:0] as shown in Table B-7.
During writes, the data is replicated so that each way receives the same copy of the data.
The exact way that is written and the exact index of the way is specified in the Test and
Debug Address Register.
Figure B-5 on page B-10 shows what happens during a write to the data RAM attached
to the main MMU.
Copyright © 2001-2003 ARM Limited. All rights reserved.
CP15 Test and Debug Registers

Table B-7 Main TLB mapping to MMUxWD

MMUxWD
Way
bits
1 [111:90]
[89:86]
[85:64]
[63:60]
[59:58]
[57]
[56]
0 [55:34]
[33:30]
[29:8]
[7:4]
[3:2]
[1]
[0]
Description
TAG[31:10]
Size of entry
PA[31:10]
Domain select [3:0]
AP[1:0]
Cachable bit
Bufferable bit
TAG[31:10]
Size of entry
PA[31:10]
Domain select [3:0]
AP[1:0]
Cachable bit
Bufferable bit
B-9