Table 2-13 Effects Of Control Register On Tcm Interface - ARM ARM926EJ-S Technical Reference Manual

Programmer's Model
TCM MMU
Instruction Disabled
TCM disabled
Instruction Disabled
TCM enabled
Instruction Disabled
TCM enabled
Instruction Enabled
TCM enabled
Data TCM Disabled
disabled
Data TCM Disabled
enabled
Data TCM Disabled
enabled
Data TCM Enabled
enabled
2-16
Effects of the Control Register on TCM interface
The M bit of the Control Register, when combined with the En bit in the respective TCM
region register c9, directly affects the TCM interface behavior, as shown in Table 2-13.
Cache Behavior
ICache All instruction fetches are from the external memory (AHB).
disabled
ICache All instruction fetches are from the TCM interface, or from external memory
disabled (AHB), depending on the setting of the base address in the instruction TCM
region register. No protection checks are made. All addresses are flat mapped.
That is, VA = MVA= PA.
ICache All instruction fetches are from the TCM interface, or from the ICache,
enabled depending on the setting of the base address in the Instruction TCM region
register. No protection checks are made. All addresses are flat mapped. That is,
VA = MVA= PA.
ICache All instruction fetches are from the TCM interface, or from the ICache/AHB
enabled interface, depending on the setting of the base address in the Instruction TCM
region register. Protection checks are made. All addresses are remapped from
VA to PA, depending on the page entry. That is, the VA is translated to an MVA,
and the MVA is remapped to a PA.
DCache All data accesses are to external memory (AHB).
disabled
DCache All data accesses are to the TCM interface, or to the external memory, depending
disabled on the setting of the base address in the data TCM region register. No protection
checks are made. All addresses are flat mapped. That is, VA = MVA= PA.
DCache All data accesses are to the TCM interface or to external memory, depending on
enabled the setting of the base address in the data TCM region register. All addresses are
flat mapped. That is, VA =MVA = PA.
DCache All data accesses are either from the TCM interface, or from the DCache/AHB
enabled interface, depending on the setting of the base address in the data TCM region
register. Protection checks are made. All addresses are remapped from VA to PA,
depending on the page entry. That is the VA is translated to an MVA, and the
MVA is remapped to a PA.
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Table 2-13 Effects of Control Register on TCM interface

ARM DDI0198D