Table 3-3 Interpreting First-Level Descriptor Bits [1:0] - ARM ARM926EJ-S Technical Reference Manual

Memory Management Unit
3.2.4 Section descriptor
31
3-10
Bits
Section Coarse Fine
[3:2] - -
- [3:2] [3:2]
[1:0] [1:0] [1:0]
The two least significant bits of the first-level descriptor indicate the descriptor type as
shown in Table 3-3.
Value Meaning
0 0 Invalid
0 1 Coarse page table
1 0 Section
1 1 Fine page table
A section descriptor provides the base address of a 1MB block of memory. Figure 3-5
shows the format of a section descriptor.
Section base address
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Table 3-2 First-level descriptor bits (continued)
Description
Bits C and B indicate whether the area of memory mapped
by this page is treated as write-back cachable, write-through
cachable, noncached buffered, or noncached nonbuffered.
Should Be Zero.
These bits indicate the page size and validity and are
interpreted as shown in Table 3-3.

Table 3-3 Interpreting first-level descriptor bits [1:0]

Description
Generates a section translation fault
Indicates that this is a coarse page table descriptor
Indicates that this is a section descriptor
Indicates that this is a fine page table descriptor
20 19 12 11 10 9 8
SBZ
5 4 3 2 1 0
S
AP B Domain 1 C B 1
Z
Figure 3-5 Section descriptor
ARM DDI0198D
0